WO2010133999A1

WO2010133999A1 - Test device to test the robustness of electronic circuits or devices

Info

Publication number: WO2010133999A1
Application number: PCT/IB2010/052080
Authority: WO
Inventors: Luigi Salvi
Original assignee: Euro Instruments S.R.L.
Priority date: 2009-05-21
Filing date: 2010-05-11
Publication date: 2010-11-25
Also published as: IT1394193B1; ITBS20090091A1

Abstract

The invention relates to a test device to test the robustness of electronic circuits or devices (DUT) towards electrical overstresses (Electrical Overstresses, EOS), comprising an electronic test board (12), an adapter circuit (14, 15) to which the DUT can be mounted acting as an interface between the DUT and the electronic test board so as to supply the DUT at least one electrical power supply signal and stimulation signals suitable to simulate the functioning of the DUT in different conditions of use. The electronic test board comprises at least one first EOS generator circuit (18) applicable to at least one electrical power supply signal of the DUT, a second EOS generator circuit (20) applicable to said stimulation signals, and a selection circuit (22) suitable to alternatively or contemporaneously operate said EOS generator circuits.

Description

DESCRIPTION

"Test device to test the robustness of electronic circuits or devices"

[0001] The present invention relates to techniques for checking the reliability of electronic circuits or devices and relates in particular to a test device to test the robustness of electronic circuits or devices (Device Under Test, hereinafter referred to for brevity as "DUT") towards electrical overstresses (hereinafter referred to for brevity as "EOS"), for example induced by system transients which may occur during the functioning of the electronic circuit or device.

[0002] As is known, electrical overstresses are a constant cause of failure in integrated circuits. It is estimated that about 40% of the failures found in integrated circuits can be attributed to EOS phenomena or events. [0003] In particular, for semiconductor devices, EOS events comprise a wide range of stresses of an electrical nature caused, for instance, by electromagnetic impulses (EMP) , system transients of various types (so called surge spikes on the input/output power lines) and electrostatic discharges (ESD) . In particular, the events of the last type of EOS occur for times ranging from 1 nanosecond to 1 microsecond and mainly during manufacturing and handling phases, that is when the device is not subject to electric polarisation.

[0004] The EOS events considered here belong to the family of system transients (on the input/output power lines).

In temporal terms these particular events can be defined as surge or overcurrent phenomena lasting between 1 microsecond and 1 millisecond and manifest themselves during functioning of the device.

[0005] The purpose of the present invention is to propose a device able to test the behaviour of electronic circuits or devices (DUT) towards electrical overstresses (EOS) , so as to assess the robustness/sensitivity of such circuits in normal functioning conditions of the application .

[0006] Such purpose is achieved by a device according to claim 1. The dependent claims describe preferred or advantageous embodiments of the test device.

[0007] The characteristics and advantages of the device according to the invention will in any case be evident from the description below made by way of a non-limiting example of its preferred embodiments with reference to the attached figures, wherein:

[0008] - Figure 1 shows an example of a test device according to the invention, in a practical embodiment;

[0009] - Figure 2 shows an example of a waveform of an electrical overstress (EOS) ; [0010] - Figure 3 shows the waveform of a positive EOS voltage peak;

[0011] - Figure 4 shows the waveform of a negative EOS- voltage peak; [0012] - Figure 5 shows an example of an EOS test sequence;

[0013] - Figure 6 is a functional block diagram of the test device;

[0014] - Figure 7 is a block diagram of the EOS generator circuit only;

[0015] - Figure 8 is a block diagram describing the EOS generator circuit in greater detail;

[0016] - Figure 9 is a block diagram of the selection circuit of the EOS generator circuits, called "EOS matrix";

[0017] - Figure 10 is a block diagram describing the EOS block matrix in greater detail;

[0018] - Figure 11 is a circuit diagram of the EOS generator circuit on the DUT power supplies; [0019] - Figures 12 and 13 show a circuit diagram of the

EOS generator circuit on dynamic signals, in two embodiments;

[0020] - Figure 14 is a circuit diagram of the EOS generator circuit on the monitoring signals; [0021] - Figure 15 is a circuit diagram of the EOS generator circuit on the static signals;

[0022] - Figure 16 is an embodiment of an electronic test circuit; and

[0023] - Figures 17 and 18 are two examples of adapter circuits for testing a DUT in different stimulation conditions .

[0024] Figure 1 shows in its entirety a test device 10 for testing the behaviour of electronic circuits or devices (DUT) towards electrical overstresses 1 (Electrical Overstresses, EOS) according to the invention.

[0025] According to a general embodiment, the test device 10 comprises an electronic test board 12 and at least one adapter circuit 14, 15 on which at least one DUT 16 is applicable. The adapter circuit 14, 15 acts as an interface betwen the DUT and the electronic test board 10 to provide the DUT with at least one electrical power supply signal 2 and stimulation signals 4 suitable to stimulate the functioning of the DUT in different conditions of use. [0026] The electronic test board 12 comprises at least a first EOS generator circuit 18 applicable at least to an electrical power supply signal of the DUT, a second EOS generator circuit 20 ^' applicable to the stimulation signals, and a selection circuit 22, hereinafter referred to as "EOS matrix", suitable to activate alternatively or contemporaneously said EOS generator circuits. [0027] According to one embodiment, the adapter circuit 14, 15 is also configured to provide monitoring signals 24 of the behaviour of the DUT towards the overstresses . In this case, the electronic test board comprises a third EOS generator circuit 19 applicable to said monitoring signals 24. Advantageously, said third generator circuit 19 is also controlled by the selection circuit 22. [0028] The stimulation signals 4 to subject the DUT so as to simulate functioning in different configurations or situations of use may be static and/or dynamic, digital or analogic signals. In particular, advantageously, the electrical overstress may be applied in a stimulation configuration of the DUT by a dynamic signal overlapping the static signal.

[0029] The device according to the invention is therefore able to test the behaviour of the device stressed by electrical overstresses applied on the power supply and signal lines. The term signal lines, to which the stimulation signals are applied, refers in particular to the input/output lines (I/O) 28.

[0030] In particular, such electrical overstresses take the form of impulse signals, also known as "spikes" (see figures 2 and 5) which simulate transient events and the electrical features of which (amplitude, width, period) are programmable and can be configured by a computerised application. In addition, such impulse signals may be positive or negative in relation to the nominal voltage of the DUT. [0031] With reference to figure 3 showing the characteristic parameters of a positive EOS, one example of an EOS impulse has the following characteristics:

[0032] - Absolute amplitude (a) : from OV to 60V

[0033] - Under-elongation (uv) (compared to EOS amplitude EOS) : 10%;

[0034] - Rise time (ts) : 2V/μs;

[0035] - Fall time (td) : 2V/μs;

[0036] - Pulse width (Ii) on the power supply lines

(Programmable): from 5μs to 200μs; [0037] - Pulse width (Ii) on the signals (Programmable) : from 5μs to 500μs;

[0038] - Waiting time (that is the time between trigger command and the rising front of the EOS in synchronous mode) : lμs. [0039] With reference to figure 4 showing the typical parameters of a negative EOS, one example of an EOS has the following characteristics:

[0040] - Absolute amplitude (a) : da OV a 60V

[0041] - Relative amplitude (ar) : 20V; [0042] - Over-voltage (ov) (compared to EOS amplitude) : 10 % ;

[0043] - Rise time (ts) : 2V/μs; [0044] - Fall time (td) : 2V/μs;

[0045] - Pulse width (Ii) on the power supply lines (Programmable) : from 5μs to 200μs;

[0046]- Pulse width (Ii) on the signals (Programmable): from 5μs to 500μs;

[0047] - Waiting time (that is the time between trigger command and the rising front of the EOS in synchronous mode) : lμs .

[0048] Advantageously, the EOS may be synchronous with the stimulation sequence of the DUT, or asynchronous, for example generated randomly by a computer. [0049] According to a preferred embodiment, each adapter circuit 14, 15 is detachably applicable to the electronic test board by means of at least one electric connector 30. In fact, as will be described better below, different adapter circuits 14, 15 can be mounted on the same test board 12 to simulate different functioning configurations, for example static and dynamic, of the DUT.

[0050] According to one embodiment, the first EOS generator circuit 18 is configured so as to inject a voltage peak 1 directly onto the power supply line 6 of the DUT. For this reason, advantageously, a protection inductor 32 of the DUT (Figure 11) is inserted between the power supply and the DUT.

[0051] As regards however the generation of EOS on the dynamic 4 and/or monitoring 24 stimulation signals, on account of the high frequencies at play, the electronic test board is provided with a switch 34 able to switch between said dynamic or monitoring stimulation signals and the generation circuits of EOS 19, 20. [0052] As regards the generation of EOS on the static stimulation signals 4', these may advantageously be defined by a pull-up or pull-down resistor 36 connected to the DUT and positioned on the adapter circuit. In this case, the electronic test board is provided, for each static simulation signal, with a switch or relay 38 able to communicate between said static stimulation signal and the second EOS generation circuit. The position of the switches 38, and therefore the configuration of the test board, is, for example, determined at the beginning of the test . [0053] Advantageously, the EOS generator circuits and the selection circuit are managed by a control logic 40 which can be configured by a computer 44. The latter is, in addition, used to configure and programme the electrical parameters of the EOS to monitor the behaviour of the DUT subjected to EOS. [0054] According to one advantageous embodiment, the device can be set in such a way as to power the DLJT at a number of different voltage levels, for example four. It is, in addition, also possible to conduct digital stimulation and monitor the signals of interest.

[0055] For example, the device comprises four programmable power supply units and the DUT can be stressed with voltage peaks on the terminations of the DUT relative to the power supplies and to the signals. [0056] The voltage peaks may be of positive or negative polarity, with reference to the voltage level of the DUT. [0057] A practical embodiment of a test device according to the invention as illustrated in figure 1 will now be¹ described. [0058] The test device 10 includes the following instrumentation :

[0059] [0059] - Six programmable power supply units 1001 to supply the power for the tests; [0060]- one PSU (Power Supply Unit,) of (±15V, ±5V, +12V) to supply power to the system;

[0061] - a cardframe developed on a PXI platform (Peripheral Component Interconnect (PCI) extension for Instrumentation) 1004 configured to stimulate and monitor the DUT devices during the ^'tests; [0062] - a personal computer 44 integrated in the cardframe PXI to manage the various device functions;

[0063] - an Uninterrupted Power Supply f 1100VA to maintain the power supply of the computer and the instrumentation 1002; [0064] - a Backplane Board to enable rapid connection of the instrumentation 1002;

[0065] - a sliding drawer 1003 to house the circuits needed for the tests.

[0066] All the settings of the test device relative to the tests to be. performed on the DUT can be programmed using a software user interface and saved in a recipe, thanks to the presence of a computer 44 managing all the parameters .

[0067] The electronic test board 12 comprises a mother board which contains all the electronics needed to perform the EOS tests and therefore generate the voltage peaks. The DUT 16 can be housed inside a dedicated adapter 14, 15, which contains the electronics needed to perform the dynamic tests and is therefore designed to the specifications of the HTOL circuits (High Temperature

Operating Life), and/or static tests, in which case it is configured HTRB (High Temperature Reverse Bias).

[0068] The resources available for stimulation of the DUT are as follows: [0069] - four power supply channels, to which EOS is not appl ied ;

[0070] - four power supply channels, to which EOS may be applied;

[0071] - eight digital stimuli, with the possibility of applying EOS, scalable up to a maximum of 128 channels;

[0072] - two analogic stimuli, with the possibility of applying EOS;

[0073]- eight monitoring channels, with the possibility of applying EOS; [0074] - fifty static levels, with the possibility of applying EOS.

[0075] Figure 5 shows an example of a test sequence with voltage peaks of different amplitude.

[0076] During a series of EOS tests the configuration of the mother board 12 is modified by the relays 42 to select each termination of the DUT and apply the voltage peaks to it and for the period of adjustment all the signals and power supplies must be disabled to prevent damage to the device. [0077] Figure 6 shows a functional block diagram of the test device in its entirety. The heart of the device is the EOS generator circuit 18-20 and the selection matrix

22 of the EOS to apply. Such circuits are managed by a control logic 40, in turn operated by a personal computer 44. The latter also controls the stimuli 4, 4' to subject the DUT to and receives the monitoring signals 24 from the DUT.

[0078] As shown in figure 7, the EOS generator circuit comprises an EOS generator circuit on the power supplies 18 and an EOS generator circuit on the signals 20.In turn, each of said circuits comprises a sub-circuit 18a for the positive EOS, with relative discharge circuit 18b, and a sub-circuit for the negative EOS 18c, with relative discharge circuit 18d. Each sub-circuit for generation of the EOS, comprises a section of charge pump 18e, an applications section of the EOS 18f, and a control section of the level of the EOS 18g. Each discharge circuit comprises a discharge control section 18h and a discharge circuit 18i (figure 8) . [0079] As mentioned above, the matrix EOS 22 represents the part of the system which enables selection of the EOS test mode, making it possible to apply the voltage peaks to different types of signals, as shown in the block diagram in figure 9. The EOS matrix comprises four sub- blocks: a first sub-block 22a for the selection of the EOS on the power supplies, a second sub-block 22b for the selection of the EOS on the dynamic signals, a third sub- block 22c for the selection of the EOS on the static signals, and a fourth sub-block 22d for the selection of the EOS on the monitoring. [0080] Each of said sub-blocks contains dedicated circuitry, which will be described below in more detail, and which is shown in the block diagram in figure 10 in its general form. [0081] EOS on the power supplies

[0082] The circuitry dedicated to application of the EOS to the power supply terminations of the DUT is structured so as to inject the voltage peak directly onto the power supply line 6; for this reason an inductor 32, is inserted between the power supply and the DUT so as to protect the DUT (figure 11) .

[0083] The inductance value may be chosen depending on the test characteristics; if the test requires sudden current variations, the oscillations felt by the power supply can be mitigated by selecting an appropriate Cin capacity on the adapter of the DUT. [0084] EOS on dynamic signals

[0085] The circuitry relative to the dynamic signals 4 applicable to the input/output terminals 28 of the DUT makes it possible to achieve frequencies to the order of 50MS/s (Mega Samples per second) ; consequently, in this case it is impossible to maintain inductance in series and a relay 34 must be inserted to switch from the digital signal to the EOS generation circuitry. The user may also select a static level 4', if necessary, and add the voltage peak to this.

[0086] Figure 13 shows an alternative implementation of the circuit in figure 12, making it possible to apply the spike to a digital stimulation circuit 4 without interrupting functioning, as is needed rather in the circuit in figure 12. By means of this configuration the digital stimulation can be supplied indirectly, protecting the stimulation circuit 4 in relation to the circuit which the spike 1 comes from. [0087] EOS on monitoring

[0088] The circuitry for the generation of EOS on the terminals of the monitoring signals 24 in output to the DUT works in a similar way to that of the digital signals. So, in this case too a relay 34 is present which switches from the monitoring signal to the generation circuitry of the EOS.

[0089] It should be noted that when the user sets an EOS on a monitoring signal, acquisition is stopped and resumes subsequent to generation of the EOS. [0090] EOS on static signals

[0091] In reliability tests of the static type, or on static signals during dynamic tests, the DUT 28 may need static levels, typically obtained by means of pull-up or pull-down resistors 36, which in this case must be positioned on the adapter 14 of the DUT. As happens for the EOS on the power supplies the switching of the relays

38 must occur subsequent to turning off all the signals.

[0092] Mother board

[0093] Figure 16 shows the layout of a motherboard 12 of the device according to the invention. Note:

[0094] - a first circuit area 18 dedicated to generating the EOS on the power supplies;

[0095] - a second circuit area 20 dedicated to generating the EOS on the signals; [0096] - a third circuit area 22 implementing the EOS matrix;

[0097] - the drivers of the relays 42, that is the circuits piloting opening and closing of the relays 42;

[0098] - the peak measurement devices 48 of the EOS impulses, making it possible to measure the level reached by the spike;

[0099] - a test area 50 able to receive the adapters for the tests of static and dynamic EOS.

[00100] The mother board 12 handling sorting of all the signals to the connector 30 of the adapter 14, 15, designed in a dedicated manner for each device.

[00101] Mother board adapters

[00102] Since the EOS tests can be performed in various stimulation configurations of the device, it is advantageous to use special adapters 14, 15 to mount on the mother board 12.

[00103] Figures 17 and 18 shows examples of the adapters 14, 15 for tests in HTRB (High Temperature Riverse Bias) and HTOL (High Temperature Operating Life) configurations respectively.

[00104] The adapter 14 for tests in HTRB conditions provides for application of the EOS to the power supplies, static signals and monitoring. [00105] The adapter 15 for tests in HTOL conditions provides for application of the EOS stress to power supplies, dynamic signals and monitoring.

[00106] However, specific adapters may be defined based on the user's needs. [00107] In short, the test device according to the invention comprises a generator circuit of system transient type overpressures (EOS) able to apply positive and negative stresses of system transients to all the input/output terminals (I/O) of a device or circuit subjected to testing (DUT), to the power supply lines and monitoring lines, both in static conditions, that is with electrically polarised DUT in stand-by not traversed by significant current, and dynamic conditions, that is with the DUT completely operative, with the possibility of managing powered ohm-inducing charges. [00108] In particular, the solution of the device described herein is able to operate in dynamic High Temperature Operating Life (HTOL) and static High Temperature Reverse Bias (HTRB) conditions. [00109] The solution proposed here makes it possible for the designer to test the circuit protection used in the DUT circuit in relation to the system transients (EOS) , so as to define the application limits or margins in relation to such EOS events. [00110] The solution described may also be included in a production control programme in real time, so as to enable intervention during the testing phase on production lots of the said product.

[00111] A person skilled in the art may make modifications, adaptations and replacements of elements with other functionally equivalent, to the embodiments of the test device according to the invention so as to satisfy contingent requirements while remaining within the sphere of protection of the following claims. Each of the characteristics described as belonging to a possible embodiment may be made independently of the other embodiments described.

Claims

1. Test device to test the behavior of circuits or electronic devices (DUT) (EOS), comprising:

- an electronic test board (12); - an adapter circuit (14, 15) on which the DUT is mountable and which acts as interface between the DUT and the electronic test board in order to provide to DUT at least an electrical power supply signal and stimulation signals suitable to simulate the operation of the DUT in different conditions of use, wherein said electronic test board comprises at least a first EOS generator circuit (18) applicable at least to an electrical power supply signal of DUT, a second EOS generator circuit (20) applicable to said stimulation signals, and a selection circuit (22) suitable to activate said EOS generator circuits alternatively or contemporaneously.

2. Device according to claim 1, wherein the adapter circuit (14, 15) is configured to provide also signals (24) monitoring the behavior of the DUT subjected to overstresses, and wherein the electronic test board includes a third EOS generator circuit (19) applicable to said monitoring signals, said third generator circuit being controlled by the selection circuit.

3. Device according to claims 1 or 2, wherein said stimulation signals are static and/or dynamic signals, digital or analogic signals.

4. Device according to anyone of the previous claims, wherein said second EOS generator circuit is electrically connectable to I/O lines of DUT.

5. Device according to anyone of previous claims, wherein the EOS generation circuit on stimulation signals is configured in order to apply EOS in a synchronous way with reference to the stimulation frequency.

6. Device according to anyone of the claims 1-4, wherein the of generation circuit on stimulation signals is configured in order to apply EOS in a random asynchronous way with reference to the stimulation frequency.

7. Device according to anyone of the previous claims, wherein the adapter circuit is applicable to the electronic test board in a movable way trough an electronic connector (30).

8. Device according to anyone of the previous claims, wherein the first EOS generator circuit is configured in order to inject a voltage peak directly on the power supply line of DUT.

9. Device according to claim 8, where an inductor (32), that protects the DUT, is inserted between the power supply and the DUT.

10. Device according to anyone of the previous claims, wherein the electronic test board is provided, for any signal of dynamic stimulation or monitoring, with a switch (34) suitable to switch over between said signal of dynamic stimulation or monitoring and the second EOS generator circuit.

11. Device according to anyone of the previous claims, wherein the signals of static stimulation are obtained with at least a pull-up or pull-down resistor (36), connected to the DUT and situated on the adapter circuit, and where the electronic test board is provided, for any static stimulus signal, with a switch (38), suitable to switch over between said static stimulation signal and the second EOS generator circuit.

12. Device according to anyone of the previous claims, wherein EOS generator circuits and the selection circuit are managed by a control logic, that can be configured by a computer.

13. Device according to anyone of the previous claims, comprising a computer for configuration and programming of the EOS electrical parameters and for the monitoring of the behavior of the DUT subjected to EOS.