WO2010133925A1 - Procédé d'enseignement pour un nano-bloc neuronal - Google Patents

Procédé d'enseignement pour un nano-bloc neuronal Download PDF

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Publication number
WO2010133925A1
WO2010133925A1 PCT/IB2009/053528 IB2009053528W WO2010133925A1 WO 2010133925 A1 WO2010133925 A1 WO 2010133925A1 IB 2009053528 W IB2009053528 W IB 2009053528W WO 2010133925 A1 WO2010133925 A1 WO 2010133925A1
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conductor
value
correction step
potential
potential applied
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PCT/IB2009/053528
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English (en)
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Jacques-Olivier Klein
Eric Belhaire
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Universite Paris Sud (Paris 11)
Centre National De La Recherche Scientifique - Cnrs
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Priority to PCT/IB2009/053528 priority Critical patent/WO2010133925A1/fr
Publication of WO2010133925A1 publication Critical patent/WO2010133925A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons

Definitions

  • the invention relates to a neuronal nano-block and to a teaching method for such neuronal nano-block.
  • Using nanocomponents in electronic circuit is considered as a solution to overcome the end of Moore's law.
  • Figure 1 represents a neuronal nano-block structure comprising two pairs of pre-synaptic conductors 12, 14; 16, 18 linked to four post-synaptic conductors 201, 202, 203, 204.
  • Each pre-synaptic conductor 12, 14; 16, 18 is linked to the four post-synaptic conductors 201, 202, 203, 204 by a plurality of synapses 221, 241, 261, 281; 222, 242, 262, 282; 223, 243, 263, 283; 224, 244, 264, 284, each synapse comprising a nanoconductor .
  • each post-synaptic conductor 201, 202, 203, 204 is linked to a neuron cell 301, 302, 303, 304.
  • the potential of each post-synaptic conductor 201, 202, 203, 204 corresponds to the linear contribution of each input potential ViI, Vi2, Vi3, Vi4.
  • Equation (1) expresses the potential y x of the postsynaptic conductor j : with X 1 the input potential of the pre-synaptic conductor i and W 1 -, the conductance of the nanoconductor linking the pre-synaptic conductor i with the post-synaptic conduct or j .
  • Neuron cells 301, 302, 303, 304 correspond to a nonlinear decision operator, for example sigmoid, sign or stepwise function.
  • Each neuron cell requires a plurality of synapses, therefore it appears that it is important to reduce the size of synapses, for example packing them in high-density arrays .
  • Such resistive elements can be considered as nanoconductor for the synapse.
  • one of the main challenges is to find a teaching method for assembly of such elements.
  • Such teaching method consists in tuning the synapses in particular the nanoconductors so as to have the neuronal nano-block execute a desired logical function.
  • the current teaching methods require selective addressing of synaptic connections in order to proceed to the teaching steps. This constrains to add selection devices, for example transistors, in the nanocomponent array and leads to an important loss in terms of integration density.
  • One goal of the present invention consists in providing a neuronal nano-block and a teaching method for such neuronal nano-block that do not comprise such drawbacks, in particular that do not require an individual access to each synapse during the teaching steps.
  • one subject of the invention is a teaching method for a neuronal nano-block, the neuronal nano-block comprising at least one pair of pre-synaptic conductors linked to at least one post-synaptic conductor by a plurality of synapses, each synapse comprising an adjustable nanoconductor, wherein the value of the conductance of each adjustable nanoconductor is unchanged when the absolute value of the potential applied to said nanoconductor is smaller than or equal to a threshold value Vt, at least one end of the post-synaptic conductor being linked to a neuron cell, wherein the teaching method comprises:
  • a sign determining step S2 in which the measured sign of the measured potential Vm of the post-synaptic conductor is measured
  • a comparison step S3 in which the measured sign of the measured potential Vm of the post-synaptic conductor is compared to the desired sign of the desired potential Vd of the post-synaptic conductor according to the input potentials
  • a teaching step S4 in which at least one or a combination of the following correction steps is carried out:
  • a correction step CSl in which a negative teaching potential VpI is applied to the post synaptic conductor when the measured sign is negative while the desired sign is positive,
  • ⁇ a correction step CS2 in which a positive teaching potential Vp2 is applied to the post synaptic conductor when the measured sign is negative while the desired sign is positive, with the proviso that this step is not carried out simultaneously with the proceeding correction step CSl
  • ⁇ a correction step CS3 in which a negative teaching potential VpI is applied to the post synaptic conductor when the measured sign is positive while the desired sign is negative
  • 4 a correction step CS4 in which a positive teaching potential Vp2 is applied to the post synaptic conductor when the measured sign is positive while the desired sign is negative, with the proviso that this step is not carried out simultaneously with the proceeding correction step CS3;
  • a correction step CS5 in which the sign of each input potential applied to said at least one pair of pre-synaptic conductors is changed; and wherein the absolute value of the teaching potential is greater than or equal to the threshold value Vt and the potential of each synapse is considered positive when the potential of the pre-synaptic conductor is greater than the potential of the post-synaptic conductor.
  • the teaching method according to the invention does not require individual access to each synapse.
  • a block of interconnected synaptic devices can be trained by controlling the voltage of the post and pre-synaptic conductors.
  • each synapse comprises an adjustable nanoconductor having a conductance that:
  • each synapse comprises an adjustable nanoconductor having a conductance that: • increases when the value of the potential applied to said conductor is smaller than or equal to a first negative threshold value VtI,
  • each synapse comprises an adjustable nanoconductor having a conductance that: • increases when the value of the potential applied to said conductor is smaller than or equal to a first negative threshold value VtI,
  • each synapse comprises an adjustable nanoconductor having a conductance that: • decreases when the value of the potential applied to said conductor is smaller than or equal to a first negative threshold value VtI,
  • each synapse comprises an adjustable nanoconductor having a conductance that is stable when the value of the potential applied to said conductor is smaller than or equal to a positive threshold value Vt and increases when the value of the potential applied to said conductor is greater than said threshold value Vt, and during the teaching step the correction step CSl, the correction step CS5 and the correction step CS3 are carried out;
  • each synapse comprises an adjustable nanoconductor having a conductance that is stable when the value of the potential applied to said conductor is greater than or equal to a negative threshold value Vt and increases when the value of the potential applied to said conductor is smaller than said threshold value Vt, and during the teaching step the correction step CS4, the correction step CS5 and correction step CS2 are carried out;
  • each synapse comprises an adjustable nanoconductor having a conductance that is stable when the value of the potential applied to said conductor is greater than or equal to a negative threshold value Vt and decreases when the value of the potential applied to said conductor is smaller than said threshold value Vt, and during the teaching step the correction step CS2, the correction step CS5 and correction step CS4 are carried out;
  • each synapse comprises an adjustable nanoconductor having a conductance that is stable when the value of the potential applied to said conductor is smaller than or equal to a positive threshold value Vt and decreases when the value of the potential applied to said conductor is greater than said threshold value Vt, and during the teaching step the correction step CS3, the correction step CS5 and correction step CSl are carried out;
  • each synapse comprises an adjustable nanoconductor having a conductance that:
  • each synapse comprises an adjustable nanoconductor having a conductance that
  • the invention also relates to a neuronal nano-block comprising :
  • each synapse comprising an adjustable nanoconductor, wherein the value of the conductance of each adjustable nanoconductor is unchanged when the absolute value of the potential applied to each nanoconductor is smaller than or equal to a threshold value Vt, at least one end of the post-synaptic conductor being linked to a neuron cell, wherein the neuron cell is configured so as to: • compare the measured sign of the measured potential Vm of the post-synaptic conductor with the desired sign of the desired potential Vd of the post-synaptic conductor according to the signs of input potentials applied to the at least one pair of pre-synaptic conductors,
  • a correction step CSl in which a negative teaching potential VpI is applied to the post synaptic conductor when the measured sign is negative while the desired sign is positive,
  • a correction step CS2 in which a positive teaching potential Vp2 is applied to the post synaptic conductor when the measured sign is negative while the desired sign is positive,
  • a correction step CS3 in which a negative teaching potential VpI is applied to the post synaptic conductor when the measured sign is positive while the desired sign is negative,
  • a correction step CS4 in which a positive teaching potential Vp2 is applied to the post synaptic conductor when the measured sign is positive while the desired sign is negative; 4 a correction step CS5, in which the sign of each input potential applied to the at least one pair of pre-synaptic conductors is changed, and wherein the absolute value of the teaching potential is greater than or equal to the threshold value Vt and the potential of each synapse is considered positive when the potential of the pre-synaptic conductor is greater than the potential of the post-synaptic conductor.
  • each synapse comprises an adjustable nanoconductor having a conductance that:
  • each synapse comprises an adjustable nanoconductor having a conductance that:
  • the neuron cell is configured to execute the correction step CS3, the correction step CS4, the correction step CS5, the correction step CSl and the correction step CS2;
  • each synapse comprises an adjustable nanoconductor having a conductance that: • increases when the value of the potential applied to said conductor is smaller than or equal to a first negative threshold value VtI,
  • each synapse comprises an adjustable nanoconductor having a conductance that:
  • each synapse comprises an adjustable nanoconductor having a conductance that is stable when the value of the potential applied to said conductor is smaller than or equal to a positive threshold value Vt and increases when the value of the potential applied to said conductor is greater than said threshold value Vt, and the neuron cell is configured to execute the correction step CSl, the correction step CS5 and the correction step CS3;
  • each synapse comprises an adjustable nanoconductor having a conductance that is stable when the value of the potential applied to said conductor is greater than or equal to a negative threshold value Vt and increases when the value of the potential applied to said conductor is smaller than said threshold value Vt, and the neuron cell is configured to execute the correction step CS4, the correction step CS5 and correction step CS2;
  • each synapse comprises an adjustable nanoconductor having a conductance that is stable when the value of the potential applied to said conductor is greater than or equal to a negative threshold value Vt and decreases when the value of the potential applied to said conductor is smaller than said threshold value Vt, and the neuron cell is configured to execute the correction step CS2, the correction step CS5 and correction step CS4;
  • each synapse comprises an adjustable nanoconductor having a conductance that is stable when the value of the potential applied to said conductor is smaller than or equal to a positive threshold value Vt and decreases when the value of the potential applied to said conductor is greater than said threshold value Vt, and the neuron cell is configured to execute the correction step CS3, the correction step CS5 and correction step CSl;
  • each synapse comprises an adjustable nanoconductor having a conductance that:
  • each synapse comprises an adjustable nanoconductor having a conductance that:
  • the invention further relates to a neuron cell arranged to be linked to a post-synaptic conductor of a neuronal nano-block comprising: • at least one pair of pre-synaptic conductors linked to at least one post-synaptic conductor by a plurality of synapses, each synapse comprising an adjustable nanoconductor , wherein the value of the conductance of each adjustable nanoconductor is unchanged when the absolute value of the potential applied to each nanoconductor is smaller than or equal to a threshold value Vt, wherein said neuron cell is configured so as to: • compare the measured sign of the measured potential Vm of the post-synaptic conductor with the desired sign of the desired potential Vd of the post-synaptic conductor according to the signs of input potentials applied to the at least one pair of pre-synaptic conductors,
  • a correction step CSl in which a negative teaching potential VpI is applied to the post synaptic conductor when the measured sign is negative while the desired sign is positive,
  • a correction step CS2 in which a positive teaching potential Vp2 is applied to the post synaptic conductor when the measured sign is negative while the desired sign is positive,
  • ⁇ a correction step CS3 in which a negative teaching potential VpI is applied to the post synaptic conductor when the measured sign is positive while the desired sign is negative
  • 4 a correction step CS4 in which a positive teaching potential Vp2 is applied to the post synaptic conductor when the measured sign is positive while the desired sign is negative
  • ⁇ a correction step CS5 in which the sign of each input potential applied to the at least one pair of pre-synaptic conductors is changed, and wherein the absolute value of the teaching potential is greater than or equal to the threshold value Vt and the potential of each synapse is considered positive when the potential of the pre-synaptic conductor is greater than the potential of the post-synaptic conductor.
  • the invention relates to a computer program product comprising one or more stored sequence of instruction that is accessible to a processor and which, when executed by the processor, causes the processor to carry out at least one, for example all, of the steps of the method according to the invention.
  • the invention also relates to a computer readable medium carrying one or more sequences of instructions of the computer program according to the invention.
  • FIG. 1 is a schematic representation of a neuronal nano-block comprising four neuron cells
  • FIGS. 2a to 2j are schematic representations of the varation of conductance of different nanoconductors that may be used in a neuronal nano-block according to the invention
  • FIG. 3 is a schematic representation of a neuronal nano-block according to the invention
  • - Figure 4 is a schematic representation of a neuron cell according to a first embodiment of the invention.
  • FIG. 5 is a schematic representation of a neuron cell according to a second embodiment of the invention .
  • resistive elements can be used as nanoconductor for the synapses of neuronal nano-blocks.
  • the inventors have classified adjustable nanoconductors having such non-volatile resistive memories and multilevel capabilities into different classes represented on Figures 2. Each adjustable nanoconductor has been classified depending on how the potential applied to it controls the conductance change.
  • the non-volatile feature of the conductance implies that the conductance of the adjustable nanoconductor remains stable for a potential applied to the nanoconductor comprised in an operating range including 0 Volt.
  • the value of the conductance of each adjustable nanoconductor is unchanged when the absolute value of the potential applied to the nanoconductor is smaller than or equal to a threshold value Vt.
  • Vt defines a maximum operating range [-Vt; Vt] .
  • the potential applied to each nanoconductor should remains inside the maximum operating range to keep unaffected the programmed function of the neuronal nano-block.
  • the conductance is affected.
  • the conductance may increase or decrease depending on the potential polarity applied and the nanoconductor .
  • Figure 2a represents the variation of the conductance of a nanoconductor having a conductance that: • decreases (-) when the value of the potential applied to said nanoconductor is smaller than or equal to a first negative threshold value VtI,
  • Such nanoconductor is classified as "-0+” nanoconductor to summarize the effect of the potential applied to said nanoconductor on the conductance change.
  • Figure 2b represents the variation of the conductance of a nanoconductor having a conductance that:
  • Such nanoconductor is classified as "+0-" nanoconductor to summarize the effect of the potential applied to said nanoconductor on the conductance change.
  • Figure 2c represents the variation of the conductance of a nanoconductor having a conductance that: • increases (+) when the value of the potential applied to said conductor is smaller than or equal to a first negative threshold value VtI,
  • Such nanoconductor is classified as "+0+” nanoconductor to summarize the effect of the potential applied to said nanoconductor on the conductance change.
  • Figure 2d represents the variation of the conductance of a nanoconductor having a conductance that:
  • Such nanoconductor is classified as "-0-" nanoconductor to summarize the effect of the potential applied to said nanoconductor on the conductance change.
  • Figure 2e represents the variation of the conductance of a nanoconductor having a conductance that is stable (0) when the value of the potential applied to said conductor is smaller than or equal to a positive threshold value Vt and increases ( + ) when the value of the potential applied to said conductor is greater than said threshold value Vt.
  • Such nanoconductor is classified as "0+” nanoconductor to summarize the effect of the potential applied to said nanoconductor on the conductance change.
  • Figure 2f represents the variation of the conductance of a nanoconductor having a conductance that is stable (0) when the value of the potential applied to said conductor is greater than or equal to a negative threshold value Vt and increases ( + ) when the value of the potential applied to said conductor is smaller than said threshold value Vt.
  • Such nanoconductor is classified as "+0" nanoconductor to summarize the effect of the potential applied to said nanoconductor on the conductance change.
  • Figure 2g represents the variation of the conductance of a nanoconductor having a conductance that is stable (0) when the value of the potential applied to said conductor is greater than or equal to a negative threshold value Vt and decreases (-) when the value of the potential applied to said conductor is smaller than said threshold value Vt.
  • Such nanoconductor is classified as "-0" nanoconductor to summarize the effect of the potential applied to said nanoconductor on the conductance change.
  • Figure 2h represents the variation of the conductance of a nanoconductor having a conductance that is stable (0) when the value of the potential applied to said conductor is smaller than or equal to a positive threshold value Vt and decreases (-) when the value of the potential applied to said conductor is greater than said threshold value Vt.
  • Such nanoconductor is classified as "0-" nanoconductor to summarize the effect of the potential applied to said nanoconductor on the conductance change.
  • the conductance change is electrically irreversible because only one direction is available, either increase or decrease of the conductance. Consequently, this device can only be programmed once, unless another mean, for example temperature or light, can be used to reset the programmed devices.
  • the inventors have defined two more classes of adjustable nanoconductor, having two positive and two negative threshold values of potential for each polarity enable to switch between increase and decrease of the conductance without any change in the voltage polarity.
  • Figure 2i represents the variation of the conductance of a nanoconductor having a conductance that: • is stable (0) when the value of the potential applied to said conductor is comprised between a first positive threshold value VtI and a second negative threshold value Vt2,
  • Such nanoconductor is classified as "-+0+-" nanoconductor to summarize the effect of the potential applied to said nanoconductor on the conductance change.
  • Figure 2j represents the variation of the conductance of a nanoconductor having a conductance that: • is stable (0) when the value of the potential applied to said conductor is comprised between a first positive threshold value VtI and a second negative threshold value Vt2, • increases (+) when the value of the potential applied to said conductor is greater than or equal to a third positive threshold value Vt3 or when the value of the potential applied to said conductor is smaller than or equal to a fourth negative threshold value Vt4, • decreases (-) when the value of the potential applied to said conductor is comprised between the values of said first and third threshold values VtI, Vt3 or when comprised between the values of said second and fourth threshold values Vt2, Vt4.
  • Such nanoconductor is classified as "+-0-+” nanoconductor to summarize the effect of the potential applied to said nanoconductor on the conductance change.
  • FIG. 3 illustrates an architecture of a neuronal nano-block according to the invention.
  • the nano-block represented on figure 3 comprising a one pair of pre-synaptic conductors 12, 14; 16, 18 linked to a post-synaptic conductor 20 by a plurality of synapses 22, 24, 26, 28.
  • Each synapse comprises an adjustable nanoconductor.
  • the adjustable nanoconductors are selected from the nanoconductor represented on figures 2a to 2j.
  • each pair of pre-synaptic conductors is linked to a switching device configured to switch a differential signal voltage representing an input potentials of each conductor of the pair of pre-synaptic conductors.
  • a switching device configured to switch a differential signal voltage representing an input potentials of each conductor of the pair of pre-synaptic conductors.
  • the end of the post-synaptic conductor 20 is linked to a neuron cell 30.
  • the neuron cell 30 is configured so as to execute a teaching method according to the invention.
  • the teaching method comprises:
  • ViI, Vi2, Vi3, Vi4 are applied to the pairs of pre-synaptic conductors 12, 14, 16, 18.
  • the sign determining step S2 the measured sign of the measured potential Vm of the post-synaptic conductor
  • the measured sign of the measured potential Vm of the post-synaptic conductor 20 is compared to the desired sign of the desired potential Vd of the post-synaptic conductor
  • the teaching step S4 may comprise at least one, for example two, or a combination of the following correction steps:
  • a correction step CSl in which a negative teaching potential VpI is applied to the post synaptic conductor 20 when the measured sign is negative while the desired sign is positive,
  • a correction step CS2 in which a positive teaching potential Vp2 is applied to the post synaptic 20 conductor when the measured sign is negative while the desired sign is positive, with the proviso that this step is not carried out simultaneously with the proceeding correction step CSl,
  • a correction step CS3 in which a negative teaching potential VpI is applied to the post synaptic conductor 20 when the measured sign is positive while the desired sign is negative,
  • a correction step CS4 in which a positive teaching potential Vp2 is applied to the post synaptic conductor 20 when the measured sign is positive while the desired sign is negative, with the proviso that this step is not carried out simultaneously with the proceeding correction step CS3;
  • the nanoconductors 22, 24, 26, 28 may be a "-0+" type. According to such embodiment, during the teaching step the correction step CSl, the correction step CS2, the correction step CS5, the correction step CS3 and the correction step CS4 are carried out successively.
  • the invention further relates to a neuron cell 30 configured to execute successively the correction step CSl, the correction step CS2, the correction step CS5, the correction step CS3 and the correction step CS4.
  • the nanoconductors 22, 24, 26, 28 may be a "+0-" type. According to such embodiment, during the teaching step the correction step CS3, the correction step CS4, the correction step CS5, the correction step CSl and the correction step CS2 are carried out successively.
  • the invention further relates to a neuron cell 30 configured to execute successively the correction step CS3, the correction step CS4, the correction step CS5, the correction step CSl and the correction step CS2.
  • the nanoconductors 22, 24, 26, 28 may be a "+0+" type.
  • the correction step CS2 and the correction step CS3 are carried out.
  • the correction steps may be carried out successively or simultaneously.
  • Advantageously carrying out the correction steps simultaneously allows reducing the teaching time of the neuronal nano-block.
  • the invention further relates to a neuron cell 30 configured to execute successively or simultaneously the correction step CS2, and the correction step CS3.
  • the nanoconductors 22, 24, 26, 28 may be a "-0-" type.
  • the correction step CSl, and the correction step CS4 are carried out during the teaching step.
  • the correction steps may be carried out successively or simultaneously.
  • Advantageously carrying out the correction steps simultaneously allows reducing the teaching time of the neuronal nano-block.
  • the invention further relates to a neuron cell 30 configured to execute successively or simultaneously the correction step CSl, and the correction step CS4.
  • the nanoconductors 22, 24, 26, 28 may be a "0+" type.
  • the correction step CSl the correction step CS5 and the correction step CS3 are carried out successively.
  • the invention further relates to a neuron cell 30 configured to execute successively the correction step CSl, the correction step CS5 and the correction step CS3.
  • the nanoconductors 22, 24, 26, 28 may be a "+0" type.
  • the correction step CS4 the correction step CS5 and correction step CS2 are carried out successively.
  • the invention further relates to a neuron cell 30 configured to execute successively the correction step CS4, the correction step CS5 and correction step CS2.
  • the nanoconductors 22, 24, 26, 28 may be a "-0" type.
  • the correction step CS2 the correction step CS5 and correction step CS4 are carried out successively.
  • the invention further relates to a neuron cell 30 configured to execute successively the correction step CS2, the correction step CS5 and correction step CS4.
  • the nanoconductors 22, 24, 26, 28 may be a "0-" type. According to such embodiment, during the teaching step the correction step CS3, the correction step CS5 and correction step CSl are carried out successively.
  • the invention further relates to a neuron cell 30 configured to execute successively the correction step CS3, the correction step CS5 and correction step CSl.
  • the nanoconductors 22, 24, 26, 28 may be a "-+0+-" type.
  • the correction step CSl, and the correction step CS4 are carried out, with the absolute value of the teaching potential greater than or equal to the largest absolute value of the third and fourth threshold values Vt3, Vt4.
  • the correction steps may be carried out successively or simultaneously. Advantageously carrying out the correction steps simultaneously allows reducing the teaching time of the neuronal nano-block.
  • the invention further relates to a neuron cell 30 configured to execute successively or simultaneously the correction step CSl, and the correction step CS4.
  • the nanoconductors 22, 24, 26, 28 may be a "+-0-+" type.
  • the correction step CS2, and the correction step CS3 are carried out, with the absolute value of the teaching potential greater than or equal to the largest absolute value of the third and fourth threshold values Vt3, Vt4.
  • the correction steps may be carried out successively or simultaneously. Advantageously carrying out the correction steps simultaneously allows reducing the teaching time of the neuronal nano-block.
  • the invention further relates to a neuron cell 30 configured to execute successively or simultaneously the correction step CS2, and the correction step CS3.
  • FIG. 4 An example of a neuron cell structure is illustrated on figure 4.
  • the neuron cell 30 represented on figure 4 is linked to a post-synaptic conductor via the conductor 31.
  • the conductor 31 is connected to an analog switch 40 controlled by the teaching potential T.
  • the analog switch 40 is linked to a threshold device 42.
  • the threshold device 42 is arranged to compare the value of the received post-synaptic potential with a predetermined value.
  • the value of the potential delivered by the threshold device 42 corresponds to the measured potential Vm and depends on the result of said comparison.
  • the measured potential is inputted in an inverter 44 linked to a NOR gate 46 and an AND gate 48.
  • the NOR 46 and AND 48 gates also receive as input signals the desired value Vd of the post-synaptic potential and a first command signal VcI.
  • the NOR 46 and AND 48 gates are linked to a second NOR gate 52.
  • the second NOR gate is linked to a second analog switch 40.
  • the second analog switch 40 receives a reference signal Vref and a second command signal VcI.
  • the second analog switch 54 is linked to the first analog switch 40.
  • a neuron cell having the architecture represented on figure 4 is arranges so as to execute the correction steps CSl to CS4 of a method according to the invention.
  • the person skilled in the art may select the correction steps CSl to CS4 he wishes to carry out.
  • the correction step CS5 may be carried out by using means to change the sign of each input potential ViI, Vi2, Vi3, Vi4 applied to the pairs of pre-synaptic conductors 12, 14, 16, 18.
  • Figure 5 illustrates a representation of a neuron cell arranged so as to execute the correction steps CSl to CS4 according to the invention.
  • the neuron cell 30 represented on figure 5 is linked to a post-synaptic conductor via the conductor 31.
  • the conductor 31 is connected to a threshold device 42.
  • the threshold device 42 is arranged to compare the value of the received post-synaptic potential with a predetermined value.
  • the value of the potential delivered by the threshold device 42 corresponds to the measured potential Vm and depends on the result of said comparison.
  • the measured potential is inputted in a first AND gate 56 and in an inverter (not represented) linked to a second AND gate 58.
  • the desired post-synaptic potential is inputted directly in the second AND gate 58 and inputted in the first AND gate 56 via an inverter (not represented) .
  • the first AND gate 56 is linked to a third 60 and a fourth 62 AND gate.
  • the second AND gate 58 is linked to a fifth 64 and a sixth 66 AND gate.
  • the third 60, fourth 62, fifth 64 and sixth 66 AND gates receive as input signal control signal VCl, VC2, VC3, and VC4 that allow controlling the correction step to be carried out.
  • the third 60 and fifth 64 AND gates are linked to a first OR gate 68.
  • the fourth 62 and the sixth 66 AND gates are linked to a second OR gate 70.
  • the first and second OR gates are linked to CMOS switch or transistors 72 and 73 respectively.
  • the CMOS switches or transistors 72 and 73 are linked to the conductor 31.
  • a neuron cell having the architecture represented on figure 5 is arranges so as to execute the correction steps CSl to CS4 of a method according to the invention.
  • the correction step CS5 requires the use of means to change the sign of each input potential ViI, Vi2, Vi3, Vi4 applied to the pairs of pre-synaptic conductors 12, 14, 16, 18.

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Abstract

L'invention porte sur un procédé d'enseignement pour nano-bloc neuronal (10) comprenant : • une étape de comparaison dans laquelle on compare le signe mesuré du potentiel mesuré Vm du conducteur post-synaptique (20) avec le signe désiré du potentiel désiré Vd du conducteur post-synaptique (20) selon des potentiels d'entrée (ViI, Vi2, Vi3, Vi4) appliqués à la paire de conducteurs pré-synaptiques (12, 14, 16, 18), • une étape d'enseignement S4 dans laquelle on exécute des étapes de correction au moyen d'une impulsion de tension vers le conducteur post-synaptique.
PCT/IB2009/053528 2009-05-20 2009-05-20 Procédé d'enseignement pour un nano-bloc neuronal WO2010133925A1 (fr)

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US11270194B2 (en) 2017-07-26 2022-03-08 International Business Machines Corporation System and method for constructing synaptic weights for artificial neural networks from signed analog conductance-pairs of varying significance
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US11915132B2 (en) 2017-11-20 2024-02-27 International Business Machines Corporation Synaptic weight transfer between conductance pairs with polarity inversion for reducing fixed device asymmetries

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