WO2010129065A2 - Amplificateur à gain variable - Google Patents

Amplificateur à gain variable Download PDF

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Publication number
WO2010129065A2
WO2010129065A2 PCT/US2010/001363 US2010001363W WO2010129065A2 WO 2010129065 A2 WO2010129065 A2 WO 2010129065A2 US 2010001363 W US2010001363 W US 2010001363W WO 2010129065 A2 WO2010129065 A2 WO 2010129065A2
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WO
WIPO (PCT)
Prior art keywords
amplifier
resistance
stage
control signal
feedback
Prior art date
Application number
PCT/US2010/001363
Other languages
English (en)
Other versions
WO2010129065A3 (fr
Inventor
Krishna Shivaram
Kashif A. Ahmed
Original Assignee
Mindspeed Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/387,826 external-priority patent/US7973602B2/en
Priority claimed from US12/387,824 external-priority patent/US7948323B2/en
Application filed by Mindspeed Technologies, Inc. filed Critical Mindspeed Technologies, Inc.
Publication of WO2010129065A2 publication Critical patent/WO2010129065A2/fr
Publication of WO2010129065A3 publication Critical patent/WO2010129065A3/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45098—PI types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/453—Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45522—Indexing scheme relating to differential amplifiers the FBC comprising one or more potentiometers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45528—Indexing scheme relating to differential amplifiers the FBC comprising one or more passive resistors and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45618—Indexing scheme relating to differential amplifiers the IC comprising only one switch
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45702—Indexing scheme relating to differential amplifiers the LC comprising two resistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45728—Indexing scheme relating to differential amplifiers the LC comprising one switch
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3084—Automatic control in amplifiers having semiconductor devices in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves

Definitions

  • the invention relates to transimpedance amplifiers and in particular to a method and apparatus for increasing dynamic range, linearity, and stability of a transimpedance amplifier.
  • FIG. 1 illustrates an example environment of use.
  • an optical fiber 100 provides an optical signal to a photodetector 104.
  • the photodetector 104 converts the optical signal to a low power electrical current.
  • the output from the photodetector 104 feeds into an amplifier 108, which increases the power level of the input to a level suitable for downstream processing and decoding.
  • One type of amplifier often utilized for this application is a transimpedance amplifier (TIA), which is a low noise current to voltage amplifier.
  • TIA transimpedance amplifier
  • the output of the amplifier 108 feeds into an equalizer 112.
  • the equalizer 112 comprises an electronic dispersion compensation (EDC) equalizer configured to correct for known signal dispersion: within the fiber.
  • EDC electronic dispersion compensation
  • the EDC equalizer is configured with a transfer function inverse to that of the optical fiber to thereby reverse the effects of the fiber.
  • the equalizer 112 For the equalizer 112 to accurately reverse the dispersive effects of the fiber channel, it is essential for the signal presented to the equalizer to be an accurate amplification of the signal from the fiber 100. As a result, it is essential for the amplifier 108 to have excellent linearity, avoid clipping, and otherwise be free from unwanted distortion.
  • the equalizer is primarily configured to combat dispersion and as a result, distortion introduced by the amplifier 108 can not be corrected by the equalizer.
  • an amplifier having an input configured to receive an input signal and having a degeneration resistance.
  • the amplifier also includes an amplifier feedback loop configured to receive a control signal such that the control signal controls the feedback resistance which in turn controls the gain of the amplifier.
  • a replica circuit configured to replicate the amplifier and amplifier feedback loop to thereby create a feedback resistance in the replica circuit.
  • a replica circuit feedback loop configured to alter the degeneration resistance in relation to the feedback resistance in the replica circuit.
  • the replica circuit may be a scaled version of the amplifier and the feedback loop.
  • the control signal comprises an automatic gain control signal.
  • the amplifier may comprise a transimpedance amplifier.
  • a current mirror may be part of the replica circuit feedback loop.
  • the amplifier feedback loop may further comprise a FET switch configured to receive the control signal and the replica circuit feedback loop further comprises a FET switch configured to alter the degeneration resistance in relation to the feedback resistance in the replica circuit.
  • Also disclosed herein is a method for maintaining linearity in an amplifier comprising receiving an input signal at an input of an amplifier and then amplifying the input signal with the amplifier.
  • the amplifier further comprises a feedback resistance and a degeneration resistance.
  • This method then creates a feedback resistance in a replica circuit such that the replica circuit is a replica of the amplifier and the feedback resistance.
  • the feedback resistance may comprise a ratio or be related to the feedback resistance in the amplifier.
  • This method creates a degeneration resistance control signal based on the feedback resistance in the replica circuit and then providing the degeneration resistance control signal to a degeneration resistance control device in the amplifier to thereby control the degeneration resistance in the amplifier.
  • the ratio comprises 1 to 1'.
  • the degeneration resistance control device comprises a FET switch. It is contemplated that the method may further comprise a current mirror configured to create the degeneration resistance control signal.
  • the feedback resistance comprises resistance from a FET switch resistance and a feedback resistor. The amplifier may have the bandwidth to support data rates of 10 gigabit per second or greater.
  • the TIA comprises a variable gain amplifier configured to receive and amplify a signal, wherein the gain is set by a gain control signal which modifies a feedback resistance.
  • a replica circuit is also provided and configured to create a replica circuit feedback resistance which is a ratio of the feedback resistance of the variable gain amplifier.
  • An amplifier amplifies a resistance control signal such that the resistance control signal is based on the replica circuit feedback resistance.
  • a resistance control device configured to change a degeneration resistance in the variable gain amplifier. The degeneration resistance is changed in relation to the feedback resistance in the variable gain amplifier based on the resistance control signal.
  • the replica circuit replicates one or more aspects of the variable gain amplifier.
  • the resistance control device comprises a FET switch.
  • changing the degeneration resistance in relation to the feedback resistance in the variable gain amplifier comprises maintaining the product of the degeneration resistance and the feedback resistance in the variable gain amplifier as generally constant.
  • a transimpedance amplifier comprising an input configured to receive an input signal and an amplifier configured to amplify the input signal to create an amplified signal.
  • the amplifier also has an output configured to output the amplified signal.
  • a feedback loop having a feedback resistance is part of the system and it has a feedback resistance comprising a switch resistance, a feedback resistor in parallel with the switch resistance, and a divider element.
  • the divider element is in parallel with the feedback resistance and is in series with the switch resistance to create a combined switch resistance. The divider element reduces the effect of changes in the switch resistance on the combined resistance.
  • the divider element comprises a resistance.
  • the switch resistance may comprise the resistance of a FET switch and the switch resistance may change with an input voltage to the FET switch. It is contemplated that the TIA amplifier may further comprise a detection circuit configured to provide a gain control signal to the FET switch.
  • a first stage amplifier has one or more first stage inputs and one or more first stage outputs and a second stage amplifier has one or more second stage inputs and one or more second stage outputs.
  • the one or more second stage inputs connect to the one or more first stage outputs.
  • one or more impedance matching devices at the output of one or more of the first stage amplifier and second stage amplifier.
  • the one or more impedance matching devices have impedance controlled by one or more control signals.
  • a detection system is also provided and configured to monitor an input to the first stage amplifier input or an amplified signal from the first stage amplifier or the second stage amplifier and generate, based on the monitoring, one or more control signals to control the resistance of the one or more impedance matching devices.
  • the amplifier further comprises a feedback resistor between a second stage input and a second stage output.
  • the impedance matching devices may comprise FET switches. It is contemplated that the one or more impedance matching devices may comprise a first impedance matching device between the first stage amplifier and a second stage amplifier and a second impedance matching device at the one or more second stage outputs. The one or more impedance matching devices adjust the impedance between the first stage amplifier and the second stage amplifier.
  • a two stage amplifier comprising a first stage amplifier and a second stage amplifier.
  • the output of the first stage amplifier "connects to the input of the second stage amplifier.
  • a variable impedance matching device is located between the first stage amplifier and the second stage amplifier such that the variable impedance matching device has an impedance controlled by a control signal received by the variable impedance matching device.
  • a detection circuit is also provided and is configured to detect a peak power level or average power level from a signal output from the two stage amplifier and based on the detection, generate the control signal.
  • the variable impedance matching device may comprise a FET switch, hi one embodiment, the second stage amplifier has differential inputs and the FET switch is connected between the differential inputs and the control signal changes the resistance of the FET switch.
  • the amplifier may further comprise a second variable impedance matching device at the output of the second stage amplifier and the detection circuit further outputs a second control signal to the second variable impedance matching device. In one configuration the amplifier further comprises one or more feedback resistors connected between an input and an output of the second stage amplifier.
  • Also disclosed is a method for variably amplifying a signal comprising receiving a signal and amplifying the signal in a first stage amplifier to create a first amplified signal. Then presenting the first amplified signal to a second stage amplifier and controlling the impedance between the first stage amplifier and the second stage amplifier based on a control signal. The control signal controls the gain of the amplifier. Then amplifying the first amplified signal with a second stage amplifier and outputting the second stage amplifier on an output of the second stage amplifier.
  • controlling impedance comprising adjusting a resistance between differential signal paths between the first amplifier stage and the second amplifier stage.
  • the control signal may comprise an automatic gain control signal.
  • This method may further comprise controlling the impedance of an output of the second stage amplifier based on a second control signal.
  • the method may further comprise monitoring the output of the second stage and creating the control signal and second control signal based on the monitoring.
  • controlling the impedance comprises providing the control signal to a FET switch.
  • Figure 1 is a block diagram of a prior art optical receiver front end having an amplifier and an equalizer.
  • Figure 2 illustrates a circuit level block diagram with the divider network to address the drawbacks in the prior art.
  • Figure 3 illustrates a generalized block diagram of a circuit of Figure 2.
  • Figure 4 illustrates a block diagram of an example embodiment of a system having a replica circuit.
  • Figure 5 illustrates a circuit diagram of an example implementation of a transimpedance amplifier with a replica circuit.
  • Figure 6 illustrates an example embodiment of a prior art amplifier utilizing a prior art solution for increasing dynamic range.
  • Figure 7 illustrates an amplifier having multiple automatic gain control elements with modified resistive network.
  • Figure 8 illustrates an example circuit level diagram of the generalized block diagram of Figure 7.
  • FIG. 2 illustrates a circuit level block diagram of one innovation to address the drawback in the prior art.
  • This circuit illustrates an exemplary TIA device 200.
  • amplifier element 204 may be broadly described as the amplifier while gain control loop 208 serves as a voltage based automatic gain control.
  • gain control loop 208 serves as a voltage based automatic gain control.
  • a collector resistor capacitance RcCc and a degeneration resistance capacitance RdCd are described below in more detail.
  • an input 212 connects to a transistor 216, which is part of the amplifier element 204.
  • the transistor 216 has a transconductance value defined by g m and is configured to generate an amplified output at outputs V out and V e .
  • a voltage controlled feedback loop 208 provides the amplifier feedback.
  • a FET switch 220 and a feedback resistor 224 Controlling the FET switch 220 is a control voltage V agc , which determines the amount of resistance in the feedback loop 208.
  • a drawback to this configuration is that the FET switch 220 causes unwanted distortion, which if uncorrected can hinder circuit performance. This distortion occurs as a result of the FET resistance (R sw ) changing in response to voltage changes across the switch. These changes in resistance R sw also change the resistance in the feedback loop, which affects the linearity of signal amplification.
  • the divider element 230 can be any device that establishes a series resistance in the feedback loop.
  • the divider element 230 may be a passive element, active element or a combination of both.
  • the divider element 230 comprises one or more fixed resistances. Through voltage division, a portion of the voltage across the feedback loop is expressed across the divider element 230 while a portion is expressed across the FET switch 220. As compared to prior art embodiments which lacked the benefit of element 230, the innovation reduces the voltage swing across the switch 220. As a result, changes in switch resistance R sw have a smaller delta affect on the total resistance across the loop. This in turn reduces the voltage change resulting from changes in R sw . Testing including harmonic analysis reveals this divider element 230 improves performance.
  • Figure 3 illustrates a generalized block diagram of the circuit of Figure 2.
  • a feedback resistance 304 is in parallel with an amplifier 300.
  • a variable FET resistor switch 308 receives a control input that determines the resistance presented by the switch, which in turn controls the resistance of the feedback loop.
  • a series resistor 312 is also provided in series with the variable switch. The series resistor 312 could be fixed or variable. Operation occurs as described above in connection with Figure 2. The addition of the series resistance 312 reduces the dominance of the variable switch resistance. This in turn reduces the change in feedback resistance resulting from changes in the resistance of variable switch.
  • the V agc value may be increased to lower the feedback resistance value by providing a shunt around the feedback resistor R f 224.
  • the input to the FET switch 220 is related to the value of the input current. This operation occurs dynamically such that for low input currents, the input to the Vagc magnitude is likewise small. In response to larger input currents it is desired to have smaller feedback resistance. In this manner, the swing across the feedback path is adjusted in an effort to maintain linearity and avoid clipping and distortion.
  • the FET switch 220 has a resistance R sw defined as follows:
  • the resistance R sw depends inversely on the input voltage to the FET switch 220.
  • the swing across the drain-source terminals Vj 5 affects the switch resistance, which in turn adversely affects the linearity.
  • the transimpedance of the amplifier is defined by the following equation, where A is the gain of the amplifier and R' f is the combined feedback of the FET switch 220 R sw and the feedback resistor R f .
  • the bandwidth of the TIA is defined as follows, where C Pd is the capacitance of the degeneration element.
  • transitioning from a low current input to a high current input changes the AC characteristic of amplifier behavior. For example, peaking can cause distortion. Some of these unwanted characteristics flow directly from the AC response of the switch. This is often referred to as the dynamic behavior of the TIA in response to different input currents.
  • Differing input current levels change the poles and zeros of the amplifiers so caution must be exercised to avoid instability problems. For example, if a TIA is configured to have certain AC response for low current, then in response to increased current, the transimpedance changes. When this occurs, the pole locations move closer in vicinity and this can cause instability due to phase modulations. Any RC combination in the circuit creates a pole or a zero.
  • pole locations depend on RV and R 0 . And, as set forth above, as the input current changes, so does R' f , which causes the pole 1 location to move higher on the pole/zero Bode plot. This can then create instability. Note that pole 2 is dependant on the collector resistance and capacitance and as such, changes in input current will generally not change the pole 2 location.
  • Adjusting the gain A may occur in relation to the input current. It is contemplated that the gain may be increased or decreased in relation to the input current to maintain stability. In one embodiment, a decrease in the gain of the amplifier will maintain the separation between the poles. In one embodiment these changes are in the Y domain or gain domain.
  • the gain of internal amp A is defined as:
  • R 0 is the collector resistance and gm is the transconductance of the transistor which is determined by the transistor dimensions, design, and current.
  • the transistor is a bipolar device, but it is contemplated that in other embodiments the transistor can comprise any process.
  • R d is the degeneration resistance, which may be assumed to be the emitter resistance of the internal amplifier. Because all these values with the exception of R ⁇ are constants, by changing Rj, the gain can be changed. Thus, increasing R d will decrease the gain A.
  • RV* Rd should be maintained constant. This is true because R 0 does not change for a given setting even with input current changes. The only values that change are RV and Rd. RV changes with R sw , which changes with input current. Therefore, by adjusting Rj it is possible to control the gain, which maintains system stability.
  • Figure 4 illustrates on example embodiment of such an exemplary system.
  • Figure 4 is similar to Figure 1 , and only the aspects of Figure 4 which differ from Figure 1 are discussed herein.
  • Figure 4 includes a replica circuit 404.
  • the replica circuit is configured to maintain a value R d in relation to the value RV, thereby maintaining the product of the two at or near a constant value, hi turn and as discussed above, stability is maintained.
  • the replica circuit comprises any configuration of hardware or software and may include active devices, passive devices, or both.
  • the term replica circuit indicates that one or more aspects of the TIA circuit 108 are duplicated to create a circuit that behaves and reacts to inputs and environmental conditions in a manner similar to the TIA itself.
  • Figure 5 illustrates a circuit diagram of an example implementation of a replica circuit. This is but one possible example embodiment of a replica circuit and as such it is contemplated that one of ordinary skill in the art may generate variations on this circuit that do not depart from the claims that follow.
  • the original TIA 504 is shown with R' f and R d shown for purposes of reference. Replicating this circuit is a replica circuit 508.
  • Replica circuit 508 is generally similar to the TIA circuit 504.
  • the replica circuit may be larger, smaller, or the same size as the TIA circuit 504.
  • the replica circuit 508 is a scaled down version of the TIA 504.
  • a constant voltage source 516 is applied to the replica circuit R f and the resulting current is provided to an amplifier circuit 520, which extracts the current.
  • the resulting current is mirrored by current mirror 512 to create a reference voltage.
  • the current mirror may be a 1 :1 ratio or other ratio.
  • This reference voltage is provided as an input to an amplifier 530.
  • This reference voltage is related to R f of the replica circuit.
  • the other input to the amplifier 530 is a negative feedback from a switch 534.
  • the switch 534 comprises a FET switch.
  • the TIA 504 reacts to changes in input current is as commonly understood which in turn change the value of R' f 540.
  • a replica circuit 508 is provided. Due to the duplicate nature of the replica circuit 508, the value of R' f in the replica circuit is likewise changing in relation to R' f 540.
  • V ref can be expressed as follows:
  • I re f is related to V ref and V 1 ef is related to or based on the changing value R f .
  • V ref is related to V d and R f and it is possible to create a V ref that is inversely proportional to R' f .
  • I d through R d is roughly a constant.
  • the amplifier 530 can be created to establish Vj and V re f the same. As such, then
  • Also disclosed herein is a method and apparatus for increasing the bandwidth of an amplifier system, without degrading gain and dynamic range. As is understood, it is preferred for an amplifier to have a high gain, wide or high bandwidth, large dynamic range and minimal peaking at lower gain. Prior art solutions were able to improve one of these performance aspects, at the expense of other aspects.
  • FIG. 6 illustrates on example embodiment of a prior art amplifier utilizing a prior art solution for increasing bandwidth.
  • inputs 604 V mp and V 111111 connect to a first stage amplifier 608, the output of which connects to a second stage amplifier 612.
  • Feedback resistors 616A, 616B connect as shown to provide feedback to the second stage amplifier 612.
  • the outputs from the second stage amplifier 612 connect to resistors R 620A, 620B, and the opposing ends of the resistors 620A, 620B connect to the drain and source of an FET switch 624.
  • the gate of the FET switch 624 is controlled by an automatic gain control voltage, defined as V agc .
  • the resulting voltage is provided on outputs 640 as V outp and V outm .
  • an input voltage on input 604 is amplified by the first stage amplifier 608 and the second stage amplifier 612.
  • the control voltage Vagc controls the gain between the input 604 and the outputs 640.
  • the resistors 620 and FET switch 624 appear as an RC element which lowers the bandwidth due to the capacitance of the switch 624 which appears as a low pass filter.
  • control voltages V agc i, V agc2 are presented to the gate terminals to create two independent terminals to control the dynamic range.
  • V agC such as for example near V dd
  • the FET switch 704 in this embodiment a P channel FET, results in no effect on the incoming signal and the level of amplification.
  • V agc i the FET appears as an open circuit.
  • V agC As V agC
  • the focus is on large signals. Typically it is desired to have a lower gain when presented with a large input signal to avoid saturation.
  • V agc i and V agc2 By lowering the values of V agc i and V agc2 , the output impedances of the first and second stages are reduced. By having two V agc controls, the effect is multiplicative and it is possible to obtain a larger dynamic range.
  • and V agc2 are generated by a detection circuit 712.
  • the detection circuit may comprise any combination of hardware, software, or both configured to monitor and process the incoming signal, the outgoing signal, or both to generate the control signals V agC
  • the values for V outp and V outm are feedback to the detection circuit 712.
  • averaging or peak detection occurs and the result is subtracted or compared to a threshold. If the result is higher than the threshold, then one or more V agc values are adjusted to maintain the output within a desired range.
  • Figure 8 illustrates one example circuit level diagram of the generalized block diagram of Figure 7.
  • the FET 804 comprises the first
  • the FET switch and the FET 808 comprises the second FET switch.
  • the first amplifier stage is shown as a differential amplifier by current mirror 812 while the second gain stage is shown as a differential amplifier by the second current mirror 816.
  • the resistors 820 represent resistors 616 in Figure 7. This is but one example embodiment of a circuit level implementation and as such, it is contemplated that other circuit arrangements are possible based on this disclosure. For example, it is contemplated that these principles maybe implemented in TIA, equalizers, limiting amplifiers, crosspoint switches, or any other application benefiting from one or more of increased bandwidth, gain, stability, and dynamic range and limited peaking, and variable gain amplifiers (VGAs). [0079] The following table sets forth simulation results for the innovation set forth herein.
  • the bandwidth of the prior art approach is only 2.1 GHz, which does not approach the higher bandwidths, such as 10 GHz.
  • the prior art does not meet specification.
  • the current approach shown in the final column and as disclosed herein achieves the desired bandwidth around 12.78 GHz.
  • the other factors are not degraded as would normally occur in prior art approaches. For example, trie gain is maintained and the dynamic range actually increases to 19.12 db. Finally, peaking is also improved.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

L'invention concerne diverses configurations d'amplificateurs ayant une bande passante, une linéarité, une plage dynamique accrues et moins de distorsion. Pour augmenter la bande passante dans un amplificateur de transimpédance, un circuit de réplique est créé pour répliquer une résistance de contre-réaction, ou la résistance ou la valeur qui se rapporte à une résistance de réaction. A partir du circuit de réplique, les valeurs répliquées sont mises en miroir et traitées de façon à commander un commutateur FET qui modifie une résistance de contre-réaction. Le signal de commande du commutateur FET se rapporte à la résistance de réaction et modifie la résistance de contre-réaction pour, de ce fait, maintenir constant le produit de la résistance de réaction et de la résistance de contre-réaction. Dans un autre mode de réalisation, un second commutateur commandé par un signal de commande à gain automatique est établi entre un amplificateur de premier étage et un amplificateur de second étage en vue d'améliorer la plage dynamique et la bande passante sans dégrader d'autres caractéristiques d'amplificateur.
PCT/US2010/001363 2009-05-06 2010-05-06 Amplificateur à gain variable WO2010129065A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/387,826 US7973602B2 (en) 2009-05-06 2009-05-06 Variable gain amplifier
US12/387,826 2009-05-06
US12/387,824 2009-05-06
US12/387,824 US7948323B2 (en) 2009-05-06 2009-05-06 Linear transimpedance amplifier with wide dynamic range for high rate applications

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Publication Number Publication Date
WO2010129065A2 true WO2010129065A2 (fr) 2010-11-11
WO2010129065A3 WO2010129065A3 (fr) 2011-03-03

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111628729A (zh) * 2020-06-22 2020-09-04 西安电子科技大学芜湖研究院 一种大线性动态范围高带宽可重构跨阻放大器

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US20080055005A1 (en) * 2006-05-25 2008-03-06 Il-Ku Nam Feedback-type variable gain amplifier and method of controlling the same

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US20050024142A1 (en) * 2003-07-31 2005-02-03 Tirdad Sowlati Variable gain amplifier system
US20060125557A1 (en) * 2004-12-13 2006-06-15 Broadcom Corporation Impedance matched variable gain low noise amplifier using shunt feed-back
US20060261893A1 (en) * 2005-05-17 2006-11-23 Ming-Chou Chiang Current-matching variable gain amplifier
US20080055005A1 (en) * 2006-05-25 2008-03-06 Il-Ku Nam Feedback-type variable gain amplifier and method of controlling the same

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Publication number Priority date Publication date Assignee Title
CN111628729A (zh) * 2020-06-22 2020-09-04 西安电子科技大学芜湖研究院 一种大线性动态范围高带宽可重构跨阻放大器
CN111628729B (zh) * 2020-06-22 2023-04-28 西安电子科技大学芜湖研究院 一种大线性动态范围高带宽可重构跨阻放大器

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