WO2010119124A1

WO2010119124A1 - Organic non-volatile memory device

Info

Publication number: WO2010119124A1
Application number: PCT/EP2010/055047
Authority: WO
Inventors: Maarten Debucquoy; Maarten Rockele; Jan Genoe; Gerwin Gelinck; Paul Heremans
Original assignee: Imec; Katholieke Universiteit Leuven, K.U. Leuven R&D
Priority date: 2009-04-16
Filing date: 2010-04-16
Publication date: 2010-10-21

Abstract

The invention relates to an organic memory element comprising an organic semiconductor material, a gate dielectric stack comprising a first dielectric layer acting as a barrier layer and a second dielectric layer of an organic material, and a gate electrode. The gate electrode is separated from the second dielectric layer through the barrier layer. For programming charge carriers are injected into the second dielectric layer by application of a programming pulse of a first voltage to the gate electrode to cause a shift of the threshold voltage. For erasing, an erasing pulse of a second voltage with opposite polarity to the first voltage is applied to the gate electrode to cause an opposite shift of the transistor threshold voltage to the OFF state threshold voltage. The organic semiconductor material is an ambipolar organic semiconductor material.

Description

Organic non-volatile memory device

Technical field of the invention

This invention relates to organic devices, more in particular to organic non-volatile memory devices and to methods for programming such organic memory devices.

Background of the invention

There has been made substantial progress on organic semiconductor devices in the past decade. This progress has led to flexible displays comprising transistors with an organic semiconductor material, organic light emitting diodes (OLEDs), solar cells based on organic semiconductors and integrated circuits comprising both transistors and memory elements, and industrialization is ongoing. WO99/30432 demonstrates the state of organic semiconductors at the end of the 1990s. This patent application relates to an identification transponder of which the integrated circuit predominantly comprises organic materials. The transistors of the integrated circuits comprise both an organic electrical conductor, such as polyaniline, and an organic semiconductor material, such as polythienylene-vinylene. A memory element is included in the integrated circuit. The memory element is based on a vertical interconnect area (via) between a first and a second conductive layer. Programming occurs mechanically or optically (with a laser), i.e. by partial removal or destruction of material in an individual via. A 15-bit pattern is accommodated by 15 vias. Some of the progress made since then relates to improvement of materials. The organic material PEDOT/PSS is used as electrically conductive material, while many devices use metals instead. The material pentacene is currently a widely applied semiconductor material, which demonstrates an intrinsic (undoped) mobility, has a good on/off ratio and can be processed in a manner suitable for industrial use. Additionally, ambipolar semiconductor materials attract attention for their ability to conduct both electrons and holes, whereas, traditionally, most organic semiconductors materials only allow electron or typically hole transport, i.e. are unipolar. It has been shown that pentacene, when processed properly, also has ambipolar properties. The ambipolar semiconductor materials allow manufacture of inverters and other more advanced CMOS like logic. For organic semiconductor applications to become fully mature, there is a need for non-volatile organic memory devices that can easily be integrated into existing circuit technology. A first non-volatile memory element taken into consideration was a ferroelectric memory element. Such an element is known from EP1700309. It comprises on top of a planarized substrate a gate electrode that is covered by an organic ferroelectric layer. The device is completed with source and drain electrodes and an ambipolar organic semiconductor material or a blend of material with ambipolar properties. This results in larger memory windows, larger current ratios between the "0" and the "1 " state, facilitating read-out operation. However, ferroelectric materials have major disadvantages. The ferroelectric material is a polarizable material of which the polarization direction may be defined by applying an electric field. When using the organic ferroelectric material in combination with a unipolar organic semiconductor material, ionic species or polar small molecules (space charge) may be transported through the gate dielectric. This transportation may occur either under influence of the electric fields employed during device operation or after writing a certain polarization state. This causes fatigue or other degradation phenomena. The ambipolar properties provide a shield against such transport of ionic species, for instance hydroxyl-ions, that are already in the device or are attracted from the ambient. However, an extremely high degree of ambipolarity is needed to obtain a good shield, f.i. a charge carrier density in the order of 10¹² cm^"2 is needed. This appears to be beyond realistic expectations for organic semiconductor materials.

An alternative organic memory element is based on an electret dielectric material rather than a ferroelectric material. Such electret materials are preferably non-polar and hydrophobic polymers, such as polystyrene, PaMS, PVN, P4MS. The operation of such a memory element is based on charge carrier trapping in the gate dielectric. This last mechanism, wherein a floating gate is charged and discharged, has shown promising results in terms of switching speed and retention, as e.g. reported by K.-J. Baeg et al in Organic non-volatile memory based on pentacene field-effect transistor using a polymeric gate electret", Advanced Materials 2006, 18, 3179-3183 and in "Polarity effects of polymer gate electrets on non-volatile organic field-effect transistor memory", Advanced Functional Materials, 2008, 18, 1 -8. The memory devices reported by Baeg et al are based on an OFET (Organic Field Effect Transistor) structure, comprising an additional polymeric gate dielectric layer with charge trapping ability (electret layer). The device structure comprises a gate electrode defined in a silicon substrate, a gate dielectric of silicon oxide (SiO₂), the additional dielectric layer of the electret material, a semiconductor material such as pentacene and source and drain electrodes. This OFET memory device displays reversible shifts of the threshold voltage V_th when an appropriate gate voltage is applied above a certain threshold voltage. The nonvolatile memory characteristics are related to the effect of trapped charges in the polymeric gate dielectric layer, via charge transfer between the organic semiconductor layer and the dielectric layer. Such a charge trapping memory device has different stable memory states between which can be switched by trapping and detrapping of charge carriers. The different memory states can be recognized by the different levels of current going through the device upon the application of an appropriate read-out voltage.

To program the device into a certain memory state, a programming voltage can be applied to trap mobile carriers in energy traps, or just the other way around, to free some immobilized charge carriers from their traps. This is shown in Fig. 2 of the 2006 article. The element is programmed by application of a programming voltage of 200 V on the gate for a device with a silicon oxide dielectric thickness of 300 nm. Erasure occurs by subsequent application of a voltage of opposite polarity, e.g. of - 100V. By reduction of the gate oxide thickness to 100 nm, the programming voltage is reduced to 60V, and the erasing voltage becomes - 50V. The directions of programming and erasing may also be reversed i.e. programming with -200V and erasing with 200V. The programming voltage may be further reduced to approximately 35V by means of illumination with visible light during the programming process, but in that case the retention time was also dramatically decreased.

It is a disadvantage of the known device that the programming voltages are still too high for effective incorporation into integrated circuits. The reduction to 35V appears to go in the good direction, but the decreased retention time implies that in this case the element does not act as a viable memory element anymore.

Summary of the invention

It is an aim of the present invention to provide organic non-volatile trapped charge memory devices and methods for programming such devices, leading to a large memory window, good data retention, a large U/lott ratio and low programming voltages for switching between memory states. This aim is achieved by a method according to the present invention.

The present invention provides a method for programming (i.e. writing and erasing) non-volatile organic memory devices having a transistor structure with a gate dielectric stack comprising at least two dielectric layers, wherein writing (i.e. switching to the ON state of the memory device) comprises causing a shift of the transistor threshold voltage to the ON state threshold voltage V_th,o_N by applying a first gate voltage, thereby e.g. trapping a first type of charge carriers in the gate dielectric stack, and wherein erasing (i.e. switching to the OFF state of the memory device) comprises causing an opposite shift of the transistor threshold voltage to the OFF state threshold voltage V_thiOFF by applying a second gate voltage, thereby for example trapping a second (opposite) type of charge carriers in the gate dielectric stack and/or detrapping the first type of charge carriers from the gate dielectric stack. In embodiments of the present invention V_th,oN and V_th,oFF are substantially different from the initial transistor threshold voltage V_th,ι, the initial threshold voltage being the threshold voltage of the device before any programming is performed. The initial transistor threshold voltage has a value in between V_th,_ON and V_th,_OFF, i.e. V_th,_OFF < V_thil < Vth.oN or Vth.oFF > Vth.i > Vth.oN- Particularly, the first gate voltage is negative, so as to trap holes into the gate dielectric stack.

A method according to the present invention can be used for programming organic non-volatile memory devices wherein the organic semiconductor layer has ambipolar properties. Use of a method of the present invention for programming a non-volatile memory device has advantages as compared to prior art methods, wherein V_thiOFF or V_thiON correspond to the initial transistor threshold voltage V_thil (i.e. wherein e.g. writing comprises shifting the threshold voltage to V_th,oN and wherein erasing comprises shifting the threshold voltage to V_th,ι, thereby reversing the threshold voltage shift caused by writing). It is an advantage of a method according to the present invention that the memory window (i.e. the difference between V_th,oN and V^_OFF) can be larger than in prior art methods, thus leading to an improved data retention. It is an advantage of a method according to the present invention that the difference between memory states (i.e. the current ratio between the ON state and the OFF state) can be larger than in prior art methods, thus leading to a good reliability of reading the memory state. In an ambipolar memory device that is programmed according to a method of the present invention, the difference between the memory states can be larger because the net trapped charge can be negative and positive, while in a unipolar device, wherein programming is based on trapping and detrapping of one type of charge carriers, it can only be zero and negative or zero and positive. It is an advantage of the present invention that, as compared to unipolar devices, the programming voltages can be lower. While it may not be possible to detrap one type of charge carriers at a given gate voltage (e.g. for erasing a unipolar memory), it may be possible to trap the opposite type of charge carriers at that given gate voltage (ambipolar memory). In this case an ambipolar memory device can have lower programming voltages than a unipolar device. Lower programming voltages are further enabled in an embodiment of the present invention by thinning the gate dielectic stack to a thickness below 100 nm, while maintaining a charge barrier between the gate and the charge traps. The gate dielectric stack comprises a first dielectric layer at the side of the gate electrode, the first dielectric layer acting as a charge barrier, and a second dielectric layer at the side of the organic semiconductor layer, for example an organic dielectric layer, wherein charges can be trapped. The second dielectric layer comprises in particular an electret material This charge barrier is necessary to prevent that charge carriers, and particularly holes, to be injected into the dielectric stack from the semiconductor material, flow through the gate dielectric stack so as to arrive at the gate. Such a charge barrier has preferably a leakage current lower than 1 e ^"^ mA/cm² at an electric field of 5 (MV/cm). The leakage current is measured in structures with only a barrier layer, without second dielectric layer and semiconductor layer. The voltage over this barrier layer is increased at fixed voltage steps and the - leakage - current through the barrier at each voltage is measured. This voltage is thereafter recalculated to a field over the barrier layer.

The charge barrier may be deposited by sputtering, chemical vapour deposition (CVD), atomic layer deposition (ALD) or may be formed by thermal oxidation or anodization. Preferably, use is made of ALD or anodization of the gate electrode, that in that embodiment suitably comprises aluminium. Preferably, the charge barrier has a thickness in the range of 10 nm to 100 nm, more preferably in the range between 20 nm and 50 nm. The charge barrier suitably comprises an inorganic material, such as silicon oxide, silicon nitride, a stack of silicon oxide and silicon nitride, or silicon oxide, silicon nitride and silicon oxide, tantalum oxide.

More preferably, the second dielectric layer is deposited with a thickness of less than 20 nm, more preferably in the range of 2-15 nm, more preferably 5- 12 nm. The use of a thin film of second dielectric material turns out sufficient for trapping. However, it has turned out that the retention time of particularly electrons is improved by using an second dielectric layer with more than a minimum thickness. The second dielectric layer can have a leakage current that is larger than the leakage current of the first dielectric layer, e.g. at least a factor of 3 larger. Preferably, the first dielectric layer (charge barrier) has a stack dielectric constant ε in the range of 1 e-2 to 0.1 per nm. This preferred implementation is for instance obtained with an electric field of at least 5 MV/cm and a programming voltage between gate and source V_GS of 20 V. More preferably, the stack dielectric constant ε is in the range of 1.5-5.0 e-2 per nm, for instance 2.5e-2 per nm. The stack dielectric contant is defined as the ratio of the dielectric constant of a single layer over a stack permittivity product, that is defined as the t(second dielectric layer)^*ε(first dielectric layer)+t(first dielectric layer)^*ε(second dielectric layer). Herein, t is the layer thickness and ε is the relative dielectric constant of the material.

Brief description of the drawings Figure 1 shows a cross section of an organic charge trapping memory device;

Figure 2 illustrates accumulation of electrons in an organic semiconductor layer and subsequent trapping of electrons in the gate dielectric, upon application of a suitable programming voltage;

Figure 3 illustrates accumulation of holes in the organic semiconductor layer and subsequent trapping of holes in the gate dielectric, upon application of a suitable programming voltage;

Figure 4 shows I_D-V_GS characteristics of a prior art unipolar device wherein only holes can be trapped. In the example shown the turn-on voltage of the transistor can switch from 0 V to -7 V; Figure 5 shows l_D-V_Gs characteristics of an ambipolar device according to the present invention wherein both holes and electrons can be trapped. In the example shown the turn-on voltage of the transistor can switch from +7 V to -7

V;

Figure 6 shows I_D-V_GS characteristics for different states of a memory device programmed according to a method of the present invention;

Figure 7 shows the evolution of the onset voltage of a charge trapping memory device as a function of time;

Figure 8 illustrates the trade-off between fast writing and erasing and good retention; Figure 9 illustrates a measurement procedure performed on a structure as shown in Figure 1 ; Figure 10 shows measurement results illustrating trapping of both electrons and holes as a function of the programming voltage;

Figure 1 1 shows measurement results illustrating trapping of both electrons and holes as a function of the programming time; Figure 12 shows the V_0n+ and V_0n- voltages as a function of temperature;

Figure 13 illustrates the electron mobility and V_0n+ as a function of temperature;

Figure 14 shows l_D-V_Gs characteristics for an organic transistor with unipolar hole transport;

Figure 15 shows I_D-V_GS characteristics for an organic transistor with unipolar electron transport;

Figure 16 shows the V_0n+ and V_0n- voltages as a function of time after programming

Figure 17 shows the current ratio I_D+/I_D- as a function of programming cycles for memory elements with second dielectric layers of different thickness.

Detailed description of the invention

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention and how it may be practiced in particular embodiments. However it will be understood that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures and techniques have not been described in detail, so as not to obscure the present invention. While certain aspects of the present invention will be described with respect to particular embodiments and with reference to certain drawings, the invention is not to be limited thereto. The drawings included and described herein are schematic and are not meant to limit the scope of the invention. It is also noted that in the drawings, the size of some elements may be exaggerated and, therefore, not drawn to scale for illustrative purposes.

Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein. It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the steps or elements listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B. The present invention provides methods for programming organic nonvolatile charge trapping memory devices wherein charge carriers of both polarities, electrons and holes, can be trapped. The difference between the charge of the trapped electrons and the charge of the trapped holes is the net trapped charge, which determines the memory state. The methods of the present invention are further described for embodiments wherein the device is a memory field-effect transistor, wherein the charge carriers are trapped in (part of) the gate dielectric. However, methods of the present invention may also be used for programming memory devices based on other mechanisms (e.g. charge trapping in the semiconductor) or for memory devices having other device structures (e.g. two-terminal device structures).

The invention is further described for the exemplary embodiment wherein pentacene is used as an ambipolar organic semiconductor layer. However, other ambipolar organic semiconductor materials or combinations of materials may be used, such as for example a layer comprising a mixture of an n-type and a p-type organic semiconductor. The invention is further described for the case wherein the gate dielectric is a dielectric stack comprising a silicon oxide layer and a PaMS (poly(a-methylstyrene) layer. However, other dielectric layers or other combinations of dielectric layers can be used. Preferably the gate dielectric layer or gate dielectric stack allows good trapping of charge carriers and good storage of charge carriers in the traps.

The structure used for simulations and experiments is a top contact pentacene memory transistor as illustrated in Figure 1. On a heavily doped n⁺⁺ silicon substrate, acting as a gate electrode, a gate dielectric is present, the gate dielectric comprising a silicon dioxide layer and a PaMS layer. On top of this gate dielectric an organic semiconductor layer is present (in the example shown a pentacene layer), with Au source and drain contacts. The transfer curve (i.e. I₀ versus V_Gs curve wherein I₀ is the source-drain current and wherein V_Gs is the gate-source voltage) of the transistor structure shown in Figure 1 can be shifted by applying a first gate voltage to the gate. For example, by applying an appropriate gate voltage, electrons can be accumulated in the organic semiconductor layer and transferred to the dielectric stack, where they can be trapped. Because the organic semiconductor layer has ambipolar properties, by applying a second appropriate gate voltage, holes can be accumulated in the organic semiconductor layer and transferred to the dielectric stack, where they can be trapped. Figure 2 schematically illustrates accumulation of electrons in the organic semiconductor layer and subsequent transfer and trapping of the electrons in the gate dielectric, upon application of a suitable programming voltage. Figure 3 schematically illustrates accumulation of holes in the organic semiconductor layer and subsequent transfer and trapping of holes in the gate dielectric, upon application of a suitable programming voltage. The present invention provides a method for programming (i.e. writing and erasing) non-volatile organic memory devices having a transistor structure, wherein writing comprises causing a shift of the transistor threshold voltage to the ON state threshold voltage V_th,oN by applying a first gate voltage, thereby e.g. trapping a first type of charge carriers in the gate dielectric, and wherein erasing comprises causing an opposite shift of the transistor threshold voltage to the OFF state threshold voltage V_th,o_FF by applying a second gate voltage, thereby for example by trapping a second (opposite) type of charge carriers in the gate dielectric. In embodiments of the present invention V_th,oN and V_th,oFF are substantially different from the initial transistor threshold voltage V_thil. The initial transistor threshold voltage has a value in between V_thiON and V_thiOFF, i.e.

Vth.OFF < Vth.l < Vth.ON Or Vth.OFF > Vth.i > Vth.ON- In embodiments of the present invention, writing of the memory can for example comprise injecting electrons from the organic semiconductor layer into the gate dielectric stack and trapping the electrons in the gate dielectric stack, by applying a positive gate voltage. Erasing of the memory can comprise injecting holes from the organic semiconductor layer into the gate dielectric stack and trapping the holes in the gate dielectric stack, by applying a negative gate voltage. For example, switching between the ON state and the OFF state of the memory device can comprise symmetrical switching of the transfer characteristics around the initial threshold voltage of the memory transistor.

In preferred embodiments of the present invention, writing of the memory comprises injecting holes from the organic semiconductor layer into the gate dielectric stack and trapping the holes in the gate dielectric stack, by applying a negative gate voltage. Erasing of the memory then comprises injecting electrons from the organic semiconductor layer into the gate dielectric stack and trapping the electrons in the gate dielectric stack, by applying a positive gate voltage. This preferred embodiment results in a better retention of the memory device, as illustrated below.

The difference between the charge of the trapped electrons and the charge of the trapped holes is the net trapped charge that determines the memory state. This mechanism can only be used if the organic semiconductor allows ambipolar transport. In addition, at least one of the source and drain contacts preferably allows injecting electrons into the organic semiconductor layer and at least one of the source and drain contacts preferably allows injecting holes into the organic semiconductor layer. Furthermore, the gate dielectric or gate dielectric stack preferably allows good trapping of both electrons and holes and good storage of both types of charge carriers in the traps. The gate dielectric stack does not only act as the place of charge storage of the memory device. As the PaMS polymer layer controls the interface with the organic semiconductor, it also controls the supply of charge carriers in the channel and in that way the tunnelling of these charge carriers and the behaviour of the organic memory transistor.

Figure 4 shows I_D-V_GS characteristics of a prior art unipolar memory device wherein only holes can be trapped. The initial transfer characteristics (i.e. the transfer characteristic before hole trapping) have a turn-on voltage at ~0V, and are measured by sweeping V_GS from -3 V to +14.5 V and then back from +14.5V to -3 V. The transfer characteristics after hole trapping (for subsequent sweeps of V_Gs) have a turn-on voltage of V_GS ~ -7V, and are achieved by sweeping V_Gs from -3V to -15 V, and then back. When applying a 'read' voltage V_GS = -5V, the transistor can be in two distinct states: the 'ON' state (corresponding to a device without trapped holes), or the 'OFF' state, corresponding to a device programmed with trapped holes. In the example shown, the turn-on voltage of the transistor can switch from 0 V (ON state) to -7 V (OFF state), resulting in a memory window of 7V.

Figure 5 shows I_D-V_GS characteristics of an ambipolar device that can be programmed according to the present invention, i.e. wherein both holes and electrons can be trapped. The central curve (full line, up-pointing trinagles) shows the initial transfer characteristic, i.e. before charge trapping, while the dashed lines with down-pointing triangles show the transfer characteristics after electron trapping (right curves, corresponding to the ON state) and hole trapping (left curves, corresponding to the OFF state). The initial transfer characteristic is measured by sweeping V_GS from -3 V to + 4 V. Electron trapping is achieved by sweeping V_GS further, from +4V to +14.5V. Electrons remain trapped as the gate voltage is swept back to -3V, resulting in the device to be ON at V_GS=0V. Hole trapping is achieved when the gate voltage is swept to V_GS of -15V. Holes remain trapped as the gate voltage is swept back to 0 V, resulting in the device to be OFF at V_Gs = OV. In the example shown the turn-on voltage of the transistor can switch from +7 V (ON state) to -7 V (OFF state), leading to a memory window of 14V.

Figure 6 shows the I_D-V_GS characteristic of an ambipolar device that is programmed according to a method of the present invention, thereby illustrating advantages of a method of the present invention. The dotted curve in Figure 6 shows the initial transfer characteristics of the OTFT, i.e. before programming. The dashed curve shows the transfer characteristics that are obtained after applying a gate voltage of +16V, resulting in trapping of electrons in the gate dielectric. This curve corresponds to the ON state of the memory device. The dash-dotted curve shows the transfer characteristics that are obtained after applying a gate voltage of -16V, leading to trapping of holes in the gate dielectric. Relative to the initial transfer characteristic, the dash-dotted curve is shifted in the opposite direction as compared to the dashed curve. According to prior art methods disclosed by Baeg et al as referred to above, the central curve corresponds to the OFF state of the memory device characterized by l_Offi, while the dashed curve corresponds to the ON state of the memory device characterized by I_0n-I- This is an example of electron trapping.

In embodiments of the present invention, the OFF state corresponds to the dash-dotted curve, characterized by l_Off2- In embodiments of the present invention, preferably the dashed curve is used as the ON state, with ON current l_On2- From the results shown in Figure 6 it can be concluded that in embodiments of the present invention there is a larger difference between the ON state and the OFF state than in prior art methods, i.e. WW is larger than lon-i/loff-i- Therefore, the difference between both memory states is larger and the reliability of reading the memory state can be better. Also, the difference between the threshold voltages or between the onset voltages (the onset voltage being the voltage at which charges start to accumulate in the channel) corresponding to the ON state and the OFF state is larger than in prior art methods, leading to a larger memory window and better data retention. In the example shown in Figure 6, trapping of holes leads to a larger shift of the transfer curve than trapping of electrons. Figure 7 shows the evolution of the onset voltage of a charge trapping memory device as a function of time. The circles illustrate the rate at which trapped electrons are released, while the squares illustrate the rate of release of trapped holes. It is clear that that the difference between the circles and the squares (corresponding to the ON state and the OFF state in embodiments of the present invention) is larger than the difference between the line indicated by circles and a horizontal line at V= OV (corresponding to the ON state and the OFF state in prior art methods). In the example shown, the holes stay much longer trapped than the electrons. This is partly related to the observation that initially the number of trapped holes is larger than the number of trapped electrons (because in this device holes are trapped more easily than electrons), but in addition the slope of the lines following the circles (for electrons) and squares (for holes) are also different. This indicates that the retention is better for holes than for electrons. Therefore, in preferred embodiments of the present invention, writing of the memory device is done by injecting holes in the dielectric stack and erasing is done by injecting electrons. The better retention observed for the holes allows using a thinner gate dielectric stack and thus enables the use of lower programming and erase voltages.

By proper design and material choice, in embodiments of the present invention a good trade-off can be obtained between writing, erasing and retention characteristics of the memory device. In prior art methods, wherein programming of the memory device is based on one type of charge carriers, e.g. electrons, there is a need for making a trade-off between fast programming (writing and erasing) and a long retention. Both cannot be optimized simultaneously. In case of an ambipolar device, wherein both types of charge carriers can be provided from the organic semiconductor and trapped, this trade-off can be avoided: deep traps with a good retention time can be used for writing and at the same time fast erasing is possible by overwriting e.g. trapped electrons with holes. This is illustrated in Figure 8. Figure 8.1. shows a situation wherein an electron is captured in an undeep trap. This leads to a bad retention but fast erasing (removal of electron). The second situation, illustrated in Figure 8.2., corresponds to capturing an electron in a deep trap, leading to a good retention but a slow erasing. The third situation illustrated in Figure 8.3. corresponds to a method according to the present invention, wherein writing occurs by capturing an electron in a deep trap (thus leading to a good retention) and wherein erasing occurs by capturing a hole (thus leading to fast erasing). By properly designing and controlling the location and the properties of the traps, memory devices with a good retention at the same time allowing fast programming can be obtained.

Measurements were performed on a structure as shown in Figure 1 , wherein the dielectric layer comprises a 21 nm thick silicon dioxide layer and a 4 nm thick PaMS layer, and wherein the organic semiconductor layer is a 40 nm thick pentacene layer. The measurement procedure is illustrated in Figure 9. After subsequently applying a negative, a positive and a negative programming voltage to the gate, the I₀ versus V_Gs curve was measured. From this result, the negative onset voltage of the memory device V_0n- was calculated, corresponding to a memory state (e.g. OFF state) resulting from hole trapping. Next a positive programming voltage was applied and the I₀ versus V_Gs curve was measured again. From this, the positive onset voltage of the memory device V_0n+ was calculated, corresponding to a memory state (e.g. ON state) resulting from electron trapping. This procedure was repeated several times. Figure 10, Figure 11 , Figure 16 and Figure 17 show results of measurements performed according to the procedure illustrated in Figure 9. The curves in Figure 10 show V_0n+ (circles), V_0n- (squares) and ΔV_on = V_0n+ - V_0n- as a function of the programming voltage V_Gs, for a programming time of 1.5 ms. It can be seen that both positive and negative programming voltages lead to a shift in V_0n, illustrating that both electrons and holes can be trapped. Figure 1 1 shows V_0n+, V_0n- and ΔV_on as a function of the programming time, for a programming voltage of 15V/-15V. Based on these results it can be concluded that both electrons and holes can tunnel from the semiconductor into the dielectric stack and be trapped. Fig. 16 shows the V_0n+ and the V_0n-, i.e. the shifts in threshold voltages in time after programming by trapping electrons (V_0n+) and holes (V_0n-) into the gate dielectric stack. This figure therewith shows the retention time. Programming pulses of 20V and -20V were applied for the electrons and holes trapping respectively. The figure shows different lines corresponding with second dielectric layers of 2 nm thickness, 5 nm thickness, 7 nm thickness and 10 nm thickness (only holes). The time scale is logarithmic, the voltage scale is relative to the V_0n+ , V_0n- as measured directly after manufacturing and calibration. Programming time was 1.5 ms. The initial V_0n+ was approximately 2V, the initial V_0n- was approximately -8V. It turns out that the average value is approximately -3V.

The Figure 16 demonstrates that the retention time for holes is better than for electrons. The threshold voltage V_0n- is after 10⁷ seconds (i.e. nearly 4 months) still 50% of the initial value. After 12 days (10⁶ seconds), it is still 70% of the initial value. It turns out to be largely independent of the thickness of the second dielectric layer. Contrarily, the thickness of the second dielectric layer has a major impact on the retention time of electrons. For a thickness of 2 nm, and 4nm (non-shown experiment), the retention time is not more than 10³ seconds, which is less than 1 hour. For a thickness of 5 and 7 nm, the threshold voltage has decreased to 20% of the initial value after 10⁶ seconds, i.e. 12 days. The 50% decrease is reached after approximately 1 day. Hence, the retention time for holes is much better than the retention time for electrons. Moreover, the retention time for electrons turns out much more dependent on the thickness of the second dielectric layer.

Fig. 17 shows the current ratio of I₀₊ and I₀- as a function of the number of programming cycles. This current ratio refers to the current in the memory element during read-out. The programmed state is here the state in which holes are programmed into the memory. The resulting current is the I₀₊. The erased state is the state in which electrons are programmed into the memory. The resulting current is the I_D- The I_D+ and I_D- are thus the effect of the shift of threshold voltages V_0n- and V_0n+. The I₀₊ has been measured at a gate-source voltage V_Gs of -2V, and a source-drain voltage of -0.02 V. I₀- is taken fixed at 100 pA to exclude variations in I₀₊ / I_D- due to the noise in the cut-off current of the memory element. The repeated tunneling of holes and electrons apparently damages the material. After 1 cycle, I₀₊ / I_D- is 574. After 98 cycles, I₀₊ / I_D- is still 330, and the device still works as a memory transistor with two distinct states. From 100 cycles on, I₀₊ / I_D- decreases more rapidly, and after 2345 cycles, I_D+ / I₀- is only 1.4. Although these numbers clearly limit the reprogrammability, more than 350 cycles can be achieved with an I₀₊ / I_D- higher than 100. Up to now only up to 10 write-and-erase cycles have been shown for organic charge trapping memories. A source-drain voltage V_SD of - 0.02 V was used for this experiment. However, the source-drain reading voltage may be increased to almost 2V before I₀₊ ends up in the saturation regime and becomes independent of the source-drain reading voltage. Such a higher source drain reading voltage also increases the current ratio.

Additional experiments were performed to illustrate that the method of the present invention can only be used for devices with ambipolar properties.

It is known that ambipolar carrier transport can occur in pentacene, and that it becomes less ambipolar for decreasing temperatures. Figure 12 shows the V_0n+ (circles) and V_0n- (squares) voltages as a function of temperature, illustrating that V_0n- (corresponding to hole trapping) is temperature independent and that V_0n+ (corresponding to electron trapping) changes with temperature, leading to a decreasing memory window (difference between V_0n+ and V_0n-) for lower temperatures. As illustrated in Figure 13, a similar activation energy can be observed for the electron mobility and for V_0n+, from which it may be concluded that V_0n+ is temperature dependent because the supply of electrons in the channel of the device is a limiting factor. From this it can be concluded that it is preferred to have a good supply of both types of charges carriers from the organic semiconductor layer, because the supply of charge carriers can limit the memory window.

The ambipolarity of the semiconductor does not mean that the mobility of electrons and holes has to be equal, or even of the same order of magnitude. Even when the mobility of one of the charge carriers is 6 orders of magnitude less than that of the other (e.g. hole mobility of the order of 0.1 to 1 cm²/Vs and electron mobility of the order of 1 E-7 to 1 E-6 cm²/Vs), sufficient charge carriers of both types can be accumulated to make the device operate according to the present invention. Also, the threshold voltages for accumulating electrons and holes need not be symmetric around 0 V. For instance, from the characteristics of Fig. 5, it can be seen that the threshold voltage for accumulating holes in the un- programmed device is about V_Gs=-2 V, whereas electron current starts flowing for VQ_S > -5V (in other words, the threshold for accumulating electrons is about V_Gs=-5V). AS a result, programming by a charge carrier type can occur for accumulation densities much lower than the density required to have an appreciable current of that carrier type in the channel. In particular, programming can occur for accumulation densities as low as 1 E6 cm^"2 of a charge carrier type.

Experiments were performed for analyzing what happens if the organic semiconductor is a unipolar semiconductor, by exposing a transistor with a pentacene organic semiconductor layer (as in Figure 1 ) to air. It is known that air induces electron traps impeding electron transport in pentacene. Figure 14 shows I_D-VQ_S characteristics for such an organic transistor with unipolar hole transport, wherein the V_Gs voltage is swept between -15V and +15V. The full triangle curve shows the initial transistor characteristics, while the full line with circles shows the characteristic after the first V_GS voltage sweep and the dashed lines with squares show the characteristics after subsequent V_GS voltage sweeps. The initial transistor characteristics have been measured by sweeping VQ_S from V_Gs=-3 V to V_Gs=+14.5V. When sweeping V_GS back to +3 V (open circles), no change in the transfer curve is detected. When sweeping further to V_GS=-15V, holes are trapped, such that the onset voltage shifts to V_GS=-7V. When the gate voltage is then sweeped back and forth between V_GS=-15 V and V_GS=+14.5 V, no substantial change in the transfer curve is seen (dashed lines with square symbols).

As electron transport is impeded, there is no electron accumulation and no electron trapping in the dielectric stack. Tunneling of holes into the gate dielectric, and trapping of holes in the dielectric stack of holes results in a shift of the transfer characteristic during the first sweep to V_GS = -15V. However, after this shift, when sweeping the gate voltage between -15V and +15V, the memory state does not change (dashed lines). This indicates that the trapped holes remain trapped and that for the voltage range used the holes are not released from the traps (i.e. the memory is not erased). In such a situation, higher voltages are needed to erase the memory. This is opposed to ambipolar devices of the present invention, for which transfer curves are shown in Figure 5. In this case, sweeping the gate voltage between -15V and +15V leads to repeated switching between the ON state and the OFF state.

Figure 15 shows l_D-V_Gs characteristics for an organic transistor with unipolar electron transport. The organic semiconductor layer comprises PTCDI- Ci₃H₁₇ as an organic semiconductor layer and the source and drain contacts comprise LiF/AI. The full triangles shows the initial transistor characteristic, while the open circles shows the characteristics after the first V_GS voltage sweep and the dashed line with squares show the characteristics after subsequent V_GS voltage sweeps. The initial transistor characteristics have been measured by sweeping V_Gs from +3V to -14.5 V and back to 3 V. When sweeping V_GS from +3V to +15V and back to +OV, the onset voltage shifts from ~1 V to ~3V. Subsequent scans of V_GS between +15V and -14.5V (dashed lines with square symbols) do not shift the characteristics any more.

It can be seen that in this case there is no hole trapping in the dielectric. Tunneling of electrons into the gate dielectric and trapping of electrons in the dielectric stack results in a shift of the transfer characteristics. However, after this shift, when sweeping the gate voltage between -15V and +15V, the memory state does not change (dashed lines with squares). This indicates that the trapped electrons remain trapped and that for the voltage range used the electrons are not released from the traps (i.e. the memory is not erased). In such a situation, higher voltages are needed to erase the memory. This is opposed to ambipolar devices of the present invention, for which transfer curves are shown in Figure 5. In this case, sweeping the gate voltage between -15V and +15V leads to repeated switching between the ON state and the OFF state.

In short, the organic memory element of the invention comprises an organic semiconductor material, a gate dielectric stack comprising a first dielectric layer acting as a barrier layer and a second dielectric layer of an organic material, and a gate electrode. The gate electrode is separated from the second dielectric layer through the barrier layer. For programming charge carriers are injected into the second dielectric layer by application of a programming pulse of a first voltage to the gate electrode to cause a shift of the threshold voltage. For erasing, an erasing pulse of a second voltage with opposite polarity to the first voltage is applied to the gate electrode to cause an opposite shift of the transistor threshold voltage to the OFF state threshold voltage. The organic semiconductor material is an ambipolar organic semiconductor material.

Claims

1. An organic memory element comprising an organic semiconductor layer, a gate dielectric stack comprising a first dielectric layer acting as a barrier layer and a second dielectric layer of an organic material, and a gate electrode, which gate electrode is separated from the second dielectric layer through the barrier layer, wherein for programming charge carriers are injected into the second dielectric layer by application of a programming pulse of a first voltage to the gate electrode, and wherein for erasing, an erasing pulse of a second voltage with opposite polarity to the first voltage is applied to the gate electrode, characterized in that the organic semiconductor material is an ambipolar organic semiconductor material, such that by application of a first of the programming pulse and the erasing pulse holes are injected from the organic semiconductor layer into the second dielectric layer and by application of the other electrons are injected from the organic semiconductor layer into the second dielectric layer.

2. The organic memory element as claimed in Claim 1 , wherein the barrier layer has a thickness in the range of 10 to 100 nm.

3. The organic memory element as claimed in Claim 1 or 2, wherein the second dielectric layer has a thickness in the range of 2 to 15 nm.

4. The organic memory element as claimed in any of claims 1 to 3, wherein the barrier layer has a leakage current lower than 1 e^"6 m A/cm² at an electric field of 5 (MV/cm).

5. The organic memory element as claimed in any of claims 1 to 4, wherein the barrier layer is provided by means of atomic layer deposition (ALD) or anodization.

6. The organic memory element as claimed in any of claims 1 to 5, wherein the accumulation of a carrier type at the interface between the semiconductor and the gate dielectric at gate voltages used for programming or erasing is at least 10⁶/cm².

7. The organic memory element as claimed in any of claims 1 to 6, wherein the memory element is a transistor that further comprises a source electrode and a drain electrode and a channel extending between the source electrode and the drain electrode, which channel has a channel length of 1 to 200 microns.

8. An integrated circuit comprising the organic memory element and a field effect transistor, which memory element and which field effect transistor comprise the same organic semiconductor material and wherein the barrier layer of the memory element is used as the gate dielectric of the field effect transistor.

9. A method of operating an organic memory element comprising an organic semiconductor material, a gate dielectric stack comprising a first dielectric layer or barrier layer and a second dielectric layer of an organic material, and a gate electrode, which gate electrode is separated from the second dielectric layer through the barrier layer, said memory element having a threshold voltage, said method comprising the steps of: programming the memory element through injection of charge carriers into the second dielectric layer by application of a first gate voltage to the gate electrode to cause a shift of the threshold voltage; erasing the memory element by application of a second gate voltage with opposite polarity to the first voltage to cause an opposite shift of the transistor threshold voltage to the OFF state threshold voltage, characterized in that the organic semiconductor material is an ambipolar organic semiconductor material, such that by application of a first of the programming pulse and the erasing pulse holes are injected from the organic semiconductor layer into the second dielectric layer and by application of the other electrons are injected from the organic semiconductor layer into the second dielectric layer.

10. The method as claimed in claim 9, wherein a cycle of programming and erasing is repeated for more than 10 times, particularly more than 50 times.

1 1. The method as claimed in claim 9 or 10, wherein the first and second voltage have an absolute value of at most 30V, preferably at most 20V.

12. The method as claimed in any one of claims 9 to 1 1 , wherein the first voltage is a negative voltage so as to inject holes into the second dielectric layer.

13. The method as claimed in any one of claims 9 to 12, wherein the first and second gate voltage are applied as pulses with a duration of less than 5 ms, preferably less than 2 ms.

14. A method of reading a memory element according to any one of claims 1 to 7.