WO2010086642A3 - Apparatus for use in near field rf communicators - Google Patents
Apparatus for use in near field rf communicators Download PDFInfo
- Publication number
- WO2010086642A3 WO2010086642A3 PCT/GB2010/050106 GB2010050106W WO2010086642A3 WO 2010086642 A3 WO2010086642 A3 WO 2010086642A3 GB 2010050106 W GB2010050106 W GB 2010050106W WO 2010086642 A3 WO2010086642 A3 WO 2010086642A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- voltage
- transitions
- voltage level
- programming
- communicators
- Prior art date
Links
- 230000007704 transition Effects 0.000 abstract 3
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Logic Circuits (AREA)
Abstract
A voltage level shifter has a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage levels (a and ã), and an output. The relative timing of transitions between first and second control voltage levels (a and ã) and transitions between the reset and programming voltage levels is controlled so that the voltage level shifter is not exposed to the programming voltage level during control voltage transitions.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0901313.7A GB2467183B (en) | 2009-01-27 | 2009-01-27 | Apparatus for use in near field rf communicators |
GB0901313.7 | 2009-01-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2010086642A2 WO2010086642A2 (en) | 2010-08-05 |
WO2010086642A3 true WO2010086642A3 (en) | 2010-11-18 |
Family
ID=40469143
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2010/050106 WO2010086642A2 (en) | 2009-01-27 | 2010-01-25 | Apparatus for use in near field rf communicators |
Country Status (2)
Country | Link |
---|---|
GB (1) | GB2467183B (en) |
WO (1) | WO2010086642A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104410403B (en) * | 2014-12-09 | 2017-10-03 | 复旦大学 | Twin voltage sub-threshold level converter |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6133756A (en) * | 1998-03-13 | 2000-10-17 | Nec Corporation | Output buffer control circuit |
US6433582B2 (en) * | 1997-02-25 | 2002-08-13 | Sharp Kabushiki Kaisha | Voltage level shifter circuit |
US20050237099A1 (en) * | 2004-04-21 | 2005-10-27 | Fujitsu Limited | Level conversion circuit |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001319490A (en) * | 2000-05-12 | 2001-11-16 | Mitsubishi Electric Corp | High voltage switch circuit, and semiconductor memory provided with high voltage switch circuit |
JP3548535B2 (en) * | 2001-01-24 | 2004-07-28 | Necエレクトロニクス株式会社 | Semiconductor circuit |
-
2009
- 2009-01-27 GB GB0901313.7A patent/GB2467183B/en active Active
-
2010
- 2010-01-25 WO PCT/GB2010/050106 patent/WO2010086642A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6433582B2 (en) * | 1997-02-25 | 2002-08-13 | Sharp Kabushiki Kaisha | Voltage level shifter circuit |
US6133756A (en) * | 1998-03-13 | 2000-10-17 | Nec Corporation | Output buffer control circuit |
US20050237099A1 (en) * | 2004-04-21 | 2005-10-27 | Fujitsu Limited | Level conversion circuit |
Also Published As
Publication number | Publication date |
---|---|
GB2467183A (en) | 2010-07-28 |
GB2467183B (en) | 2013-08-07 |
WO2010086642A2 (en) | 2010-08-05 |
GB0901313D0 (en) | 2009-03-11 |
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