WO2010079090A1 - Ied destiné à un système d'automatisation de sous-station, et procédé d'ingénierie associé - Google Patents
Ied destiné à un système d'automatisation de sous-station, et procédé d'ingénierie associé Download PDFInfo
- Publication number
- WO2010079090A1 WO2010079090A1 PCT/EP2009/067711 EP2009067711W WO2010079090A1 WO 2010079090 A1 WO2010079090 A1 WO 2010079090A1 EP 2009067711 W EP2009067711 W EP 2009067711W WO 2010079090 A1 WO2010079090 A1 WO 2010079090A1
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- WIPO (PCT)
- Prior art keywords
- network
- ied
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- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/201—Multicast operation; Broadcast operation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Definitions
- the invention relates to the field of Substation Automation (SA) systems for substations in high and medium voltage electric power networks.
- SA Substation Automation
- Substations in high and medium- voltage power networks include primary devices such as electrical cables, lines, bus bars, switches, power transformers and instrument transformers, which are generally arranged in switch yards and/or bays. These primary devices are operated in an automated way via a Substation Automation (SA) system.
- the SA system comprises secondary devices, among which Intelligent Electronic Devices (IED) are responsible for protection, control and monitoring of the primary devices.
- IED Intelligent Electronic Devices
- an IED controls actuators of assigned primary devices on the base of signals from assigned sensors for switch or tap changer position, temperature, voltage, current etc., signals from other IEDs, and signals from a supervisory system.
- an IED communicates a state or behaviour of its assigned primary devices, i.e. selected sensor readings, to other IEDs or to the supervisory system.
- the secondary devices may be assigned to hierarchical levels, i.e. the station level, the bay level, and the process level, the latter being separated from the bay level by a so-called process interface.
- IEDs on the station level of the SA system include a supervisory computer or station PC comprising an Operator Work Station (OWS) with a Human- Machine Interface (HMI) and running a Supervisory Control And Data Acquisition (SCADA) software, as well as a gateway for communication with a Network Control Centre (NCC).
- OWS Operator Work Station
- HMI Human- Machine Interface
- SCADA Supervisory Control And Data Acquisition
- NCC Network Control Centre
- IEDs on the bay level also termed bay units or protection and/or control IEDs in what follows, in turn are connected to each other as well as to the IEDs on the station level via an inter-bay or station bus primarily serving the purpose of exchanging commands and status information.
- Secondary devices on the process-level comprise sensors for voltage (VT), current (CT) and gas density measurements, contact probes for sensing switch and transformer tap changer positions, and/or actuators (I/O) for changing transformer tap positions, or for controlling switchgear like circuit breakers or disconnectors.
- Exemplary sensors such as non-conventional current or voltage transformers comprise an Analogue to Digital (AD) converter for sampling of analogue signals, and are connected to the bay units via a dedicated or intra-bay process bus, which can be considered as the process interface replacing the conventional hard-wired process interface.
- AD Analogue to Digital
- the latter connects conventional current or voltage transformers in the switchyard to the bay level equipment via dedicated copper wires, in which case the analogue signals of the instrument transformers are sampled by the bay units.
- IEC 61850-8-1 specifies the Manufacturing Message Specification (MMS, ISO/IEC 9506) protocol based on a reduced Open Systems Interconnection (OSI) protocol stack built upon the Transmission Control Protocol (TCP) and Internet Protocol (IP) in the transport and network layer, respectively, and upon Ethernet and/or RS-232C as physical media.
- OSI Open Systems Interconnection
- IEC 61850-8-1 specifies the Generic Object Oriented Substation Events (GOOSE) directly on the Ethernet link layer of the communication stack.
- GOOSE Generic Object Oriented Substation Events
- the standard defines a format to publish, as multicast messages on an industrial Ethernet, event-based messages and digitized measurement data from current or voltage sensors on the process level as a substitute to traditional copper wiring.
- SV or other process data may be transmitted over an inter-bay process bus, making the transmitted information available to neighbouring bays.
- the inter-bay process bus and the station bus can be merged into one single communication network.
- the communication network can be considered an inter-bay process bus that transmits, in addition to the process data, command and/or status related messages otherwise exchanged via a dedicated station bus.
- a protection IED it is no longer necessary for a protection IED to be hardwired to respective sensors in order to receive the necessary information required for computing a specific protection function. Instead, it is possible for a protection IED to subscribe to a data stream which is available on the system-wide SA communication network or a specific sub-network thereof.
- the process data is digitized, optionally provided with a time-stamp, and published by a process interface, i.e. either a sensor device itself incorporating Analogue to Digital (AD) converter functionality and being directly connected to the communication network, a different protection IED making its local measurements available, or a Merging Unit (MU) merging instantaneous signals of a plurality of connected sensors into a single network message.
- a process interface i.e. either a sensor device itself incorporating Analogue to Digital (AD) converter functionality and being directly connected to the communication network, a different protection IED making its local measurements available, or a Merging Unit (MU) merging instantaneous signals of a plurality of connected sensors into a single network message.
- AD Analogue to Digital
- MU Merging Unit
- IEC 61850 9-2 traffic is a multicast protocol, allowing the client device to subscribe to specific data streams, and neglect the streams which are not relevant.
- a significant amount of network traffic needs to be processed by the receiving devices.
- FPGA Field Programmable Gate Arrays
- the amount of measurement traffic needed to be processed on the IED devices easily exceeds the available computational power of those devices, and the amount of interrupts generated by the network interface, and the timely processing of the packet information can easily absorb the available CPU capacity of the IED devices and therefore impact the execution of time-critical tasks.
- Circuit IC containing a central processing unit that includes at least first and second processing cores.
- Each of the processing cores includes a full set of the components utilized by conventional single-core CPU to fetch, decode, and execute instructions and transfer information to and from other parts of the data processing system such as a global data storage or shared memory.
- the IC also includes input facilities that receive control input specifying which of the processing cores is to be utilized, e.g. to utilize the second core as a virtual first processing core upon determining that the first core is inactive or defective.
- the IC includes configuration logic that dynamically decodes the control input and, in response, selectively controls reception of input signals and transmission of output signals of one or more core of the processing cores in accordance with the control input.
- IEDs for SA such as bay units or substation PCs
- IEDs for SA are equipped with an Integrated Circuit with a Central Processing Unit CPU that includes a first processing core dedicated and configured to execute Protection and Control applications, and a second processing core, or network core, dedicated and configured to handle or decode network communication traffic.
- Protection and Control functionality in the IEDs is separated or isolated from communication issues, and the former is not impeded by the latter e.g. in case of communication network problems.
- the Protection and Control applications can still continue to operate, while the second processing core handling network traffic may see an interrupt flooding.
- the network core performs computationally expensive pre- or post-processing functionality in addition to the 9-2 communication stack.
- the latter includes receiving 9-2 packets from multiple data sources, decoding the packets, verifying the integrity of the data content and other security aspects as potentially required in the standard IEC 62351.
- Post-processing operations on behalf of specific protection functions such as Digital Fourier Transformation (DFT), Root Mean Square (RMS) calculation, Digital filtering, or Peak-to-Peak computation, generally necessitate a lot of computationally expensive floating point operations and iterative calculations.
- DFT Digital Fourier Transformation
- RMS Root Mean Square
- Peak-to-Peak computation generally necessitate a lot of computationally expensive floating point operations and iterative calculations.
- the proposed multi-core CPU enables a scalable software architecture that is easy to maintain and to update with new functionality. Specifically, it allows allocating the decoding of the 9-2 network traffic to a variable number of two or more network cores depending on a few parameters, such as e.g. the number of 9-2 sources or the frequency of samples, i.e. the number of network messages received by the IED per second. Furthermore, the plurality of network cores can be assigned to one or several Network Interface Cards (NIC), the number of which represents, at least for a station PC, an additional degree of flexibility.
- NIC Network Interface Cards
- the 9-2 multicast network traffic received is distributed or re-routed to the plurality of network cores, either by the single Network Interface Card (NIC), or by a programmable switch that is part of the SA communication network and connected to two or more NICs.
- the allocation of the network core is most conveniently based on the Source Media Access Code (MAC) address of the individual network messages.
- Said Source MAC address is easy to parse, i.e. it can be isolated from a received message without knowing or decoding the entire message content.
- the security standard IEC62351 is also transparent, i.e. the entire message content including MAC of a signed message can still be read.
- the instantiation of the 9-2 stack and post processing functionality required on each IED for handling the expected amount of 9-2 traffic can be done in a static fashion.
- the data streams which are processed on each core can be configured or pre-allocated during engineering time.
- a few parameters can be taken into account in order to ensure that the individual processing cores are not overloaded.
- a dynamic (re-)allocation at runtime of streams to network cores e.g. utilizing load- balancing algorithms taking into account the computation resource requirements of various pre-/post processing tasks, can be applied as well.
- hardware-based solutions also provide the possibility to separate and offload the processing and post-processing of network traffic.
- Field Programmable Gate Arrays (FPGA) based solutions which implement the decoding and post-processing logic in hardware and push the data through means like DMA (Direct Memory Access) to the application memory are equivalent solutions to the one proposed in this invention.
- FPGA Field Programmable Gate Arrays
- DMA Direct Memory Access
- adaptations such as including e.g. additional logic to handle security enhancements for IEC 61850, or a scaling in the number of supported sources, can require a change in hardware
- Fig.l shows some of the basic components of an Intelligent Electronic Device (IED) 1 for Substation Automation (SA), such as a Station PC, a bay unit, or any other embedded device with Protection and Control functionality.
- the IED 1 has a microprocessor or Central Processing Unit (CPU) 10 with a first processing core 100 dedicated to Protection and Control tasks, and a network core 101 for handling the network traffic received via a Network Interface Card (NIC) 11.
- the IED 1 is connected, via the NIC 11, to an SA communication network 2, preferably a process bus with IEC 61850 9-2 traffic.
- Other IEDs (not depicted) of the SA system publish measurement samples as multicast messages on the network 2.
- the NIC 11 filters the messages according to their destination MAC address and stores the measurement data in shared input memory 13.
- the 9-2 decoding stack on the network core 101 reads from the shared input memory 13, processes the information, and writes it to CPU core shared memory 103.
- Post-processing functionality running either on the network core 101 or on a different core can access the processed 9-2 message and perform additional post-processing functionality, the result of which is again stored in the CPU core shared memory 103.
- Protection and control functions executed on the processing core 100 can access either the decoded raw data or the additionally post- processed data from CPU core shared memory 103.
- the IED monitors the state of a substation or of a part there of and autonomously opens an assigned circuit breaker in case it detects a potentially dangerous situation such as overload.
- Multi-core microprocessors feature a single integrated circuit that includes two or more main processing cores sharing the same Random Access Memory (RAM), each of which may be utilized as if it were a separate CPU.
- RAM Random Access Memory
- each of the main cores provides computing power that equals or exceeds that of a conventional high-performance single core processor.
- the network core 101 is dedicated for processing 9-2 traffic (receiving, decoding, post-processing), whereas one or more cores 100 are available for the protection and control applications.
- Fig.2 depicts an IED with two network cores 101, 102.
- one network interface 11 receives all traffic, and distributes or forwards, based on configuration data resulting from the SA engineering, received packets to the network cores 101, 102 for further processing.
- the exact number of network cores depends e.g. on the number of measurement samples to be processed.
- an upper limit can be defined per core in terms of messages that it can process per second, depending e.g. on the CPU clock speed, the post-processing functionality executed, and accounting for some safety margin. This limit then can be related to number of sources times the sending frequency per source, giving an estimate on how many cores are required for the 9-2 processing.
- each of the cores has a dedicated network interface. Splitting of the network traffic is accomplished by a programmable switch 20 as a node of the SA communication network 2.
- the present invention is not limited to SA, but extends to process automation control in general.
- any process automation control device adapted to be connected to a digital process bus and configured to receive and process network messages further characterized in that the device has a multi-core CPU and that the network messages are handled by one of the cores of the multi-core CPU, may benefit from the advantages as mentioned herein.
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200980154325.2A CN102273148B (zh) | 2009-01-07 | 2009-12-22 | Sa系统的ied以及工程化sa系统的方法 |
BRPI0924193A BRPI0924193A2 (pt) | 2009-01-07 | 2009-12-22 | ied (dispositivo eletrônico inteligente), para um sistema sa (automação de subestação) e método de engenharia |
RU2011133066/08A RU2504913C2 (ru) | 2009-01-07 | 2009-12-22 | Интеллектуальные электронные устройства для системы автоматизации подстанции и способ ее разработки и управления |
US13/173,924 US20110257806A1 (en) | 2009-01-07 | 2011-06-30 | Ied for, and method of engineering, and sa system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP09150131A EP2207312B1 (fr) | 2009-01-07 | 2009-01-07 | Dispositif intelligent et procédé pour le développement d'un système SA |
EP09150131.2 | 2009-01-07 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/173,924 Continuation US20110257806A1 (en) | 2009-01-07 | 2011-06-30 | Ied for, and method of engineering, and sa system |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010079090A1 true WO2010079090A1 (fr) | 2010-07-15 |
Family
ID=40599222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2009/067711 WO2010079090A1 (fr) | 2009-01-07 | 2009-12-22 | Ied destiné à un système d'automatisation de sous-station, et procédé d'ingénierie associé |
Country Status (8)
Country | Link |
---|---|
US (1) | US20110257806A1 (fr) |
EP (1) | EP2207312B1 (fr) |
CN (1) | CN102273148B (fr) |
AT (1) | ATE554571T1 (fr) |
BR (1) | BRPI0924193A2 (fr) |
ES (1) | ES2385632T3 (fr) |
RU (1) | RU2504913C2 (fr) |
WO (1) | WO2010079090A1 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8315719B2 (en) * | 2009-12-30 | 2012-11-20 | Eduardo Pedrosa Santos | Decentralized system and architecture for remote real time monitoring of power transformers, reactors, circuit breakers, instrument transformers, disconnect switches and similar high voltage equipment for power plants and electric power substations |
DE102010060938A1 (de) * | 2010-12-01 | 2012-06-06 | Technische Universität Dortmund | Kontrollsystem |
US9489242B2 (en) * | 2014-09-30 | 2016-11-08 | Telefonaktiebolaget L M Ericsson (Publ) | Algorithm for faster convergence through affinity override |
CN110445105B (zh) * | 2019-07-30 | 2021-11-09 | 北京四方继保自动化股份有限公司 | 一种基于通用ied面向功能的变电站继电保护方法 |
RU2720318C1 (ru) * | 2019-11-29 | 2020-04-28 | Публичное акционерное общество "Транснефть" (ПАО "Транснефть") | Централизованное интеллектуальное электронное устройство системы автоматизированной электрической подстанции |
JP2021135777A (ja) * | 2020-02-27 | 2021-09-13 | 株式会社小松製作所 | 作業機械のコンポーネントのソフトウェア更新システムおよびソフトウェア更新方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001013590A1 (fr) * | 1999-08-17 | 2001-02-22 | Conexant Systems, Inc. | Circuit integre pourvu d'un processeur central et d'un co-processeur permettant de traiter le flux de trafic |
WO2002084957A2 (fr) * | 2001-04-13 | 2002-10-24 | Motorola, Inc., A Corporation Of The State Of Delaware | Manipulation de flux de donnees dans des processeurs de flux de donnees |
US6550020B1 (en) | 2000-01-10 | 2003-04-15 | International Business Machines Corporation | Method and system for dynamically configuring a central processing unit with multiple processing cores |
US20030231627A1 (en) * | 2002-06-04 | 2003-12-18 | Rajesh John | Arbitration logic for assigning input packet to available thread of a multi-threaded multi-engine network processor |
EP1551137A1 (fr) * | 2003-12-31 | 2005-07-06 | Alcatel | Contrôleur parallèle au niveau de la couche liaison de données dans un commutateur de réseau |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2461830C (fr) * | 2001-09-26 | 2009-09-22 | Interact Devices | Systeme et procede de communication de signaux multimedia |
US7280562B2 (en) * | 2003-02-18 | 2007-10-09 | Qualcomm Incorporated | Variable packet lengths for high packet data rate communications |
RU48084U1 (ru) * | 2004-12-20 | 2005-09-10 | Гуляев Юрий Васильевич | Автоматизированная информационная система для придания совместимости программно-аппаратным компонентам в гетерогенных информационных средах |
US8160824B2 (en) * | 2005-01-27 | 2012-04-17 | Electro Industries/Gauge Tech | Intelligent electronic device with enhanced power quality monitoring and communication capabilities |
DE602005008739D1 (de) * | 2005-08-24 | 2008-09-18 | Abb Technology Ag | Überwachung eines Industrie-Kommunikationsnetzes |
PL1850142T3 (pl) * | 2006-04-24 | 2009-06-30 | Abb Research Ltd | Testowanie poziomu systemowego dla systemów automatyzacji stacji elektroenergetycznych |
EP1850447A1 (fr) * | 2006-04-24 | 2007-10-31 | Abb Research Ltd. | Inspection de la configuration d'un appareil électronique intelligent |
EP2044509A2 (fr) * | 2006-07-21 | 2009-04-08 | Schweitzer Engineering Laboratories, Inc. | Procédé de configuration de dispositifs électroniques intelligents pour faciliter la standardisation de messages de communication parmi plusieurs dei à l'intérieur d'un réseau |
US7583771B2 (en) * | 2006-08-22 | 2009-09-01 | Schweitzer Engineering Laboratories, Inc. | Systems and methods for resampling unreliable data |
US7630863B2 (en) * | 2006-09-19 | 2009-12-08 | Schweitzer Engineering Laboratories, Inc. | Apparatus, method, and system for wide-area protection and control using power system data having a time component associated therewith |
US20080170508A1 (en) * | 2007-01-17 | 2008-07-17 | Abb Technology Ag | Channel integrity metric calculation |
KR100843130B1 (ko) * | 2007-01-30 | 2008-07-03 | 명지대학교 산학협력단 | Iec61850 기반의 변전소 자동화 시스템에서 온라인ied 고장 진단 장치 및 방법 |
US8587949B2 (en) * | 2007-03-27 | 2013-11-19 | Electro Industries/Gauge Tech | Electronic meter having user-interface and central processing functionality on a single printed circuit board |
EP1976177B1 (fr) * | 2007-03-30 | 2014-07-02 | ABB Technology AG | Systèmes d'automatisation de sous-station à disponibilité étendue |
US7856327B2 (en) * | 2007-10-09 | 2010-12-21 | Schweitzer Engineering Laboratories, Inc. | State and topology processor |
US9401839B2 (en) * | 2008-04-04 | 2016-07-26 | Schweitzer Engineering Laboratories, Inc. | Generation and control of network events and conversion to SCADA protocol data types |
CN101304181B (zh) * | 2008-07-08 | 2010-09-22 | 国电南瑞科技股份有限公司 | 基于面向通用对象的变电站事件机制的双网控制方法 |
US8560255B2 (en) * | 2008-12-12 | 2013-10-15 | Schneider Electric USA, Inc. | Power metering and merging unit capabilities in a single IED |
-
2009
- 2009-01-07 EP EP09150131A patent/EP2207312B1/fr active Active
- 2009-01-07 ES ES09150131T patent/ES2385632T3/es active Active
- 2009-01-07 AT AT09150131T patent/ATE554571T1/de active
- 2009-12-22 BR BRPI0924193A patent/BRPI0924193A2/pt not_active IP Right Cessation
- 2009-12-22 CN CN200980154325.2A patent/CN102273148B/zh active Active
- 2009-12-22 RU RU2011133066/08A patent/RU2504913C2/ru not_active IP Right Cessation
- 2009-12-22 WO PCT/EP2009/067711 patent/WO2010079090A1/fr active Application Filing
-
2011
- 2011-06-30 US US13/173,924 patent/US20110257806A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001013590A1 (fr) * | 1999-08-17 | 2001-02-22 | Conexant Systems, Inc. | Circuit integre pourvu d'un processeur central et d'un co-processeur permettant de traiter le flux de trafic |
US6550020B1 (en) | 2000-01-10 | 2003-04-15 | International Business Machines Corporation | Method and system for dynamically configuring a central processing unit with multiple processing cores |
WO2002084957A2 (fr) * | 2001-04-13 | 2002-10-24 | Motorola, Inc., A Corporation Of The State Of Delaware | Manipulation de flux de donnees dans des processeurs de flux de donnees |
US20030231627A1 (en) * | 2002-06-04 | 2003-12-18 | Rajesh John | Arbitration logic for assigning input packet to available thread of a multi-threaded multi-engine network processor |
EP1551137A1 (fr) * | 2003-12-31 | 2005-07-06 | Alcatel | Contrôleur parallèle au niveau de la couche liaison de données dans un commutateur de réseau |
Non-Patent Citations (3)
Title |
---|
MOHAMED RAYEES A B S ED - MUHAMMAD SALMAN YOUSUF ET AL: "Substation Automation Techniques and Future Trends", INNOVATIONS IN INFORMATION TECHNOLOGY, 4TH INTERNATIONAL CONFERENCE ON, IEEE, PI, 18 November 2007 (2007-11-18), pages 412 - 416, XP031226537, ISBN: 978-1-4244-1840-4 * |
PAWEAA GEPNER ET AL: "Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications", COMPUTATIONAL SCIENCE Â ICCS 2008; [LECTURE NOTES IN COMPUTER SCIENCE], SPRINGER BERLIN HEIDELBERG, BERLIN, HEIDELBERG, vol. 5101, 25 June 2008 (2008-06-25), pages 417 - 426, XP019090517, ISBN: 978-3-540-69383-3 * |
WAHEED A ET AL: "Performance Characterization of a Dual Quad-Core Based Application Oriented Networking System", NETWORKING, ARCHITECTURE, AND STORAGE, 2008. NAS '08. INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 12 June 2008 (2008-06-12), pages 295 - 302, XP031291975, ISBN: 978-0-7695-3187-8 * |
Also Published As
Publication number | Publication date |
---|---|
EP2207312A1 (fr) | 2010-07-14 |
CN102273148A (zh) | 2011-12-07 |
EP2207312B1 (fr) | 2012-04-18 |
ES2385632T3 (es) | 2012-07-27 |
RU2011133066A (ru) | 2013-05-10 |
US20110257806A1 (en) | 2011-10-20 |
BRPI0924193A2 (pt) | 2016-06-28 |
RU2504913C2 (ru) | 2014-01-20 |
ATE554571T1 (de) | 2012-05-15 |
CN102273148B (zh) | 2018-07-17 |
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