WO2010076649A3 - Packet processing system on chip device - Google Patents

Packet processing system on chip device Download PDF

Info

Publication number
WO2010076649A3
WO2010076649A3 PCT/IB2009/007914 IB2009007914W WO2010076649A3 WO 2010076649 A3 WO2010076649 A3 WO 2010076649A3 IB 2009007914 W IB2009007914 W IB 2009007914W WO 2010076649 A3 WO2010076649 A3 WO 2010076649A3
Authority
WO
WIPO (PCT)
Prior art keywords
processing system
packet processing
chip device
traffic
data storage
Prior art date
Application number
PCT/IB2009/007914
Other languages
French (fr)
Other versions
WO2010076649A2 (en
Inventor
Rakesh Kumar Malik
Klaps Bert
Jagmeet Singh Hanspal
Prasad Kunal
Amandeep Singh Gujral
Timothy M. Shanley
Kapil Suri
Dinesh Gupta
Arun Kumar Barman
Prashant Anand
Milan Vinodrai Purohit
Neeraj Gupta
Pradeept Kumar Banerjee
Priyadarshini Dixit
Original Assignee
Transwitch India Pvt. Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transwitch India Pvt. Ltd. filed Critical Transwitch India Pvt. Ltd.
Publication of WO2010076649A2 publication Critical patent/WO2010076649A2/en
Publication of WO2010076649A3 publication Critical patent/WO2010076649A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The present invention relates to the area of packet processing system on chip device which that estimates the queue fill level for a particular type of data stored in the data storage device, enables sharing of the data storage unit between different units that have different traffic characteristics as per their traffic requirements and ensure that traffic from any one does not adversely impact the other, enhances the performance of the memory by modifying the memory access pattern and maintains a certain rate of reading the packet fragments from the DDR at the transmission end.
PCT/IB2009/007914 2008-12-31 2009-12-31 Packet processing system on chip device WO2010076649A2 (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
IN2746MU2008 2008-12-31
IN2744MU2008 2008-12-31
IN2745MU2008 2008-12-31
IN2744/MUM/2008 2008-12-31
IN2742/MUM/2008 2008-12-31
IN2745/MUM/2008 2008-12-31
IN2746/MUM/2008 2008-12-31
IN2742MU2008 2008-12-31

Publications (2)

Publication Number Publication Date
WO2010076649A2 WO2010076649A2 (en) 2010-07-08
WO2010076649A3 true WO2010076649A3 (en) 2011-11-24

Family

ID=42310268

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2009/007914 WO2010076649A2 (en) 2008-12-31 2009-12-31 Packet processing system on chip device

Country Status (1)

Country Link
WO (1) WO2010076649A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101720259B1 (en) 2009-12-04 2017-04-10 나파테크 에이/에스 An apparatus and a method of receiving and storing data packets controlled by a central controller
KR101716832B1 (en) 2009-12-04 2017-03-27 나파테크 에이/에스 An assembly and a method of receiving and storing data while saving bandwidth by controlling updating of fill levels of queues

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996013922A2 (en) * 1994-10-26 1996-05-09 Cisco Systems, Inc. Computer network switching system with expandable number of ports
US20030021269A1 (en) * 2001-07-25 2003-01-30 International Business Machines Corporation Sequence-preserving deep-packet processing in a multiprocessor system
EP1482402A2 (en) * 2003-05-27 2004-12-01 Micronas GmbH Fill level capture in a buffer
US20080165795A1 (en) * 2007-01-10 2008-07-10 Shavit Baruch Device and method for processing data chunks
WO2008084179A1 (en) * 2007-01-08 2008-07-17 Nds Limited Buffer management
US20080181246A1 (en) * 2007-01-29 2008-07-31 Via Technologies, Inc. Data-packet processing method in network system
US20080183884A1 (en) * 2007-01-29 2008-07-31 Via Technologies, Inc. Data-packet processing method in network system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996013922A2 (en) * 1994-10-26 1996-05-09 Cisco Systems, Inc. Computer network switching system with expandable number of ports
US20030021269A1 (en) * 2001-07-25 2003-01-30 International Business Machines Corporation Sequence-preserving deep-packet processing in a multiprocessor system
EP1482402A2 (en) * 2003-05-27 2004-12-01 Micronas GmbH Fill level capture in a buffer
WO2008084179A1 (en) * 2007-01-08 2008-07-17 Nds Limited Buffer management
US20080165795A1 (en) * 2007-01-10 2008-07-10 Shavit Baruch Device and method for processing data chunks
US20080181246A1 (en) * 2007-01-29 2008-07-31 Via Technologies, Inc. Data-packet processing method in network system
US20080183884A1 (en) * 2007-01-29 2008-07-31 Via Technologies, Inc. Data-packet processing method in network system

Also Published As

Publication number Publication date
WO2010076649A2 (en) 2010-07-08

Similar Documents

Publication Publication Date Title
WO2009010972A3 (en) Device, system, and method of publishing information to multiple subscribers
WO2010036819A3 (en) System and method of providing multiple virtual machines with shared access to non-volatile solid-state memory using rdma
WO2009107089A3 (en) Apparatus and method for shared buffering between switch ports
WO2010045000A3 (en) Hot memory block table in a solid state storage device
WO2012145533A3 (en) Shared resource and virtual resource management in a networked environment
WO2008094475A3 (en) Flash storage partial page caching
WO2009044904A3 (en) Semiconductor memory device
WO2012096503A3 (en) Storage device for adaptively determining a processing technique with respect to a host request based on partition data and an operating method for the storage device
WO2011019487A3 (en) On-die logic analyzer for semiconductor die
WO2010056587A3 (en) Shared virtual memory
GB0622613D0 (en) A data storage device
WO2011034673A3 (en) Memory device and method
WO2008055272A3 (en) Integrating data from symmetric and asymmetric memory
WO2012096972A3 (en) Vehicle information system with customizable user interface
WO2010016869A3 (en) Phase change memory structures and methods
WO2009134462A3 (en) Method and system to predict the likelihood of topics
WO2008022094A3 (en) Data storage device
WO2008016488A3 (en) Virtual readers for scalable rfid infrastructures
WO2010144913A3 (en) Memory change track logging
WO2009129310A3 (en) Method and system for media initialization via data sharing
EP2047368A4 (en) Nonvolatile memory system, and data read/write method for nonvolatile memory system
WO2011048572A3 (en) An in-memory processor
TW200951716A (en) Memory system
WO2012094481A3 (en) Memory address translation
WO2007015773A3 (en) Memory device and method having multiple address, data and command buses

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09836149

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09836149

Country of ref document: EP

Kind code of ref document: A2