WO2010076649A3 - Packet processing system on chip device - Google Patents
Packet processing system on chip device Download PDFInfo
- Publication number
- WO2010076649A3 WO2010076649A3 PCT/IB2009/007914 IB2009007914W WO2010076649A3 WO 2010076649 A3 WO2010076649 A3 WO 2010076649A3 IB 2009007914 W IB2009007914 W IB 2009007914W WO 2010076649 A3 WO2010076649 A3 WO 2010076649A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- processing system
- packet processing
- chip device
- traffic
- data storage
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The present invention relates to the area of packet processing system on chip device which that estimates the queue fill level for a particular type of data stored in the data storage device, enables sharing of the data storage unit between different units that have different traffic characteristics as per their traffic requirements and ensure that traffic from any one does not adversely impact the other, enhances the performance of the memory by modifying the memory access pattern and maintains a certain rate of reading the packet fragments from the DDR at the transmission end.
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IN2746MU2008 | 2008-12-31 | ||
IN2744MU2008 | 2008-12-31 | ||
IN2745MU2008 | 2008-12-31 | ||
IN2744/MUM/2008 | 2008-12-31 | ||
IN2742/MUM/2008 | 2008-12-31 | ||
IN2745/MUM/2008 | 2008-12-31 | ||
IN2746/MUM/2008 | 2008-12-31 | ||
IN2742MU2008 | 2008-12-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2010076649A2 WO2010076649A2 (en) | 2010-07-08 |
WO2010076649A3 true WO2010076649A3 (en) | 2011-11-24 |
Family
ID=42310268
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2009/007914 WO2010076649A2 (en) | 2008-12-31 | 2009-12-31 | Packet processing system on chip device |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2010076649A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101720259B1 (en) | 2009-12-04 | 2017-04-10 | 나파테크 에이/에스 | An apparatus and a method of receiving and storing data packets controlled by a central controller |
KR101716832B1 (en) | 2009-12-04 | 2017-03-27 | 나파테크 에이/에스 | An assembly and a method of receiving and storing data while saving bandwidth by controlling updating of fill levels of queues |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996013922A2 (en) * | 1994-10-26 | 1996-05-09 | Cisco Systems, Inc. | Computer network switching system with expandable number of ports |
US20030021269A1 (en) * | 2001-07-25 | 2003-01-30 | International Business Machines Corporation | Sequence-preserving deep-packet processing in a multiprocessor system |
EP1482402A2 (en) * | 2003-05-27 | 2004-12-01 | Micronas GmbH | Fill level capture in a buffer |
US20080165795A1 (en) * | 2007-01-10 | 2008-07-10 | Shavit Baruch | Device and method for processing data chunks |
WO2008084179A1 (en) * | 2007-01-08 | 2008-07-17 | Nds Limited | Buffer management |
US20080181246A1 (en) * | 2007-01-29 | 2008-07-31 | Via Technologies, Inc. | Data-packet processing method in network system |
US20080183884A1 (en) * | 2007-01-29 | 2008-07-31 | Via Technologies, Inc. | Data-packet processing method in network system |
-
2009
- 2009-12-31 WO PCT/IB2009/007914 patent/WO2010076649A2/en active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996013922A2 (en) * | 1994-10-26 | 1996-05-09 | Cisco Systems, Inc. | Computer network switching system with expandable number of ports |
US20030021269A1 (en) * | 2001-07-25 | 2003-01-30 | International Business Machines Corporation | Sequence-preserving deep-packet processing in a multiprocessor system |
EP1482402A2 (en) * | 2003-05-27 | 2004-12-01 | Micronas GmbH | Fill level capture in a buffer |
WO2008084179A1 (en) * | 2007-01-08 | 2008-07-17 | Nds Limited | Buffer management |
US20080165795A1 (en) * | 2007-01-10 | 2008-07-10 | Shavit Baruch | Device and method for processing data chunks |
US20080181246A1 (en) * | 2007-01-29 | 2008-07-31 | Via Technologies, Inc. | Data-packet processing method in network system |
US20080183884A1 (en) * | 2007-01-29 | 2008-07-31 | Via Technologies, Inc. | Data-packet processing method in network system |
Also Published As
Publication number | Publication date |
---|---|
WO2010076649A2 (en) | 2010-07-08 |
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