WO2010060289A1 - 一种多核处理器的任务分配方法、系统及设备 - Google Patents

一种多核处理器的任务分配方法、系统及设备 Download PDF

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Publication number
WO2010060289A1
WO2010060289A1 PCT/CN2009/071648 CN2009071648W WO2010060289A1 WO 2010060289 A1 WO2010060289 A1 WO 2010060289A1 CN 2009071648 W CN2009071648 W CN 2009071648W WO 2010060289 A1 WO2010060289 A1 WO 2010060289A1
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state
processor
task
core
processor core
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PCT/CN2009/071648
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English (en)
French (fr)
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侯忠明
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华为技术有限公司
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Publication of WO2010060289A1 publication Critical patent/WO2010060289A1/zh
Priority to US13/099,960 priority Critical patent/US8763002B2/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention relates to a task allocation method, system and device for a multi-core processor.
  • the application is filed on November 3, 2008, and the application number is 200810225648. 3, the invention name is "a multi-core processor task allocation method and system.
  • the priority of the Chinese Patent Application the entire disclosure of which is incorporated herein by reference.
  • the present invention relates to the field of communications technologies, and in particular, to a task allocation method, system, and device for a multi-core processor.
  • processor performance has been overcome by simply increasing the main frequency.
  • the current mainstream trend is to use a processor multi-core design, such as a dual-core PC (Personal Computer) general-purpose processor.
  • the tasks of the processor are often unbalanced in the time domain, so the need for processing power is also different. For example, when the network is busy, it may require the full processing power of the network processor. When the network is idle, it may only be necessary to have the processing power of one or two processor cores.
  • the margin of processing power is Reducing processor power provides a possible space.
  • Low power design LPD, Low Power Design
  • there are some mature methods at the device level such as stopping the clock signal of an idle device or cutting off the voltage of the part.
  • a task allocation method for a multi-core processor is provided, the method comprising:
  • the task allocator determines whether the processor core is idle according to the status of the status register
  • the task allocator transmits a message packet to an idle processor core through a transmission channel.
  • a task allocation method for a multi-core processor which is used in a multi-core processor, the multi-core processor includes a plurality of sub-processing systems, and the method includes:
  • the buffer sends the message packet to a processor core of the sub-processing system.
  • a task distribution system for a multi-core processor comprising: a task allocator and a sub-processing system, the sub-processing system comprising a status register, a processor core, and a transmission channel, wherein
  • the status register is configured to send status information of the sub-processing system to the task distributor, where the status information includes whether a processor core of the sub-processing system is in an idle state, and the idle status includes waiting, sleeping, Or closed;
  • the task distributor is configured to send a message packet to the sub processing system
  • the transmission channel is configured to transmit the message packet sent by the task distributor to the processor core, where a transmission path of the transmission channel includes at least one buffer;
  • the task allocator sends the message packet to the buffer cache and wakes up the processor core when the processor core is in a sleep or off state, when the processor core is woken up
  • the buffer sends the message packet to the processor core.
  • FIG. 1 is a schematic diagram of a task allocation system of a multi-core processor according to Embodiment 1 of the present invention
  • FIG. 2 is another schematic diagram of a task allocation system of a multi-core processor according to Embodiment 1 of the present invention
  • FIG. 3 is a flowchart of a task allocation method of a multi-core processor according to Embodiment 2 of the present invention.
  • FIG. 4 is a flowchart of a task allocation method of a multi-core processor according to Embodiment 3 of the present invention.
  • FIG. 5 is a schematic structural diagram of a path controller according to Embodiment 4 of the present invention.
  • FIG. 6 is a schematic structural diagram of a buffer provided in Embodiment 5 of the present invention. detailed description
  • the multi-core processor realizes low power consumption without reducing the processing capability of the burst data and the system performance, and the embodiment of the present invention provides a task assignment of the multi-core processor.
  • the method, the system and the device are described in the following embodiments, and the technical solutions provided by the embodiments of the present invention are described.
  • an embodiment of the present invention provides a multi-core processor task distribution system 100.
  • the multi-core processor task distribution system 100 includes a task distributor 20 and a plurality of sub-processing systems 0 to X.
  • the sub-processing system 0 is described below as an example.
  • the sub-processing system 0 includes a processor core 12, a buffer 14, and a status register 16.
  • the input end and the output end of the buffer 14 are respectively connected to the task distributor 20 and the processor core 12 for receiving task information from the task distributor 20 and transmitting the task information to the processor core 12.
  • the status register 16 is in communication with the buffer 14 and the processor core 12 for feeding back the status of the processor core 12 and the buffer 14 to the task distributor 20.
  • the task distributor 20 distributes the tasks to the plurality of sub-processing systems 0 to X based on the judgment results reflected by the respective status registers in the multi-core processor task allocation system 100.
  • status register 16 maintains the state of supervisory processor core 12 and buffer 14.
  • the status register 16 feeds back to the task distributor 20 that the sub-processing system 0 to which it belongs is in a busy state.
  • the status register 16 feeds back to the task distributor 20 that the sub-processing system 0 to which it belongs is in an idle state.
  • the status register 16 may include a first status bit in the information fed back to the task distributor 20 for indicating whether the sub-processing system 0 to which it belongs is in an idle state.
  • the status register 16 may further include a second status bit in the information fed back to the task distributor 20, which is used to indicate the current status of the sub-processing system 0 to which it belongs, that is, the specific one in the idle state.
  • a state condition such as waiting, hibernation, or shutdown.
  • the task allocator 20 can preferentially assign tasks to the sub-processing system in the waiting state, avoiding the energy consumption and efficiency of waking up the sub-processing system in the dormant and closed states. reduce.
  • the information fed back to the task distributor 20 by the status register 16 may further include a third status bit for indicating the processor core.
  • the degree of idleness of 12 such as a few threads are idle, and task dispatcher 20 prioritizes assigning tasks to processor cores 12 that are highly idle when assigning tasks.
  • the buffer 14 may be implemented in the form of a FIFO (First In First Out, FIFO). In other alternative embodiments, other types of buffers may also be used. The implementation of the embodiments of the present invention will not be affected.
  • FIFO First In First Out
  • the multi-core processor task assignment system 100 of the embodiment of the present invention determines the state of the sub-processing system through the status register 16, if there is a task that needs to be allocated, and the active sub-processing system is busy.
  • the task allocator 20 learns that the sub-processing systems of the dormant or off states can process the tasks according to the status register 16 of the sub-processing system in the dormant or off state, and the task distributor 20 can first store the tasks in the buffer 14, and The internal processor core 12 of the sub-processing system in the dormant or off state is awakened, thereby improving the efficiency of task processing.
  • its corresponding processor core 12 can be woken up by the buffer 14.
  • the embodiment of the present invention fully utilizes the characteristics of the multi-core processor structure, and utilizes the buffer and the status register.
  • the task distributor can also assign tasks to the task, so that when the processor core is Call After waking up, it can be processed in time to improve the efficiency of task processing.
  • an embodiment of the present invention further provides another multi-core processor task distribution system 200.
  • the differences from the multi-core processor task assignment system 100 provided by the embodiment of the present invention are omitted, and the difference between the multi-core processor task assignment system 200 of the present embodiment and the multi-core processor task assignment system 100 described in the previous embodiment is omitted.
  • the sub-processing system further includes a bypass (pass) 213 and a path controller 215, wherein the path controller 215 is in communication with the task distributor 220 and receives task information sent by the task distributor 220, and the path controller 215 The transmission channel of the task information is selected based on the status information stored in the status register 216.
  • the path controller 215 selects the buffer 214 as the path for the task information transmission; when the processor core 212 is waiting In the state, the path controller 215 selects the bypass 213 as the path for the task information transmission, and the bypass 213 can directly send the received task message to the processor core 212 in the waiting state to speed up the processing speed of the task information;
  • the path controller 215 sends the task information through the buffer 214, and the buffer 214 receives and caches the task message while waking up the processor core 212 in the sleep or shutdown state. After the kernel 212 is woken up, the buffer 214 sends the cached task message to the processor core 212.
  • the system provided by the embodiment of the present invention can flexibly configure according to application scenarios and data traffic by setting a status register and a transmission channel, thereby improving the efficiency of processing tasks of the multi-core processor, and achieving low power consumption without reducing system performance;
  • the switching state of the processor core is shielded. From the perspective of the task distributor, all processor cores are available, ensuring that the power consumption is reduced without reducing the processing power of burst data.
  • the embodiment of the invention provides a task allocation method for a multi-core processor, the method comprising:
  • the task allocator determines whether the processor core is idle according to the state of the status register
  • the message packet is then transmitted to the free processor core through the transport channel.
  • the task allocation method of the multi-core processor provided by the embodiment of the present invention is described below with reference to the accompanying drawings.
  • the embodiment of the present invention provides a task allocation method for a multi-core processor, which is set between a task allocator and a processor core.
  • the transmission channel is a buffer as an example. Referring to FIG. 3, the method includes:
  • the task allocator finds an idle processor core according to the busy state of the status register corresponding to each processor core, and then sends the message packet to the idle processor core through the buffer. If the free processor core is in a sleep or shutdown state, execute 302; if the idle processor core is in a wait state, execute 304.
  • the state register is set according to the state of the internal thread, to 8 threads.
  • a processor core can process up to 8 tasks simultaneously, with a weight of 0-8 to indicate the busy state of the processor core. If all 8 threads are idle, the third status bit of the status register is 8. If 3 are occupied and 5 are idle, the third status bit of the status register is 5.
  • the task allocator usually gives priority to the processor core with a high degree of idleness in the status register, and the multi-threaded processor core can only shut down the processor core when all internal threads are idle.
  • the task allocator allocates tasks in the active kernel, at this point, in order to achieve a balance between efficiency and power consumption, it can be set according to the processing power of the processor core, when the idle thread ratio in the active processor core is higher than the shutdown threshold. Then turn off a processor core, the kernel is set to inactive, and automatically stop working after all internal threads have finished running.
  • the processor core priority allocation algorithm with high idleness is still executed in all active processor cores.
  • the processor core is in a sleep or shutdown state, and the message packet sent by the task distributor to the processor core is temporarily stored in the buffer, and the processor core is woken up and the status register is set to be busy.
  • the processor core When the processor core is in the sleep state, the power consumption of the entire system is reduced and the processor core in the sleep state can be quickly woken up, and the buffer pressure of the buffer is small.
  • the status register is reset to the idle state, and then ends.
  • the processor core When the status register is reset to the idle state, the processor core is in an assignable task state from the perspective of the task distributor.
  • the processor core is in a wait state, the buffer receives the message packet sent by the task distributor, and directly transmits the received message packet to the processor core for processing, and sets the status register to a busy state;
  • the processor core since the processor core is in the waiting state, the message packets transmitted through the buffer can be directly processed without waiting. At this point, the processor core can process the message packets that are already being received, but not the new message packets.
  • the processor core When the status register is reset to the idle state, the processor core is in an assignable task state from the perspective of the task distributor.
  • the multi-core processor dynamically switches through the busy state of the status register, and shields the influence of the switch state of the processor core on the task distributor when assigning tasks. Even if the processor core is off, from the task allocator point of view, the closed processor core is still available, and all processor cores are available, ensuring that while reducing power consumption, Reduce the ability to process bursty data.
  • Example 3
  • the embodiment of the present invention further provides a method for task allocation of a multi-core processor, and the transmission channel set between the task distributor and the processor core includes a bypass and a buffer as an example for description. Referring to FIG. 4, the method is described. Includes:
  • the task distributor searches for an idle processor core according to the busy state displayed by the status register corresponding to each processor core, and then sends the received message packet to the idle processor core for processing.
  • setting the idle or busy state of the status register may be implemented according to specific needs, for example, according to whether the single-threaded processor core is processing data, thereby defining the single thread.
  • the busy state of the kernel if the processor core is processing a task, or if there is a task stored in the buffer, it is busy; otherwise, when the processor core is not processing the task, and there is no task in the buffer , it is idle. More specifically, the idle state includes three cases in which the processor core waits for a processing task, sleep, and shutdown.
  • an idle kernel may be randomly selected, or an idle kernel may be selected according to a preset optimization selection algorithm, and the embodiment of the present invention does not limit the specific selection. Ways and methods.
  • the state register is set according to the state of the internal thread, taking an 8-threaded processor core as an example, that is, one processor core can simultaneously process up to 8 tasks, with a weight of 0. -8 to indicate that the processor core is busy and idle. If all 8 threads are idle, the third status bit of the status register is 8. If 3 are occupied and 5 are idle, the third status bit of the status register is 5. .
  • the task allocator usually prefers to send the task to the processor core with a high degree of idleness in the status register, while the multi-threaded processor core can shut down the processor core or put the processor core to sleep only if all internal threads are idle.
  • the multi-threaded processor core is divided into active and inactive states.
  • the task allocator only assigns tasks in the active kernel.
  • the processing power setting of the processor core when an idle thread in the active processor core is higher than the shutdown threshold, one processor core is turned off, and the kernel is set to be inactive, and after all internal threads have finished running, automatically Stop working; the task is still executing tasks in all working processor cores and the idle core processor assigns tasks preferentially.
  • the idle degree is set according to the number of idle threads in the multi-thread
  • the status register of each multi-thread processor core sets the state value according to the idle degree.
  • the task allocator preferentially selects the multi-thread processor core with the largest number of idle threads in the active kernel for allocation according to the degree of idleness.
  • the kernel status of the processor is described as follows:
  • the multi-threaded kernel has the difference between active and inactive states, and the above states of "idle” and "busy" are only valid in the active kernel, and the active kernel is internally closed or not, and the task allocator is transparent. Assigned in the active kernel. For an inactive kernel, it can also be seen as always "busy". In fact, it does not participate in the work, and the task allocator does not assign tasks to it.
  • the path controller corresponding to the idle processor core selects a channel to transmit a message packet according to the idle state of the processor core. If the processor core is in the sleep or shutdown state, execute 403, and if the processor core is in the wait state, execute 405.
  • the idle state of the processor core may be a wait state, a sleep state, or a shutdown state according to the length of idle time.
  • the busy state transitions to the idle state. Specifically, the processor core first transitions to a wait state, and when the duration of the wait state reaches a set time value, the processor core switches from a wait state to a sleep state or a shutdown state, thereby reducing power consumption.
  • the clock when the processor core is idle, the clock can be turned off to achieve low power consumption, and the mode can switch the wake-up speed quickly; or the power of a single processor core can be turned off to achieve low power consumption, which is more power-saving.
  • the switch wake-up time is relatively long, and the required cache is larger.
  • the power consumption requirement is high, the power supply of the single processor core can be respectively turned off, and the switch wake-up time requirement is required.
  • the first way to turn off the clock can be used.
  • the specific method used to achieve low power consumption depends on the specific application.
  • the processor core When the status register is reset to the idle state, the processor core is in an assignable task state from the perspective of the task distributor.
  • the processor core When the status register is reset to the idle state, the processor core is in an assignable task state from the perspective of the task distributor.
  • the multi-core processor in the embodiment of the present invention dynamically switches through the busy state of the status register, and the task distributor allocates a kernel task according to the state of the status register, and implements transmission of the message packet according to the selected transmission channel (buffer or bypass). Even if the multi-core processor is off, from the perspective of the task distributor, the closed multi-core processor is still in a state of assignable tasks, ensuring that the idle processor core is turned off to reduce power consumption, and Reduce the ability to process bursty data.
  • an embodiment of the present invention provides a path controller, where the path controller includes:
  • the receiving module 501 is configured to receive a message packet sent by the task distributor.
  • the selection module 502 is configured to select a transmission channel to transmit a message packet.
  • the selection module 502 specifically includes:
  • a first selecting unit configured to: when the state of the idle processor core is in a waiting state, select a bypass as a transmission channel, and send the received message packet to the bypass;
  • a second selecting unit configured to select a buffer as a transmission channel when the state of the idle processor core is in a sleep state or a closed state, and send the received message packet to the buffer.
  • the path controller provided by the embodiment of the invention can implement the selection of the transmission channel, and further implement the transmission of the message packet according to the selected transmission channel, thereby improving the efficiency of the processing task of the multi-core processor, so that the multi-core processor does not reduce the pair. Under the premise of burst data processing capability and system performance, low power consumption is achieved.
  • Example 5
  • an embodiment of the present invention provides a buffer, where the buffer includes:
  • the receiving module 601 is configured to receive a message packet transmitted by the path controller;
  • the cache module 602 is configured to cache the message packet received by the receiving module 601.
  • Wake-up module 603, a processor core for waking up sleep or shutdown
  • the transmission module 604 is configured to: when the wake-up module 603 wakes up the processor core, transmit the message packet buffered by the cache module 602 to the wake-up processor core.
  • the transmission module 604 is further configured to directly send the message packet received by the receiving module 601 to the processor core in an idle state.
  • the buffer provided by the embodiment of the present invention caches the received message packet while the processor core is in a dormant or off state, and wakes up the processor core. After the processor core is woken up, the buffered message packet is sent. Thereby, the efficiency of the multi-core processor processing task is improved, and the multi-core processor realizes low power consumption without reducing the processing capability and system performance of the burst data.
  • the present invention can be implemented by hardware or by software plus a necessary general hardware platform.
  • the technical solution of the present invention may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including several The instructions are for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present invention.

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Description

一种多核处理器的任务分配方法、 系统及设备 本申请要求于 2008年 11月 3日提交中国专利局, 申请号为 200810225648. 3, 发明名称 为 "一种多核处理器的任务分配方法、 系统及设备" 的中国专利申请的优先权, 其全部内容 通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域, 特别涉及一种多核处理器的任务分配方法、 系统及设备。 背景技术 书
在高性能处理器设计中, 靠单纯提高主频实现处理器性能提升已经遇到瓶颈, 目前主流 的趋势是使用处理器多内核设计, 例如 PC (Personal Computer, 个人计算机) 通用处理器 的双核以及网络处理器的几十个处理器内核的设计。 在现实中, 处理器的任务在时间域上往 往是不均衡的, 因此对处理能力的需求也有所不同。 例如, 网络繁忙时, 可能需要网络处理 器的全部处理能力, 而网络较空闲时, 可能只需要等效一两个处理器内核的处理能力就足够 了, 这种处理能力上的裕量, 为降低处理器功耗提供了可能的空间。 关于低功耗设计 (LPD, Low Power Design), 目前在器件级上已有一些比较成熟的方法, 比如停止闲置器件的时钟信 号或者切断该部分的电压。
现有技术中, 当处理器空闲时, 保存现场, 然后整个处理器进入休眠状态。 当有任务要 处理时, 恢复现场, 唤醒处理器进行处理。
在实现本发明的过程中, 发明人发现: 现有技术中由于整个处理器进入休眠, 此时无法 处理任何实时数据。 而当有任务需要处理时只能先唤醒处理器, 然后才发送任务信息, 这样 处理任务的效率就受到了影响。 发明内容
为了提高多核处理器处理任务的效率, 使多核处理器在不降低对突发数据的处理能力及 系统性能的前提下, 实现低功耗, 本发明实施例提供了一种多核处理器的任务分配方法、 系 统及设备, 所述技术方案如下: 一方面, 提供了一种多核处理器的任务分配方法, 所述方法包括:
任务分配器根据状态寄存器的状态判断处理器内核是否空闲;
所述任务分配器通过传输通道向空闲的处理器内核传输消息包。
另一方面, 还提供了一种多核处理器的任务分配方法, 用于多核处理器中, 所述多核处 理器包括多个子处理系统, 所述方法包括:
通过状态寄存器读取所述多个子处理系统的状态信息, 所述状态信息显示所述多个子处 理系统的当前状态, 所述当前状态包括等待、 休眠或关闭;
向处于休眠或关闭状态的子处理系统的缓冲器发送消息包;
唤醒所述处于休眠或关闭状态的子处理系统;
所述缓冲器将所述消息包发送给所述子处理系统的处理器内核。
再一方面, 还提供了一种多核处理器的任务分配系统, 所述系统, 包括: 任务分配器和 子处理系统, 所述子处理系统包括状态寄存器、 处理器内核及传输通道, 其中,
所述状态寄存器, 用于向所述任务分配器发送所述子处理系统的状态信息, 所述状态信 息包括所述子处理系统的处理器内核是否处于空闲状态, 所述空闲状态包括等待、 休眠或关 闭;
所述任务分配器, 用于向所述子处理系统发送消息包;
所述传输通道, 用于将所述任务分配器发送的所述消息包传送给所述处理器内核, 所述 传输通道的传输路径中至少包括一个缓冲器;
其中, 当所述处理器内核处于休眠或关闭状态时, 所述任务分配器将所述消息包发送给 所述缓冲器缓存, 并唤醒所述处理器内核, 当所述处理器内核被唤醒后, 所述缓冲器将所述 消息包发送给所述处理器内核。
本发明实施例提供的技术方案的有益效果是:
可以根据应用场景和数据流量灵活配置, 提高了多核处理器处理任务的效率, 在不降低 系统性能的前提下实现了低功耗; 屏蔽了处理器内核的开关状态, 从任务分配器来看, 所有 的处理器内核都是可用的, 确保了在降低功耗的同时, 不降低对突发数据的处理能力。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案, 下面将对实施例或现有技术 描述中所需要使用的附图作简单地介绍, 显而易见地, 下面描述中的附图仅仅是本发明的一 些实施例, 对于本领域普通技术人员来讲, 在不付出创造性劳动的前提下, 还可以根据这些 附图获得其他的附图。
图 1是本发明实施例 1提供的多核处理器的任务分配系统示意图;
图 2是本发明实施例 1提供的多核处理器的任务分配系统的另一种示意图;
图 3是本发明实施例 2提供的多核处理器的任务分配方法流程图;
图 4是本发明实施例 3提供的多核处理器的任务分配方法流程图;
图 5是本发明实施例 4提供的路径控制器结构示意图;
图 6是本发明实施例 5提供的缓冲器结构示意图。 具体实施方式
下面将结合本发明实施例中的附图, 对本发明实施例中的技术方案进行清楚、 完整地描 述, 显然, 所描述的实施例仅是本发明一部分实施例, 而不是全部的实施例。 基于本发明中 的实施例, 本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例, 都 属于本发明保护的范围。
为了提高多核处理器处理任务的效率, 使多核处理器在不降低对突发数据的处理能力及 系统性能的前提下, 实现低功耗, 本发明实施例提供了一种多核处理器的任务分配方法、 系 统及设备, 详见如下各实施例, 对本发明实施例所提供的技术方案进行描述: 实施例 1
请参照图 1, 本发明实施例提供了一种多核处理器任务分配系统 100, 所述多核处理器任 务分配系统 100, 包括任务分配器 20, 及多个子处理系统 0至 X。
下面以子处理系统 0为例进行说明,该子处理系统 0包括一处理器内核 12、一缓冲器 14、 及一状态寄存器 16。 其中, 缓冲器 14的输入端和输出端分别与任务分配器 20和处理器内核 12相通, 用于自任务分配器 20处接收任务信息, 并将该任务信息发送给处理器内核 12。 状 态寄存器 16与缓冲器 14及处理器内核 12相通, 用于将处理器内核 12和缓冲器 14的状态, 反馈给任务分配器 20。
而在实际应用中,所述任务分配器 20根据该多核处理器任务分配系统 100中的各个状态 寄存器所反映的判断结果, 向多个子处理系统 0至 X分发任务。
在实际应用中, 状态寄存器 16保持监控处理器内核 12和缓冲器 14的状态。在本发明实 施例中, 当所述处理器内核 12正在处理任务、 或缓冲器 14中保存有任务信息时, 状态寄存 器 16向任务分配器 20反馈其所属的子处理系统 0处于忙碌状态。而当处理器内核 12处于等 待、 休眠、 或关闭状态, 且缓冲器 14中并未保存有任务信息时, 则状态寄存器 16向任务分 配器 20反馈其所属的子处理系统 0处于空闲状态。
在实际应用中, 状态寄存器 16向任务分配器 20反馈的信息中可包括第一状态位, 用于 表示其所属的子处理系统 0是否处于空闲状态。
进一步地, 所述状态寄存器 16向任务分配器 20反馈的信息中还可包括第二状态位, 用 于表示其所属的子处理系统 0的当前状态, 即在空闲状态下所处的具体的某一状态情况, 如 等待、 休眠、 或关闭等。 其中, 当需要分配任务时, 处于等待状态的子处理系统的优先级高 于处于休眠状态的子处理系统, 处于休眠状态的子处理系统的优先级高于处于关闭状态的子 处理系统, 从而当有多个子处理系统处于空闲状态时, 任务分配器 20可将任务优先分配给处 于等待状态的子处理系统, 避免了唤醒处于休眠、 关闭状态的子处理系统所带来的能源的消 耗以及效率的降低。
更进一步地, 当子处理系统的处理器内核 12 为多线程处理器内核时, 所述状态寄存器 16向任务分配器 20反馈的信息还可包括第三状态位, 用于表示所述处理器内核 12的空闲程 度, 比如有几条线程空闲, 而任务分配器 20在分配任务的时候会优先向空闲程度高的处理器 内核 12分配任务。易于理解的是,当由于降低能耗的需要而让部分子处理系统休眠或关闭时, 由于此时活动内核总数减少, 在任务总数不变的情况下, 平均到剩下每个内核的任务就会增 多, 因而活动内核对应的状态寄存器中显示其有较低的空闲程度, 但只要处于活动的子处理 系统的处理器内核中仍有空闲线程, 就不会唤醒处于休眠或关闭状态的子处理系统, 从而降 低了该系统的工作功耗。
在本发明实施例中, 所述缓冲器 14可以采用 FIFO (First In First Out, 先入先出缓 存队列) 形式实现, 在其它可选择的实施例中, 也可以采用其它形式的缓冲器, 且并不会影 响到本发明实施例的实施。
本发明实施例的多核处理器任务分配系统 100通过状态寄存器 16来判断子处理系统的状 态, 如果有任务需要进行分配, 而处于活动状态的子处理系统均繁忙时。任务分配器 20根据 处于休眠或关闭状态的子处理系统的状态寄存器 16 了解到这些休眠或关闭状态的子处理系 统可以处理任务, 于是任务分配器 20可先将任务存入缓冲器 14中, 并唤醒处于休眠或关闭 状态的子处理系统的内处理器内核 12, 从而提高了任务处理的效率。
在本发明实施例中, 可由缓冲器 14来唤醒其相应的处理器内核 12。
本发明实施例充分利用多核处理器结构上的特点, 利用缓冲器和状态寄存器, 在处理器 内核处于休眠或关闭的状态时, 任务分配器也可以向其分配任务, 以使得当处理器内核被唤 醒后可以及时进行处理, 提高了任务处理的效率。
请参照图 2, 本发明实施例还提供另一种多核处理器任务分配系统 200。与本发明实施例 提供的多核处理器任务分配系统 100的相同之处省略说明, 本实施例的多核处理器任务分配 系统 200与前一实施例中所述的多核处理器任务分配系统 100的区别之处在于: 每个子处理 系统还包括旁路(Bypass ) 213及路径控制器 215, 其中, 路径控制器 215与任务分配器 220 相通, 并接受任务分配器 220发送的任务信息, 路径控制器 215根据状态寄存器 216中储存 的状态信息, 选择任务信息的传输通道。 具体地, 当待接收任务的处理器内核 212在处理数 据时, 即该处理器内核 212处于忙碌状态时, 路径控制器 215选择缓冲器 214作为任务信息 发送的路径; 当处理器内核 212处于等待状态时, 路径控制器 215选择旁路 213作为任务信 息发送的路径, 该旁路 213 可以直接将接收的任务消息发送给处于等待状态的处理器内核 212, 以加快任务信息的处理速度; 当处理器内核 212 处于休眠或关闭状态时, 路径控制器 215将任务信息通过缓冲器 214发送, 该缓冲器 214接收并缓存任务消息的同时, 唤醒处于 休眠或关闭状态的处理器内核 212, 当该处理器内核 212被唤醒后, 缓冲器 214将缓存的任 务消息发送给处理器内核 212。
本发明实施例提供的系统, 通过设置状态寄存器以及传输通道, 可以根据应用场景和数 据流量灵活配置, 提高了多核处理器处理任务的效率, 在不降低系统性能的前提下实现了低 功耗; 屏蔽了处理器内核的开关状态, 从任务分配器来看, 所有的处理器内核都是可用的, 确保了在降低功耗的同时, 不降低对突发数据的处理能力。 实施例 2
本发明实施例提供了一种多核处理器的任务分配方法, 该方法包括:
首先, 任务分配器根据状态寄存器的状态判断处理器内核是否空闲;
然后, 通过传输通道向空闲的处理器内核传输消息包。
下面将结合附图对本发明实施例提供的多核处理器的任务分配方法进行说明: 本发明实 施例提供了一种多核处理器的任务分配方法, 且以任务分配器和处理器内核之间设置的传输 通道为缓冲器为例进行说明, 参见图 3, 方法包括:
301:任务分配器根据每个处理器内核对应的状态寄存器的忙闲状态查找空闲的处理器内 核, 然后把消息包通过缓冲器发送给空闲的处理器内核处理。 如果该空闲的处理器内核处于 休眠或关闭状态, 则执行 302 ; 如果该空闲的处理器内核处于等待状态, 则执行 304。
具体地, 对于多线程处理器内核, 则要根据内部线程的状态设置状态寄存器, 以 8线程 处理器内核为例, 一个处理器内核可以同时处理最多 8个任务, 以权重 0-8来表示处理器内 核忙闲状态, 若 8个线程全部为空闲, 状态寄存器的第三状态位为 8, 若有 3个被占用, 5个 空闲, 则状态寄存器的第三状态位为 5。 为了避免资源竞争, 任务分配器通常优先把任务发 给状态寄存器空闲程度高的处理器内核, 而多线程处理器内核只有内部全部线程都空闲时才 能关闭处理器内核。 任务分配器在活动内核中分配任务时, 此时, 为了在效率和功耗上取得 一个平衡点, 可以根据处理器内核的处理能力设定, 当活动处理器内核中空闲线程比率高于 关闭阈值则关掉一个处理器内核, 此内核设为非活动状态, 待内部全部线程运行完后, 自动 停止工作, 在所有活动处理器内核中仍然执行空闲程度高的处理器内核优先分配算法。
302: 处理器内核处于休眠或关闭状态, 任务分配器发给处理器内核的消息包暂存在缓冲 器中, 同时唤醒处理器内核, 并将状态寄存器设为忙碌状态。
其中, 当处理器内核处于休眠状态时, 整个系统的功耗降低且处于休眠状态的处理器内 核可以很快地被唤醒, 缓冲器的缓存压力较小。 当处理器内核处于不活动状态时, 还可以通 过关掉单个处理器内核的电源来关闭处理器内核, 这样做可以更为省电, 但唤醒时所需要的 切换时间相对较长, 需要的缓存更大, 具体采用哪种方式实现低功耗视应用场合而定。
303: 处理器内核被唤醒后, 对暂存在缓冲器中的消息包处理完毕后, 状态寄存器复位为 空闲状态, 然后结束。
其中, 当状态寄存器复位为空闲状态后, 从任务分配器来看, 该处理器内核又处于可分 配任务状态。
304: 处理器内核处于等待状态, 缓冲器接收任务分配器发来的消息包, 并将接收的消息 包直接传输给处理器内核处理, 同时将状态寄存器设为忙碌状态;
其中, 由于处理器内核处于等待状态, 可以对通过缓冲器传输的消息包直接进行处理, 不需要等待。 此时, 该处理器内核可处理已在接收的消息包, 但不接收新消息包。
305: 当处理器内核处理完消息包后, 恢复等待状态, 将状态寄存器复位为空闲状态, 然 后结束。
其中, 当状态寄存器复位为空闲状态后, 从任务分配器来看, 该处理器内核又处于可分 配任务状态。
本发明实施例中多核处理器通过状态寄存器的忙闲状态进行动态开关, 屏蔽了处理器内 核的开关状态对任务分配器在分配任务时的影响。 即使处理器内核处于关闭状态, 但从任务 分配器来看, 该处于关闭状态的处理器内核仍是可用的, 且所有的处理器内核都是可用的, 确保了在降低功耗的同时, 不降低对突发数据的处理能力。 实施例 3
本发明实施例还提供了一种多核处理器的任务分配的方法, 且以任务分配器和处理器内 核之间设置的传输通道包括旁路和缓冲器为例, 进行说明, 参见图 4, 方法包括:
401: 任务分配器根据每个处理器内核对应的状态寄存器所显示的忙闲状态,查找空闲的 处理器内核, 然后把接收到的消息包发送给空闲的处理器内核处理。
其中, 当处理器内核为单线程内核时, 设置其状态寄存器的空闲或忙碌状态的定义, 可 以根据具体的需要实现, 例如, 根据该单线程处理器内核是否正在处理数据, 从而定义该单 线程内核的忙闲状态, 如果该处理器内核正在处理任务, 或缓冲器中保存有任务时, 则为忙 碌状态; 反之, 当处理器内核并未在处理任务, 而缓冲器中亦未有任务时, 则为空闲状态。 更具体的, 所述空闲状态包括处理器内核等待处理任务、 休眠和关闭这三种情况。 当任务分 配器获取到多个内核都处于空闲状态时, 可以随机任选出一个空闲内核, 也可以根据预设的 优化选择算法, 从中选择出一个空闲内核, 本发明实施例不限制具体的选择方式和方法。
其中, 当处理器内核为多线程处理器内核时, 则要根据内部线程的状态设置状态寄存器, 以 8线程处理器内核为例, 即一个处理器内核可以同时处理最多 8个任务, 以权重 0-8来表 示处理器内核忙闲状态, 若 8个线程全部为空闲, 状态寄存器的第三状态位为 8, 若有 3个 被占用, 5个空闲, 则状态寄存器的第三状态位为 5。 为了避免资源竞争, 任务分配器通常优 先把任务发给状态寄存器空闲程度高的处理器内核, 而多线程处理器内核只有内部全部线程 都空闲时才能关闭处理器内核或使处理器内核休眠。 根据多线程处理器内核的状态将多线程 处理器内核分为活动与非活动两种状态, 任务分配器只在活动内核中分配任务, 此时为了在 效率和功耗上取得一个平衡点, 可以根据处理器内核的处理能力设定, 当处于活动的处理器 内核中的空闲线程高于关闭阈值则关掉一个处理器内核, 此内核设为非活动状态, 待内部全 部线程运行完后, 自动停止工作; 在所有工作的处理器内核中仍然在执行任务且空闲程度高 的处理器内核优先分配任务。 即当多核处理器中的处理器内核为多线程时, 则根据多线程中 的空闲线程数目, 设定空闲程度, 每个多线程处理器内核的状态寄存器根据所述空闲程度设 定状态值, 相应地, 任务分配器根据所述空闲程度, 优先选择活动内核中空闲线程数目最大 的多线程处理器内核进行分配。
其中, 针对处理器的内核状态进行如下说明:
( 1 ) 对于单线程内核而言, 默认所有内核都可由任务分配器进行任务分配,内核为降低 功耗而关闭与否对分配器是透明的。因此,这种情况下只有空闲状态 (包括等待、休眠、关机) 和忙碌状态。
( 2 )对于多线程内核而言, 其管理较为复杂, 当一个内核中的空闲线程高于关闭阈值则 关掉一个处理器内核, 此内核设为非活动状态, 待内部全部线程运行完后, 自动停止工作, 只有所有线程都空闲, 才能关闭该内核。 因此, 如果所有内核仍由任务分配器分配任务, 就 可能造成所有内核都工作但每个内核中平均工作线程较少,从降低功耗的角度看是不合理的。 应该存在一种算法能够保证工作的内核数较少而每核内平均工作的线程数较多, 同时要关掉 某个内核时也需要有机制保证其内部全部线程不再分配任务。 因此多线程内核有活动和非活 动状态的区别, 而上述 "空闲"、 "忙"等状态只在活动内核中有效, 活动内核内部关闭与否 对任务分配器也是透明的,任务分配器只在活动内核中分配。而对于非活动的内核也可以看成 一直是 "忙"状态, 实际上不参与工作, 任务分配器也不会向其分配任务。
402: 与该空闲的处理器内核相对应的路径控制器收到任务分配器发送的消息包后, 根据 该处理器内核的空闲状态选择一个通道传输消息包。 如果处理器内核处于休眠或关闭状态, 则执行 403, 如果处理器内核处于等待状态, 则执行 405。
其中, 如前文所述, 处理器内核的空闲状态, 根据空闲的时间长短可为等待状态、 休眠 或关闭状态, 当该处理器内核不处理数据时, 则由忙碌状态转为空闲状态。 具体地, 处理器 内核首先会转为等待状态, 而当该等待状态的持续时间达到设定时间值时, 该处理器内核由 等待状态切换到休眠或关闭状态, 从而减少功耗。
403: 当处理器内核处于休眠或关闭状态, 选择使用缓冲器传输消息包, 传输的消息包由 缓冲器缓存, 同时唤醒处理器内核, 状态寄存器设为忙碌状态。
其中, 处理器内核空闲时可以采用关掉时钟的方式来实现低功耗, 该方式切换唤醒速度 快; 也可以采用分别关掉单个处理器内核的电源来实现低功耗, 该方式更省电, 节省功耗, 但切换唤醒时间相对较长, 需要的缓存更大, 例如对于功耗要求较高时, 则可以采用分别关 掉单个处理器内核的电源的方式, 而对于对切换唤醒时间要求较高时, 则可以采用上述第一 种关掉时钟的方式。 其中, 具体采用哪种方式实现低功耗依据具体的应用场合而定。
404: 处理器内核被唤醒后, 对暂存在缓冲器中的消息包处理完后, 把输入通道切换到旁 路, 状态寄存器复位为空闲状态, 然后结束。
其中, 当状态寄存器复位为空闲状态后, 从任务分配器来看, 该处理器内核又处于可分 配任务状态。
405: 当处理器内核处于等待状态, 选择使用旁路传输消息包, 旁路开始接收任务分配器 发送的消息包, 状态寄存器设为忙碌状态, 当前处理器内核可处理已在接收的消息包, 但不 接收新消息包。
其中, 当处理器内核处于等待状态, 选择使用旁路传输消息包, 将消息包直接传送给等 待状态的处理器内核, 实现了处于等待状态的处理器内核对旁路传输消息包的直接处理, 此 时消息包的处理过程不需要等待, 因此, 减少传输消息包的功耗和时延。
406: 当处理器内核处理完旁路传输的消息包后, 进入等待状态, 状态寄存器复位为空闲 状态, 然后结束。
其中, 当状态寄存器复位为空闲状态后, 从任务分配器来看, 该处理器内核又处于可分 配任务状态。
本发明实施例中的多核处理器通过状态寄存器的忙闲状态进行动态开关, 任务分配器根 据状态寄存器的状态分配内核任务, 根据选择的传输通道 (缓冲器或旁路) 实现对消息包的 传输, 即使多核处理器处于关闭状态, 从任务分配器来看, 该关闭的多核处理器仍是可分配 任务的状态, 确保了在为降低功耗而关闭空闲的处理器内核的同时, 又不会降低对突发数据 的处理能力。 实施例 4
参见图 5, 本发明实施例提供了一种路径控制器, 该路径控制器, 包括:
接收模块 501, 用于接收任务分配器发送的消息包;
选择模块 502, 用于选择传输通道传输消息包。
其中, 当传输通道包括旁路和缓冲器时, 选择模块 502具体包括:
第一选择单元, 用于当空闲的处理器内核的状态为等待状态时, 选择旁路作为传输通道, 并将接收的消息包发送给旁路;
第二选择单元, 用于当空闲的处理器内核的状态为休眠或关闭状态时, 选择缓冲器作为 传输通道, 并将接收的消息包发送给缓冲器。
本发明实施例提供的路径控制器, 可以实现对传输通道的选择, 进而根据选择的传输通 道实现对消息包的传输, 从而提高了多核处理器处理任务的效率, 使多核处理器在不降低对 突发数据的处理能力及系统性能的前提下, 实现低功耗。 实施例 5
参见图 6, 本发明实施例提供了一种缓冲器, 该缓冲器, 包括:
接收模块 601, 用于接收路径控制器传输的消息包; 缓存模块 602, 用于将接收模块 601接收到的消息包缓存;
唤醒模块 603, 用于唤醒休眠或关闭的处理器内核;
传输模块 604, 用于当唤醒模块 603唤醒处理器内核后, 将缓存模块 602缓存的消息包 传输给被唤醒的处理器内核。
进一步地, 当处理器内核处于空闲状态, 则传输模块 604还用于将接收模块 601接收的 消息包直接发送给处于空闲状态的处理器内核。
本发明实施例提供的缓冲器, 当处理器内核为休眠或关闭状态时, 对接收的消息包缓存 的同时, 并唤醒该处理器内核, 当唤醒处理器内核后, 将缓存的消息包发送, 从而提高了多 核处理器处理任务的效率, 使多核处理器在不降低对突发数据的处理能力及系统性能的前提 下, 实现低功耗。
通过以上的实施方式的描述, 本领域的技术人员可以清楚地了解到本发明可以通过硬件 实现, 也可以借助软件加必要的通用硬件平台的方式来实现。 基于这样的理解, 本发明的技 术方案可以以软件产品的形式体现出来, 该软件产品可以存储在一个非易失性存储介质 (可 以是 CD-ROM, U盘, 移动硬盘等) 中, 包括若干指令用以使得一台计算机设备 (可以是个人 计算机, 服务器, 或者网络设备等) 执行本发明各个实施例所述的方法。
以上所述仅为本发明的较佳实施例, 并不用以限制本发明, 凡在本发明的精神和原则之 内, 所作的任何修改、 等同替换、 改进等, 均应包含在本发明的保护范围之内。

Claims

权 利 要 求 书
1、 一种多核处理器的任务分配方法, 其特征在于, 所述方法包括:
任务分配器根据状态寄存器的状态判断处理器内核是否空闲;
所述任务分配器通过传输通道向空闲的处理器内核传输消息包。
2、根据权利要求 1所述的多核处理器的任务分配方法, 其特征在于, 所述任务分配器根 据状态寄存器的状态判断处理器内核是否空闲, 包括:
当所述多核处理器中包括多个多线程处理器内核时, 所述多个多线程处理器内核相应的 状态寄存器根据所述多线程处理器内核空闲线程的数目向所述任务分配器发送一状态信息; 所述任务分配器根据所述多个多线程处理器内核所相应的状态寄存器发送的状态信息, 判断所述多个多线程处理器内核的空闲程度;
所述任务分配器通过传输通道向空闲的处理器内核传输消息包, 包括:
所述任务分配器通过传输通道向空闲线程高的多线程处理器内核发送消息包。
3、 根据权利要求 1所述的多核处理器的任务分配方法, 其特征在于, 所述空闲状态, 包 括等待状态、 休眠状态或关闭状态, 所述通过传输通道向空闲的处理器内核传输消息包, 包 括:
当所述空闲的处理器内核的状态为等待时, 路径控制器选择所述传输通道中的旁路作为 所述消息包发送的通道;
当所述空闲的处理器内核的状态为休眠或关闭时, 所述路径控制器选择所述传输通道中 的缓冲器作为所述消息包发送的通道。
4、根据权利要求 1所述的实现多核处理器的任务分配方法,其特征在于,所述空闲状态, 包括等待状态、 休眠状态或关闭状态, 所述方法还包括:
所述传输通道中的缓冲器将接收的所述路径控制器发送的消息包缓存;
当所述处理器内核为休眠或关闭状态时, 唤醒所述休眠或关闭状态的处理器内核; 当所述休眠或关闭状态的处理器内核被唤醒后, 所述缓冲器将缓存的消息包发送给被唤 醒后的处理器内核。
5、 一种多核处理器的任务分配方法, 用于多核处理器中, 所述多核处理器包括多个子处 理系统, 其特征在于, 所述方法包括:
通过状态寄存器读取所述多个子处理系统的状态信息, 所述状态信息显示所述多个子处 理系统的当前状态, 所述当前状态包括等待、 休眠或关闭;
向处于休眠或关闭状态的子处理系统的缓冲器发送消息包;
唤醒所述处于休眠或关闭状态的子处理系统;
所述缓冲器将所述消息包发送给所述子处理系统的处理器内核。
6、 一种多核处理器的任务分配系统, 其特征在于, 所述系统, 包括: 任务分配器和子处 理系统, 所述子处理系统包括状态寄存器、 处理器内核及传输通道, 其中,
所述状态寄存器, 用于向所述任务分配器发送所述子处理系统的状态信息, 所述状态信 息包括所述子处理系统的处理器内核是否处于空闲状态, 所述空闲状态包括等待、 休眠或关 闭;
所述任务分配器, 用于向所述子处理系统发送消息包;
所述传输通道, 用于将所述任务分配器发送的所述消息包传送给所述处理器内核, 所述 传输通道的传输路径中至少包括一个缓冲器;
其中, 当所述处理器内核处于休眠或关闭状态时, 所述任务分配器将所述消息包发送给 所述缓冲器缓存, 并唤醒所述处理器内核, 当所述处理器内核被唤醒后, 所述缓冲器将所述 消息包发送给所述处理器内核。
7、根据权利要求 6所述的多核处理器的任务分配系统, 其特征在于, 当所述传输通道还 包括旁路, 所述子处理系统还包括: 路径控制器;
所述路径控制器, 用于接收所述任务分配器发送的消息包; 还用于根据空闲的处理器内 核的状态, 选择所述缓冲器或旁路传输消息包; 其中,
当所述空闲的处理器内核的状态为等待状态时, 所述路径控制器选择所述旁路作为传输 通道, 并将接收的消息包发送给所述旁路;
当所述空闲的处理器内核的状态为休眠或关闭状态时, 所述路径控制器选择所述缓冲器 作为传输通道, 并将接收的消息包发送给所述缓冲器。
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