WO2010057975A2 - Procédé d'estimation d'un décalage de fréquence dans un récepteur de communication - Google Patents

Procédé d'estimation d'un décalage de fréquence dans un récepteur de communication Download PDF

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Publication number
WO2010057975A2
WO2010057975A2 PCT/EP2009/065552 EP2009065552W WO2010057975A2 WO 2010057975 A2 WO2010057975 A2 WO 2010057975A2 EP 2009065552 W EP2009065552 W EP 2009065552W WO 2010057975 A2 WO2010057975 A2 WO 2010057975A2
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WO
WIPO (PCT)
Prior art keywords
frequency
spectrum
frequency offset
sequence
output
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Application number
PCT/EP2009/065552
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English (en)
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WO2010057975A3 (fr
Inventor
Dirk Schmitt
Marten Kabutz
Alkis Ikonomu
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Thomson Licensing
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Publication of WO2010057975A2 publication Critical patent/WO2010057975A2/fr
Publication of WO2010057975A3 publication Critical patent/WO2010057975A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2657—Carrier synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2668—Details of algorithms
    • H04L27/2669—Details of algorithms characterised by the domain of operation
    • H04L27/2672—Frequency domain
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2668—Details of algorithms
    • H04L27/2673—Details of algorithms characterised by synchronisation parameters
    • H04L27/2676—Blind, i.e. without using known symbols

Definitions

  • Digital Communication like DVB-T, DVB-S, DVB-S2, DVB-C, GSM, WLAN, DSL
  • ⁇ "Data-aided" frequency offset compensation is based on the assumption that part of the transmission content is predefined and thus can be used as a pilot sequence.
  • Digital communication receiver circuits suffer from a frequency offset because of the lack of precision of a local oscillator frequency in the analogue tuner, especially in the tuner synthesizer or in the analogue receiving parts in the analogue domain, like the LNB oscillator. Due to down conversions of the received signal by both an LNB and the tuner, the received signal has some unknown frequency offset. This can be as much at +/- 5 MHz during a cold startup primarily due to the exposure of the outdoor LNB to temperature extremes. In the block diagram of a digital receiver shown in Figure 1, sources of frequency offset are indicated: While the LNB introduces an unknown frequency offset of ⁇ f LNB , the tuner causes an unknown frequency
  • the third solution is the parallel search or open loop search, which is described in C. H. Wu, Frequency Synchronization, Lecture Note CCU EE, 2005.
  • the described method in the invention is related to the third field of solutions. So the invention algorithm is an open loop search.
  • the invention proposes two estimation methods based on the following steps: ⁇ Transforming complex (I, Q) samples from the tuner into a frequency domain.
  • a third estimation method is based on the following steps:
  • incoming (I, Q) samples are time domain filtered in parallel by one complex-valued filter and one delay element, and their output signals are multiplied. This results in a "band edge correlator", because it amounts to a correlation operation, and has a sharp selection effect.
  • the spectral maximum is searched.
  • Steps 1 and 2 are repeated for increasing values of center frequency shift, the global maximum is representative for the frequency offset that needs to be compensated.
  • the invention solves the problem of large frequency offset compensation using a software hardware interaction.
  • the frequency offset estimation does not need any pilot tone, as needed in the prior art. Also no timing information for the data stream is needed.
  • estimation algorithm is an open loop search (method 1 and method 2), where the following steps will be performed:
  • a digital filter can be inserted before the spectrum analyzer (method 2) .
  • a digital decimator can be inserted before the spectrum analyzer to suppress the noise and the adjacent energy before the spectrum analyzer.
  • a bandedge correlation (method 3) will be inserted before the spectrum analyzer, which gives a peak in the spectrum if the band edges are centered around the zero frequency. This method has the disadvantage that one has to know at least approximately the location of the band edges, but it yields a high noise rejectance which is helpful in very low SNR regions.
  • Figure 1 shows a block diagram of a digital receiver indicating sources of frequency offset.
  • FIG. 2 shows a block diagram of the signal processing modules used for frequency offset estimation and compensation according to the invention.
  • Figure 3 shows the state diagram of the processing steps of the first method.
  • Figure 4 shows spectrum amplitudes over frequency to illustrate how the absolute slope is calculated between two separated FFT output values.
  • Figure 5 shows a measured spectral output Y(k) after the detector .
  • Figure 6 illustrates the hardware reuse process proposed in the invention.
  • Figure 7 shows the interaction between a power spectrum estimation module and a DSP or microprocessor.
  • Figure 8 illustrates evaluation algorithms.
  • Figure 8 (a) illustrates the Differential sum algorithm.
  • Figure 8 (b) illustrates a reduced differential sum algorithm.
  • Figure 9 illustrates an evaluation algorithm
  • Figure 10 shows the state diagram of the processing steps in the third method.
  • Figure 11 symbolically illustrates the two tasks for Tl and T2.
  • the top picture of Figure 11 shows how T2 shifts the filters Fl and F2 to the edges of the channel spectrum, while the bottom picture of Figure 11 shows how the mixer Tl has to shift the channel spectrum to the bandegde filter passband.
  • the simple line spectrum is before mixer Tl and the bold dotted line spectrum is the output spectrum of Tl.
  • FIG. 2 shows a block diagram of the signal processing modules used for frequency offset estimation and compensation according to the invention.
  • An input signal 201 is multiplied, in a multiplier 202, with a local carrier frequency from a numerically controlled oscillator or NCO 204.
  • the product is forwarded, in parallel, to a bandedge correlator 207, to an anti-alias filter 208, and to a multiplexer or switch Sl 210.
  • the signal processing modules also comprise a frequency estimator 209, whose input can be selected by switch Sl 210 to be either directly the output 213 of the multiplier 202, the output 212 of the anti-alias filter 208, or the output 211 of the bandedge correlator 207.
  • the output of the frequency estimator 209 is forwarded to a microprocessor 206, which in turn controls the frequency of the NCO 204.
  • the invention proposes for frequency offset estimation and compensation to use several methods based on the open loop search principle. Three methods will be presented here, which are suited to different problems in the open loop search. The three different methods can be selected by switching the multiplexer Sl 210 in Figure 2.
  • the first method of estimating the frequency offset is given when the switch Sl 210 is connected to the output of the multiplier 202.
  • FIG. 3 shows the processing steps of the first method of frequency offset estimation.
  • the same processing steps also are comprised in the second method of frequency offset estimation.
  • These processing steps can be implemented in software or in hardware.
  • the first processing step or step 1 301 estimates the average spectrum and is divided into two stages, namely stagel 302 and stage2 303.
  • the first stage 302 consists of a FFT process which estimates the spectrum of the incoming signal for a short time.
  • the magnitudes are averaged over several windows using a Bartlett Welch method, to smooth the estimated spectrum.
  • the averaging over several windows is controlled by a loopback control step 304, which branches either back to step 302 or forward to step 307.
  • magnitudes mag of FFT frequency bins x are estimated using the following formula:
  • mag max(real(x),imag(x)) + 0.5 *mm(real(x),imag(x)) ,
  • real (x) is the real output value of an FFT bin and imag(x) is the imaginary output value of the FFT bin.
  • the smoothing window length can be adjusted by a software register. The method of smoothing the spectra via average process saves hardware impact and enables to trade off spectrum estimation time against the exactness of the spectral resolution in magnitude. The results of the estimated spectrum is then stored in a memory for further processing.
  • the frequency offset is estimated by scanning the spectrum using a secant method, where the absolute slope, i.e. the amplitude difference, between two indexed FFT output values is calculated.
  • Figure 4 shows spectrum amplitudes over frequency to illustrate the input output behavior of the secant method used for scanning the spectrum.
  • the top part of Figure 4 shows a simplified channel spectrum 401 and several double arrows symbolizing pairs of values from the spectrum, spaced apart in frequency by the secant length, between which the absolute slope will be evaluated.
  • the bottom part of Figure 4 shows, over frequency f, the absolute slope 402 as measured when the pairs of values scan the entire spectrum.
  • the secant length must be chosen according to the channel bandwidth, in order to get a single pronounced minimum. So the baud rate has to be known a priori. The secant length must then be chosen as
  • the minimum absolute slope occurs on the top of the scanned spectrum.
  • step 3 308 the output of step 2 307, corresponding to the absolute slope 402, is scanned to locate the carrier frequency which is indexed by the least bin value.
  • step 4 309 the minimum absolute slope and its index in the spectrum are then written into a software register. To control the estimation range, a start bin and an end bin in the estimated spectrum can be given by software registers. After the minimum index is found, the frequency offset can be easily compensated by adjusting 205 an NCO 204 of a digital down conversion mixer.
  • the second method differs from the first method in that a digital filter and if needed a decimator are used in front of the estimation process to prevent false locking onto adjacent channels.
  • This method is active when the switch Sl 210 is in its middle position, so that the output of the anti-alias filter 208 is selected as input for the frequency estimator 209.
  • the second method is suited if more than one channel is populated in the tuner output spectrum.
  • the second method has the same state diagram ( Figure 3) as method 1.
  • the second method only includes a prefilter in front of the frequency estimator as shown in Figure 2.
  • the third method is suited for low SNR modes where the noise floor is just slightly below the signal spectrum.
  • the third method employs a modified dual filter method for channel estimation.
  • Figure 6 illustrates the hardware reuse process proposed in the invention.
  • the hardware has a coarse tracking loop Tl 601, and a fine tracking loop T2 603.
  • the output of the fine tracking loop 603 corresponding to the upper channel bandedge X (omega+omegaO) is forwarded to an anti-alias filter 604, whereas the output of the fine tracking loop 603 corresponding to the lower channel bandedge X (omega-omegaO) is forwarded to a delay element 605.
  • the output 611 of the anti-alias filter 604 and the conjugate complex of the output 610 of the delay element 605 are multiplied in multiplier 606, to yield correlated IQ values 609.
  • x(t) denotes the time domain value
  • X(-k) is the related value in the spectrum.
  • Figure 10 shows the state diagram of the processing steps in the third method.
  • a first step 1001 the bandwidth of the bandedge correlator is setup using the block T2 of Figure 6. This step fulfills the above mentioned requirement that both edges are centered around the two edge filter if no frequency offset is included.
  • the frequency offset is set up using the block Tl. With this step the whole algorithm is able to shift the spectrum to a location where both bandedges are centered on the filter's passband.
  • Figure 11 illustrates the two tasks for Tl and T2.
  • T2 is used to adjust the bandwidth of the current channel
  • Tl is used to remove the carrier offset of the channel by shifting the total spectrum towards negative or positive frequencies.
  • the top picture of Figure 11 shows how T2 shifts the filters Fl and F2 to the edges of the channel spectrum
  • the bottom picture of Figure 11 shows how the mixer Tl has to shift the channel spectrum to the bandedge filter passband.
  • the single continuous line denotes the spectrum before mixer Tl and the bold dotted line denotes the spectrum at the output of Tl.
  • the bandedge correlator output 609 is then fed to the spectrum analyzer 607.
  • the spectrum analyzer consists of two stages 1004, 1005, and yields the estimated spectrum.
  • the last step or step 4 1007 compares the current maximum value in the spectrum with a previously stored value. If the maximum value is greater than the stored value, step 4 overwrites the stored value with the maximum value of the spectrum, and keeps the number of moving steps of block Tl Before the state machine enters step 1, the stored value is set to 0.
  • the state machine goes back to step 2 where the spectrum is shifted using the block Tl by a small frequency offset. The procedure is repeated until the frequency shift of Tl reaches a certain value controlled by microcontroller registers.
  • the frequency of the maximum magnitude indicates the exact location of the frequency offset, which can be fed to a digital derotator as described in step 4 of method 1.
  • a digital demodulator uses an anti-alias filter AA 604 to suppress adjacent channels before the decimation to the symbol rate is done by a digital decimator. Also a coarse and fine frequency tracking loop is used, where the coarse tracking loop Tl removes the coarse frequency offset before the anti- alias filter, and the fine tracking loop T2 tracks to the remaining frequency and phase offset after the decimation process. To save hardware, these modules will be reused in the frequency offset estimation step.
  • the coarse tracking loop is used by the frequency estimation process to shift the scanned frequency spectrum during the process steps; and the second tracking loop T2 is used to shift the center frequency of the upper and lower bandedge to the zero frequency by mixing with the positive and negative half symbol rate plus half bandedge bandwidth.
  • the shifted upper bandedge is fed to the anti-alias filter AA while the shifted lower bandedge is fed to the delay line DEL which compensates the group delay of the AA.
  • the output of the delay line DEL and the anti-alias filter AA is then correlated with the above described method.
  • the coarse tracking loop has to be loaded with the related frequency offset during that peak.
  • Figure 6 shows the schematic of this hardware reuse process. Keep in mind that only the delay line and the complex multiplier for the detector have to be added to the current hardware.
  • the principle of the invention is applicable to any frequency offset compensation problems in any digital communication IC.
  • FIG. 7 shows the interaction between a power spectrum estimation module 701 and a DSP or microprocessor 704.
  • the DSP or microcontroller 704 can assist to get more flexibility in searching the frequency offset value.
  • the microcontroller or DSP 704 requests 702 a new power density spectrum from the power spectrum estimation unit 701, and the power spectrum estimation unit 701 sends a callback 705 to the microcontroller or DSP 704 using an interrupt line or a mailbox signal .
  • Figure 8 (a) illustrates the Differential sum algorithm.
  • Figure 8 (b) illustrates a reduced differential sum algorithm.
  • a reduced differential sum algorithm can be used, which uses the triangular inequality to simplify the above formula to
  • diff _ sum _ red (I) ⁇ ⁇ x(l - HB - BE + n) - x(l + HB + BE - n) ⁇
  • Wl(I) Wl(I-1)-x((l-1)+HB-BE)+x(l-HB)
  • Wl(I) Wl(I-I)-X(I-I-BE)+x(l)
  • the diff_sum_red and the final estimated frequency offset is then calculated in the same manner as it is given in (2) and (1)
  • This sequence of spectrum estimation and frequency offset search can be repeated to get a better reliability of the frequency estimation .

Abstract

L'invention concerne un procédé d'estimation d'un décalage de fréquence dans un récepteur de radiocommunication, consistant à transformer une séquence d'échantillons à valeur complexe provenant d'un premier étage du récepteur en une séquence de segments de fréquences en tant que représentation dans le domaine fréquentiel, à balayer les segments de fréquences pour trouver les fréquences pour lesquelles la représentation dans le domaine fréquentiel est plate, puis à modifier un étage de conversion descendante du récepteur en fonction des fréquences trouvées.
PCT/EP2009/065552 2008-11-21 2009-11-20 Procédé d'estimation d'un décalage de fréquence dans un récepteur de communication WO2010057975A2 (fr)

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EP08169689 2008-11-21
EP08169689.0 2008-11-21

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WO2010057975A2 true WO2010057975A2 (fr) 2010-05-27
WO2010057975A3 WO2010057975A3 (fr) 2010-07-22

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101888253A (zh) * 2010-05-28 2010-11-17 深圳国微技术有限公司 通信信道基带频率的偏移纠正方法及系统
US20110129045A1 (en) * 2009-11-27 2011-06-02 Sunplus Technology Co., Ltd. Method and device for aquiring a channel with frequency offset less than half symbol rate
EP2720427A1 (fr) * 2012-10-12 2014-04-16 ST-Ericsson SA Estimation de CFO basée sur des valeurs relatives de segments de fréquences correspondants à des sous-porteuses utilisées de symboles de préambule reçus pour systèmes OFDM
US9388260B2 (en) 2011-12-22 2016-07-12 Dow Global Technologies Llc Ethylene-based polymers with improved melt strength and processes for the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060129410A1 (en) * 2002-07-05 2006-06-15 Sam Reisenfeld Frequency estimation
US7428270B1 (en) * 1999-02-15 2008-09-23 Christian Dubuc Method and system for detecting and classifying the modulation of unknown analog and digital telecommunications signals

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7428270B1 (en) * 1999-02-15 2008-09-23 Christian Dubuc Method and system for detecting and classifying the modulation of unknown analog and digital telecommunications signals
US20060129410A1 (en) * 2002-07-05 2006-06-15 Sam Reisenfeld Frequency estimation

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110129045A1 (en) * 2009-11-27 2011-06-02 Sunplus Technology Co., Ltd. Method and device for aquiring a channel with frequency offset less than half symbol rate
US8406345B2 (en) * 2009-11-27 2013-03-26 Sunplus Technology Co., Ltd. Method and device for aquiring a channel with frequency offset less than half symbol rate
CN101888253A (zh) * 2010-05-28 2010-11-17 深圳国微技术有限公司 通信信道基带频率的偏移纠正方法及系统
US9388260B2 (en) 2011-12-22 2016-07-12 Dow Global Technologies Llc Ethylene-based polymers with improved melt strength and processes for the same
EP2720427A1 (fr) * 2012-10-12 2014-04-16 ST-Ericsson SA Estimation de CFO basée sur des valeurs relatives de segments de fréquences correspondants à des sous-porteuses utilisées de symboles de préambule reçus pour systèmes OFDM
WO2014057055A1 (fr) * 2012-10-12 2014-04-17 St-Ericsson Sa Estimation de décalage de fréquence porteuse (cfo) sur la base de valeurs relatives d'intervalles de fréquence correspondant à des sous-porteuses utilisées de symboles de préambule reçus pour systèmes de multiplexage par répartition orthogonale de la fréquence (ofdm)
US9306789B2 (en) 2012-10-12 2016-04-05 St-Ericsson Sa Estimation of CFO based on relative values of frequency bins corresponding to used subcarriers of received preamble symbols for OFDM systems

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