WO2010051776A1

WO2010051776A1 - Setting flow for delay time of a blasting device and controlling flow for an electronic detonator in an electronic detonator blasting system

Info

Publication number: WO2010051776A1
Application number: PCT/CN2009/074873
Authority: WO
Inventors: 颜景龙; 张宪玉; 刘星; 李风国; 赖华平
Original assignee: 北京铱钵隆芯科技有限责任公司
Priority date: 2008-11-10
Filing date: 2009-11-09
Publication date: 2010-05-14
Also published as: ZA201104185B; AU2009311076A1; AU2009311076B2; EA201100722A1

Abstract

A setting flow for delay time of a blasting device in an electronic detonator blasting system performs steps as follows: Step A1, executing a clock calibrating procedure (2) of the blasting device; Step A2, executing a delay time writing procedure (3) of the blasting device; Step A3, outputting an error information list to a human-computer interaction module which displays the error information list (4); Step A4, ending the setting flow for delay time of the blasting device (5). The system is comprised of the blasting device and one or more electronic detonators. One or more electronic detonators is connected to a signal bus derived from the blasting device in parallel. The blasting device includes a control module, a human-computer interaction module, a power supply management module, a signal modulating and transmitting module, a signal modulating and receiving module and a power suppy. The control module includes a CPU and a timer. An alternate design of the setting flow for delay time of the blasting device is executing a clock calibrating procedure during a delay time writing procedure. A controlling flow for an electronic detonators in an electronic detonator blasting system performs a clock calibrating procedure and a delay time writing procedure respectively according to an outer command.

Description

Instruction manual

Detonation device delay time setting process in electronic detonator detonation system

And electronic detonator control process

Technical field

[1] The present invention relates to the field of detonation control technology for pyrotechnic articles, and particularly relates to the design of a deferred setting method for an electronic detonator detonation system, including a deferred device deferral setting process, an electronic detonator control process, and both The design of the mutual cooperation.

Background technique

[2] In the 1980s, developed countries such as Japan, Australia, and Europe began to study electronic detonator technology. With the rapid development of electronic technology, microelectronics technology and information technology, electronic detonator technology has made great progress. In the late 1990s, electronic detonators began to be put into application testing and marketing.

[3] As the core component of the electronic detonator, the performance of the electronic detonator control chip directly affects the performance of the electronic detonator. The patented ZL200820111269.7 or ZL200820111270.X, and the electronic detonator control chip given in 1JZL03156912.9, realize the two-wire non-polar connection of the electronic detonator, the two-way communication between the electronic detonator and the detonating device, and the built-in detonator identity code. Basic functions such as controllable detonation process and electronic delay are a qualitative leap compared with traditional detonators.

[4] Patents ZL200420034635.5, ZL98210324.7, ZL200420034635.5 and ZL200620094002

The electronic detonator implementation given in .2 uses a crystal oscillator placed outside the electronic delay module as a reference cuckoo. The main drawback of such a technical solution is that, in the actual blasting application of the electronic detonator, the deferred time of each detonator is not the same, so the first detonator will have an explosion impact on the unexploded detonator. Since the crystal relies on the stable frequency of its mechanical resonance output to generate the cuckoo clock, when the reference cuckoo circuit is taken as the crystal oscillator, the blasting shock wave will affect the resonant frequency of the crystal, thereby affecting the delay precision of the electronic detonator. Seriously, the crystal may even be damaged by the explosion shock wave, causing the chopper circuit to stop working, causing the detonator to detonate. In addition, crystals used in crystal oscillators cannot be integrated into the electronic detonator control chip, which increases the size and cost of the electronic detonator.

[5] Due to the above-mentioned defects in the use of crystal oscillators, in applications where shock waves are present, it is necessary to use a cuckoo clock circuit with impact resistance. In addition, in order to make the volume of the electronic detonator as small as possible, it is necessary to use a chopper circuit with integration. [6] Therefore, the RC oscillator can be used as a cuckoo clock circuit to provide a reference clock for the operation of the detonator chip. On the one hand, the RC oscillator is used to improve the integration of the electronic detonator control component; on the other hand, the impact resistance of the RC oscillator is utilized to improve the adaptability of the electronic detonator to the impact environment as a whole.

[7] However, factors such as temperature drift, drift, and parameter variation of the RC oscillator are likely to cause problems such as frequency drift and frequency deviation, thus affecting the delay accuracy of the electronic detonator detonation system.

Summary of the invention

[8] The present invention is further designed on the basis of the above prior art, and aims to provide a chip control flow and a detonating device control flow that can complete the calibration of the cuckoo clock and the setting of the deferred time. The two cooperate with each other, thus avoiding the influence of the frequency drift and frequency deviation of the RC oscillator on the delay accuracy, and realizing an electronic detonator blasting network with better impact resistance and sufficient delay between turns. The electronic detonator detonating system of the present invention is comprised of a detonating device and one or more electronic detonators. The detonating device comprises a control module, a human-computer interaction module, a power management module, a signal modulation transmitting module, a signal demodulation receiving module, and a power supply, and the control module further comprises a central processing unit and a fixed device. The electronic detonator includes an electronic detonator control chip, the chip includes a non-volatile memory, a logic control circuit, and a cuckoo clock circuit, and the logic control circuit further includes a programmable delay module, an input/output interface, and a serial The communication interface, the prescaler, the counter, and the central processing unit 2, the above-mentioned cuckoo clock circuit is taken as an RC oscillator.

[10] As an aspect of the technical solution of the present invention, there are two technical solutions for the detonating device to delay the setting process.

Among them, the first technical solution can be carried out according to the following steps:

[11] Step Al, perform the calibration process of the detonating device 吋 clock;

[12] Step A2, performing the detonation device to write the deferred process;

[13] Step A3, outputting a list of error information to the human-computer interaction module, which is displayed by the human-computer interaction module;

[14] Step A4, End the deferred device deferred setting process.

[15] The first technical solution of the above-mentioned detonating device delaying the setting process of the detonating device performs the calibration process of the detonating device chopping clock before performing the detonating device writing deferral process, and calibrates the chopping clock frequency of the electronic detonator, thereby ensuring The delay between each electronic detonator in the blasting network. Step A3 sends the deferred setting error information list to the human-computer interaction module display, so that the detonating device operator can be based on the demolition network. The delay setting of the road and the importance of the blasthole of the detonator are determined by re-executing the deferred device deferred setting process to ensure that all electronic detonators in the blasting network are deferred, or in the blasting network. The electronic detonator that has been deferred has been completed for the next step. This design increases the flexibility of blasting construction control.

[16] In the above-mentioned detonating device deferred setting process, the detonating device chopping clock calibration process of step A1 is performed according to the following steps:

[17] Step B1, initializing the calibration process of the detonating device, that is, storing the total number of electronic detonators of the variable blasting network N, the number of erroneous electronic detonators, and the initial number of cycles into the buffer of the control module for use. . And, obtaining the value as the value of the N;

[18] Step B2, the control module determines whether the value of the number of cycles \\^ and the value of the number of electronic calibration detonators of the 校准 calibration error is 0: if the value or the value is 0, the blast of the detonating device is ended. Calibration process; otherwise continue to step B3;

[19] Step B3, performing the calibration process of the detonating device 吋 clock;

[20] Step B4, the value of the number of loops is decremented by 1, as the value of the new ^, ie \¥ ₁ =\¥ ₁ -1; and then returns to step B2.

[21] In the deferred device deferred setting process, the detonating device in step A2 writes the deferred process according to the following steps:

[22] Step El, initialize the deferred device write deferral process, that is, deposit the initial value of the number of electronic detonators of the variable blasting network N, the number of electronic detonators of the deferred period, the number of electronic detonators E ₂ and the number of cycles \¥ ₂ The control module's cache is in use. And obtaining the value as the value of the N;

[23] Step E2, the control module determines whether the value of the number of cycles \¥ _{2 and} the value of the number of electronic detonators E ₂ in the write delay period are 0: if the value of the W ₂ or the value of the E ₂ is 0, Then perform step E5; otherwise, perform step E3;

[24] Step E3, performing the detonation device to write the deferred process;

[25] Step E4, the value of the number of cycles W ₂ is decremented by 1, as the value of the new \¥ ₂ , ie \¥ ₂ =\¥ ₂ -1; then return to step E2;

[26] Step E5, End the detonation device to write the deferred process.

[27] In the above-mentioned detonating device, the chopping clock calibration process and the detonating device writing deferral process, respectively, a cycle number variable w nw _{2 is} designed, correspondingly controlling the detonating device cuckoo clock calibration process and the detonating device writing deferred process The number of times of operation, the execution of a detonating device deferred setting process, that is, the automatic execution of multiple clock calibration processes and the writing of the deferred process, simplifying the operation steps, thereby reducing the cumbersome multiple human operations. The resulting misoperation improves the reliability of the equipment operation. This is because, after each execution of the detonating device delays the setting process, an error message list is output to prompt the selection of the next operation, and the calibration of the cuckoo clock due to a transient fault in the detonation system or Write the possibility of delaying the diurnal error. Therefore, the detonating device is designed to automatically execute the cycle number of times of the clock calibration process and the number of cycles \¥ ₂ times to write the deferred inter-turn process, which simplifies the operator's action on the device. , thereby improving the reliability of the operation of the detonating device. When the detonating device completes the preset cycle number \\^ times of the clock calibration process or the electronic detonator that does not have the chopping calibration error in the system, the detonating device 吋 clock calibration process is ended; when the detonating device completes the preset cycle number\¥ ₂ The write-deferred inter-day process or the electronic detonator that writes the deferred inter-turn error has not existed in the system, and the detonation device writes the deferred process.

[28] In the above-mentioned detonating device chopping clock calibration process, the first step of the detonating device chopping clock calibration process of step B3 can be performed as follows:

[29] Step Cl, sending a calibration command to the electronic detonators in the blasting network;

[30] Step C2, the control module waits to reach the preset delay T _Q : if it arrives, proceed to step C3; if it does not arrive, continue to wait for arrival;

[31] Step C3, the number of electronic detonators to be calibrated L is the value of the number of electronic detonators of the 吋 calibration error.

which is ;

[32] Step C4, reading an identity code of an electronic detonator in the blasting network stored in the detonating device;

[33] Step C5, reading state information of the electronic detonator stored in the detonating device;

[34] Step C6, determining whether the electronic detonator is in a calibrated state according to the status information of the detonator: if it is the calibrated state, proceed to step C13; if it is not calibrated, proceed to step C7;

[35] Step C7, sending a status readback instruction to the electronic detonator;

[36] Step C8, the control module performs a signal receiving process: if the information returned by the electronic detonator is received, proceed to step C9; if not, proceed to step C12;

[37] Step C9, the control module saves the information returned by the electronic detonator, and determines whether the calibration signal of the electronic detonator is in a calibrated state: if it is in the calibrated state, step C10 is performed; if it is not calibrated

, step C12 is performed; [38] Step C10, setting a calibration flag for the calibration of the electronic detonator inside the detonating device;

[39] Step C11, the value of the electronic calibration detonator of the calibration clock is decremented by 1, as a new value, ie = -1; then step C13;

[40] Step C12, placing an error calibration flag on the electronic detonator inside the detonating device; then proceeding to step C13;

[41] Step C13, the value of the number L of electronic detonators to be calibrated is decreased by 1, as the value of the new L, that is, L=L-1;

[42] Step C14, determining whether the value of the number of electronic detonators to be calibrated is 0: If it is 0, proceed to step C15.

If not 0, return to step C4;

[43] Step C15, the calibration process of the detonating device is completed.

[44] In the first scheme of the above-mentioned detonating device 吋 clock calibration process, the 吋 clock calibration command sent to all the electronic detonators in the blasting network by step C1 is a global command. The command is composed of a preset number of m synchronous learning heads, a clock calibration command word and a lower calibration waveform, wherein the lower calibration waveform is preset by the preset number of downward calibration pulses by 3⁄4 preset periods. Pulse composition. The detonating device transmits the synchronous learning head and the lower calibration waveform by using its own stable and accurate chirp source, and the counter inside the chip performs segmentation counting on the above-mentioned lower calibration waveform, and then calculates the chirp clock frequency of the chip itself.

[45] In particular, the above-mentioned lower calibration waveform is sent by the control module to perform the following detonator calibration waveform transmission process:

[46] Step D1, the value of the number of the next calibration pulse to be sent is set to a value of 3⁄4 of the preset calibration pulse number, that is, n=n _B ;

[47] Step D2, writing a low-level preset value v _B of the lower calibration pulse to the fixed buffer _;

[48] Step D3, sending a control signal to the signal modulation transmitting module to output a falling edge signal;

[49] Step D4, sending a control signal to the fixed device to start the calibration device;

[50] Step D5, the central processor monitors whether the length of the low-level signal output by the transmitting module reaches the low-level preset value v _{B :} if it arrives, proceeds to step D6; if not, continues to monitor Waiting to arrive;

[51] Step D6, sending a control signal to the fixed device to stop the calibration device;

[52] Step D7, writing a high-level preset value of the lower calibration pulse to the fixed buffer _3⁄4;

[53] Step D8, sending a control signal to the signal modulation transmitting module to output a rising edge signal; [54] Step D9, sending a control signal to the fixed device to start the calibration device;

[55] Step D10, the central processor monitors whether the length of the high-level signal output by the transmitting module reaches the high-level width preset value _3⁄4: if it arrives, proceeds to step D11; if not, continues to monitor Waiting to arrive;

[56] Step D11, sending a control signal to the fixed device to stop the calibration device;

[57] Step D12, the value of the number n of the lower calibration pulse to be transmitted is decreased by 1, as the value of the new n, that is, n=n-l;

[58] Step D13, determining whether the value of n is 0: If it is 0, proceed to step D14; if not, return to step D2;

[59] Step D14, End the sending process of the calibration waveform of the detonating device.

[60] In the above-mentioned detonating device calibration waveform transmission flow, the value of the high-level width preset value 3⁄4 of the lower calibration waveform is larger than the value of the low-level width preset value v _B of the lower calibration pulse, and the value of 3⁄4 The sum of the values of v and _B is equal to T _B . The advantages are: When the detonating device sends a high-level calibration pulse 向 to the electronic detonator, it is in a state of providing a forward voltage to the detonator; and when a low-level calibration pulse is transmitted, the power supply to the detonator is stopped or a negative voltage is supplied to the detonator. status. Therefore, by increasing the width of the high level of the calibration pulse, the time interval for transmitting the high level signal can be prolonged, thereby prolonging the power supply of the detonating device to the detonator, and reducing the power consumption of the internal energy storage device of the electronic detonator. It is beneficial to improve the operational reliability of the internal control chip of the electronic detonator, reduce the current noise of the blasting network bus, and improve the stability of the blasting network.

[61] In the first scheme of the above-described detonating device chirp clock calibration process, the state readback command sent to an electronic detonator in step C7 is a single instruction for the electronic detonator. The instruction is composed of a preset number of m synchronous learning heads, a status readback command word and an identity code of the electronic detonator. By sending the command to the electronic detonator, the detonation device can acquire the state of the electronic detonator, thereby enabling more reliable control of the operation of the detonator.

[62] corresponding to the first scheme of the above-mentioned detonating device, the calibration process of the detonating device, in the deferred device deferral setting process, wherein the detonating device writes the step E3 in the deferred process, that is, the detonating device writes the deferred period The process can be performed as follows:

[63] Step F1, the value of the number of electronic detonators R to be written in the deferred period is the value of the number of electronic detonators in the deferred period, that is, R=E ₂ ;

[64] Step F2, reading an identity code of an electronic detonator in the blasting network stored in the detonating device; [65] Step F3, reading state information of the electronic detonator stored in the detonating device;

[66] Step F4, determining whether the electronic detonator is in a calibrated state according to the status information of the detonator: if it is not calibrated, step F9 is performed; if it is calibrated, step F5 is performed;

[67] Step F5, reading the deferred data D _{Q of} the electronic detonator stored in the detonating device;

[68] Step F6, sending a write deferral inter-turn instruction including the deferred inter-day data 126 to the electronic detonator; [69] Step F7, the control module performs a signal receiving process: if the electronic detonator receives the write delay period 吋After the completion signal, the electronic detonator is written to the electronic detonator to delay the diurnal success flag, and then step F8 is performed; if not, the detonator is deferred to the electronic detonator within the detonating device.

, then perform step F9;

[70] Step F8, the value of the electronic detonator number of the deferred diurnal error is decremented by 1, as a new value, that is, 5 ₂ = -1;

[71] Step F9, the value of the number R of deferred electronic detonators to be written is decremented by 1, as the value of the new R, that is, R=R-1;

[72] Step F10, determining whether the value of R is 0: If it is 0, proceed to step F11; if not, return to step F2;

[73] Step Fl l, End the detonation device write deferral process.

[74] In the above-described detonation device write deferral process, the write deferral inter-turn command sent to an electronic detonator in the blasting network in step F6 is a single instruction for the electronic detonator. The instruction is composed of a preset number of _m synchronous learning heads, a write deferred inter-turn command word, an identity code of the electronic detonator, and an extended inter-day data D _{Q of} the electronic detonator. The detonating device is executed to write the deferred inter-day process, and the electronic detonators in the network are successively written into the deferred data, thereby completing the deferred network deferred design.

[75] In the above-mentioned detonating device deferred setting process, the second step of the detonating device chopping process in step B3 of the detonating device chopping clock calibration process may be performed as follows:

[76] Step Gl, the number of electronic detonators to be calibrated L is the value of the number of electronic detonators of the 吋 calibration error, ie L=E!;

[77] Step G2, reading an identity code of an electronic detonator in the blasting network stored in the detonating device; [78] Step G3, reading state information of the electronic detonator stored in the detonating device;

[79] Step G4, determining whether the electronic detonator is in a calibrated state according to the status information of the detonator: if it is a calibrated state, executing step G12; if it is an uncalibrated state, proceeding to step G5; [80] Step G5, sending a clock calibration command 2 to the electronic detonator;

[81] Step G6, the control module performs a signal receiving process: if the upper calibration waveform returned by the electronic detonator is received, step G7 is performed; if not, the calibration error of the electronic detonator is set inside the detonating device. Flag, then perform step G12;

[82] Step G7, setting a success calibration flag for the electronic detonator inside the detonating device;

[83] Step G8, decrement the value of the number of false calibration electronic detonators by 1 as the new value, ie = -1

[84] Step G9, counting the preset calibration pulse number in the upper calibration waveform 3⁄4 the upper calibration pulse with the preset period T _D , and the count value is recorded as F _{B ;}

[85] Step G10, according to the n _D, and the value of T _D F _B calculates the electronic detonator inch clock frequency f _B

[86] Step Gi l, storing the cuckoo clock information of the electronic detonator, wherein the cuckoo clock information includes the value of the chopping clock frequency f _B ;

[87] Step G12, the value of the number L of electronic detonators to be calibrated is decreased by 1, as the value of the new L, that is, L=L-1;

[88] Step G13, determining whether the value of L is 0: If it is 0, proceed to step G14; if not, return to step G2;

[89] Step G14, End the calibration process of the detonating device.

[90] Corresponding to the second scheme of the above-mentioned detonating device 吋 clock calibration process, in the detonating device deferred setting process, wherein the detonating device writes the deferred device in the deferred process, the detonating device writes the deferred process during the diurnal process Follow these steps:

[91] Step Hl, the value of the number of electronic detonators R to be written during the deferred period is the value of the number of electronic detonators in the delay period, that is, R=E ₂ ;

[92] Step H2, reading an identity code of an electronic detonator in the blasting network stored in the detonating device;

[93] Step H3, reading state information of the electronic detonator stored in the detonating device;

[94] Step H4, determining whether the electronic detonator is in a calibrated state according to the status information of the detonator: if it is not calibrated, step H10 is performed; if it is calibrated, step H5 is performed;

[95] Step H5, reading the deferred data D _{Q of} the electronic detonator stored in the detonating device _; reading the value of the chopping frequency ^ of the electronic detonator stored in the control module; [96] Step H6, performing a detonation device deferred data adjustment process, and calculating a new deferred diurnal data D _f according to the value of the above-mentioned chopping clock frequency _;

[97] Step H7, transmitting, to the electronic detonator, a write delay period command including the new deferred data D _f

[98] Step H8, the control module performs a signal receiving process: if receiving the write deferral completion signal returned by the electronic detonator, writing an extension diurnal success flag to the electronic detonator inside the detonating device, and then performing step H9; If not received, the electronic detonator is written inside the detonating device to delay the diurnal error flag, and then step H10 is performed;

[99] Step H9, the value of the electronic detonator number of the deferred error is decremented by 1, as the new value, ie = -1;

[100] Step H10, the value of the number of electronic detonators R to be deferred is reduced by 1, as the value of the new R, ie R=R-1

[101] Step Hl l, determine whether the value of R is 0: If it is 0, proceed to step H12; if not, return to step H2;

[102] Step H12, ending the detonation process of the detonating device.

[103] In the second scheme of the calibration process of the detonating device, the chopping clock calibration command 2 sent to an electronic detonator in step G5 is a single instruction for the electronic detonator. The command is composed of a preset number of m synchronous learning heads, a clock calibration command word and an identity code of the electronic detonator. After the detonating device sends the cuckoo clock calibration command to the electronic detonator, it waits for the electronic detonator to follow the upper and lower calibration waveforms of the preset upper and upper calibration pulses and the preset number of cycles of the upper calibration pulse. The electronic detonator transmits the pair of upper calibration waveforms in a manner that consumes current changes. After receiving the pair of upper calibration waveforms, the detonating device calculates the chopping clock frequency f _{B of} the detonator, and executes the detonating device deferred data adjustment process according to the chopping clock frequency f _{B to} adjust the deferred daytime that should be written into the detonator Data D _f .

[104] In the above-described detonation device write deferral process, the write deferral inter-turn instruction sent in step H7 is the same as the write deferred inter-turn instruction sent in step F6. The difference is that the deferred inter-day data in the write deferred inter-turn instruction sent in step H7 is the deferred inter-day data D _f obtained after the detonating device delays the diurnal data adjustment process.

[105] The present invention also provides a second technical solution for the deferred device deferred setting process, which can be followed by the following steps. Steps:

[106] Step L1, the process is initialized, that is, the initial value of the number of electronic detonators of the variable blasting network N, the number of electronic detonators of the 校准 calibration error, the number of electronic detonators of the deferred period, the number of electronic detonators E ₂ and the number of cycles W are stored. The buffer of the control module is inactive; wherein, the value of the number of electronic detonators of the calibration clock and the value of the electronic detonator E ₂ of the delay period are equal to the value of the total number N of electronic detonators of the blasting network;

[107] Step L2, determining whether the value of the cycle number W and the value of the E ₂ is 0: If the value of the value of W or the value of 0, then continue to perform step L5; otherwise continue to perform step L3;

[108] Step L3, the control module executes the detonation device delay setting process;

[109] Step L4, the value of the number of cycles W is decremented by 1, as the value of the new W, ie W=W-1; then returns to step L2;

[110] Step L5, the control module outputs a list of error information to the human-machine interaction module, which is displayed by the human-machine interaction module; [111] Step L6, ending the deferred device deferral setting process.

[112] In the above solution, if all the detonators in the network have successfully completed the deferred setting, the detonation device is postponed. In addition, if the number of cycles has been completed and the detonation device deferred setting process is executed, the cycle is terminated regardless of whether or not the detonator has been unsuccessfully set, and an error message list is output to the operator. Designing the number of loops of the variable W to control the number of runs of the detonating device in the step L3 to set the progress of the process, and to perform the process of deferring the setting process of the detonating device automatically by executing the detonating device deferred setting process, and also It simplifies the operation steps.

[113] In the second technical solution of the detonating device deferred setting process, wherein the step L3 can be performed according to the following steps:

[114] Step Ml, set the value of the deferred electronic detonator S to be the value of the number of electronic detonators for the calibration of the cuckoo clock, ie S=E!;

[115] Step M2, reading an identity code of an electronic detonator in the blasting network stored in the detonating device;

[116] Step M3, reading state information of the electronic detonator stored in the detonating device;

[117] Step M4, determining whether the electronic detonator is in the set deferred state according to the status information of the detonator: if the deferred state is set, proceed to step M15; otherwise, proceed to step M5;

[118] Step M5, sending a chime calibration command 2 to the electronic detonator;

[119] Step M6, the control module performs a signal receiving process: if the electronic calibration of the return of the electronic detonator is received Waveform, then set the clock calibration success flag to the electronic detonator inside the detonating device, and then proceed to step M7; if not, set the clock calibration error flag to the electronic detonator inside the detonating device, and then perform step M15;

[120] Step M7, decrement the value of the electronic calibration tube number of the calibration clock to 1 as the new value, ^= -1 [121] Step M8, the number of preset calibration pulses in the upper calibration waveform 3⁄4 The upper calibration pulse with a preset period of T _D is counted, and the count value is recorded as F _{B ;}

[122] Step M9, according to the n _D, and the value of T _D F _B calculates the electronic detonator inch clock frequency f _B;

[123] Step M10, reading the deferred data D _{Q of} the electronic detonator stored in the detonating device _;

[124] Step Mi l , performing the detonation device deferred data adjustment process, and calculating the value of the new deferred diurnal data D _f according to the value of the chopping clock frequency f _B ;

[125] Step M12, sending, to the electronic detonator, a write delay inter-turn instruction including the D _f ;

[126] Step M13, the control module performs a signal receiving process: if receiving the write delay period completion signal returned by the electronic detonator, the deferral device internally writes the deferral success sign to the electronic detonator, and then proceeds to step M14; If not received, the electronic detonator is written inside the detonating device to delay the diurnal error flag, and then proceeds to step M15;

[127] Step M14, the value of the number of electronic detonators for writing the deferred error is decremented by 1 as a new value, ie, = E ₂ -1 ;

[128] Step M15, decrementing the value of the number of deferred electronic detonators S to be set as the value of the new S,

;

[129] Step M16, determining whether the value of S is 0: If it is 0, proceed to step M17; if not, return to step M2;

[130] Step M17, End the process of deferring the detonation device.

[131] During the deferred setting process of the above-mentioned detonating device, the deferred time of all electronic detonators in the blasting network is completed one by one by performing the cesium clock calibration of an electronic detonator and then writing and deferring it. set up. This omits the storage of the calculated detonator clock frequency ^, which is advantageous for simplifying the design.

[132] In the above-mentioned detonation device deferral setting process, the cuckoo clock calibration command 2 sent to an electronic detonator in step M5 is also a single instruction for the electronic detonator. The command is composed of a preset number of m synchronous learning heads, a clock calibration command word and an identity code of the electronic detonator. [133] In the above detonation device deferral setting process, the write deferral inter-turn command sent to an electronic detonator in the blasting network in step M12 is a single instruction for the electronic detonator. The instruction is composed of a preset number of m synchronous learning heads, a write deferred inter-turn command word, an identity code of the electronic detonator, and an extended inter-day data of the electronic detonator. The deferred inter-day data in the write deferred inter-turn instruction is also the deferred inter-day data D _f obtained after the detonation device delays the diurnal data adjustment process.

[134] As another aspect of the technical solution of the present invention, the control flow of the electronic detonator control chip in the electronic detonator can be performed as follows:

[135] Step Nl, the central processing unit of the chip sends a control signal to the programmable delay module, so that the programmable delay module outputs a signal, so that the ignition control circuit is disconnected, and the ignition state is prohibited;

[136] Step N2, the central processing unit 2 reads the identity code of the electronic detonator stored in the non-volatile memory; [137] Step N3, the central processing unit 2 waits to receive the synchronous learning header sent by the electronic detonator detonating device: If yes, proceed to step N4; if not, continue to wait for reception;

[138] Step N4, the central processing unit 2 performs a synchronous learning process, and according to the received synchronous learning head, adjusts the number of clocks of the RC oscillator to be written into the prescaler, the number of the clocks and the preset communication wave The rate corresponds to the preset sample phase;

[139] Step N5, the central processing unit 2 waits to receive the command word sent by the electronic detonator detonating device: if the chime calibration command word is received, enters the chime calibration state, and proceeds to step N6; if the status readback command word is received , then enter the state readback state, continue to step N7; if the write delay period command word is received, enter the write delay period, continue to step N8; if the ignition command word is received, enter the ignition state, continue Step N9;

[140] Step N6, performing an electronic detonator clock calibration process; then returning to step N5;

[141] Step N7, performing an electronic detonator status readback process; then returning to step N5;

[142] Step N8, performing an electronic detonator write deferral process; then returning to step N5;

[143] Step N9, performing an electronic detonator ignition process;

[144] Step N10, End this electronic detonator control process.

[145] The above control flow enables external online controllability of the electronic detonator's chop clock calibration process, state readback process, write deferred process, and ignition process. details as follows:

[146] First, the electronic detonator detonating device can use its own precise cuckoo clock to use the online command to carry out the 吋校 school The standard way to ensure the delay of the electronic detonator detonation network. The calibration of the electronic detonator control chip is performed to avoid the delay accuracy caused by factors such as temperature drift, drift, and parameter variation of the RC oscillator.

[147] Second, the above-mentioned electronic detonator detonating device utilizes the state readback process to realize the readback of other state information such as the chopping clock calibration state of the electronic detonator, the writing delay period, and the like, thereby more reliably controlling the operation of the detonator.

[148] Third, the above-mentioned electronic detonator detonating device utilizes the write deferral process to realize the online setting of the deferral of the electronic detonator. Further, the data can be written into the electronic detonator after adjusting the deferred data according to the result of the chop clock calibration process, that is, the accurate chop information of the obtained electronic detonator. This increases the flexibility of the use of electronic detonators.

[149] Fourth, the above-mentioned electronic detonator detonating device utilizes the ignition process to realize the control of the ignition process of the electronic detonator, which makes the ignition more reliable.

[150] In the above control flow, the synchronous learning process of step N4 is performed according to the following steps:

[151] Step 01, the central processing unit 2 monitors whether the edge signal sent by the electronic detonator detonating device is received: if received, proceed to step 02; if not, continue to monitor and wait for receiving;

[152] Step 02, sending a control signal to the counter to start the counter;

[153] Step 03, the central processing unit 2 monitors whether the edge signal sent by the electronic detonator detonating device is received: if received, proceed to step 04; if not, continue monitoring;

[154] Step 04, the central processor 2 reads the count value of the counter at this moment, and saves the count value; [155] Step 05, the central processor 2 determines whether the number of received edge signals reaches the The synchronization learning head is preset to be twice the preset number m, that is, whether to receive 2m edge signals: if 2m edge signals are received, proceed to step 06; if not, return to step 03;

[156] Step 06, sending a control signal to the counter to stop the counter;

[157] Step 07, the central processing unit 2 calculates, according to the count values stored in the internal buffer, the number of clocks of the RC oscillator that should be written into the prescaler, the number of the clocks and the preset communication wave The rate corresponds to the preset sample phase;

[158] Step 08, writing the number of the clocks into the prescaler;

[159] Step 09, End this synchronous learning process. [160] This synchronous learning process eliminates the effect of the frequency dispersion of the RC oscillator integrated in the chip on the reliability of electronic detonator data reception. The electronic detonator detonating device sends a command to the chip, and sends a preset number of m synchronous learning heads before sending the command word. Inside the chip, when the edge signal of the synchronous learning head is received, the counter inside the startup chip counts the number of synchronous learning heads. Then, the central processor 2 calculates the number of RC oscillators that the serial communication interface should use corresponding to the preset communication baud rate and the preset sampling phase, thereby adjusting the data reception of the electronic detonator Downtime and counting interval. This ensures that even if the RC oscillator has problems such as temperature drift, drift, and parameter changes, the electronic detonator control chip incorporating the RC oscillator can reliably receive the control commands sent by the electronic detonator detonating device.

[161] In the above electronic detonator control flow, the first embodiment of the electronic detonator clock calibration process in step N6 can be performed as follows:

[162] Step P1, the central processing unit 2 monitors whether the edge signal sent by the electronic detonator detonating device is received: if received, proceed to step P2; if not, continue to monitor and wait for receiving;

[163] Step P2, sending a control signal to the counter to start the counter;

[164] Step P3, monitoring whether an edge signal sent by the electronic detonator detonating device is received: if received

, proceed to step P4; if not received, continue to monitor waiting for reception;

[165] Step P4, reading the counter value of the counter at this moment, and saving the count value to the cache of the internal processor 2;

[166] Step P5, the central processor 2 determines whether the number of received edge signals reaches twice the preset number of lower calibration pulses 3⁄4, that is, whether to receive 2n _B edge signals: if 2n _B are received Edge signal, proceed to step P6; if not, return to step P3;

[167] Step P6, sending a control signal to the counter to stop the counter;

[168] Step P7, the central processor 2 calculates the chirp clock frequency of the RC oscillator according to the count values in the counter, the preset number of the next calibration pulses n _B , and the preset period T _{B of} the pair of lower calibration pulses. The value of f _D ;

[169] Step P8, the central processor 2 positions its internal cuckoo calibration flag to a calibrated state;

[170] Step P9, ending the calibration process of the electronic detonator clock.

[171] In the above-mentioned electronic detonator clock calibration process, the electronic detonator detonating device sends a cuckoo clock calibration command to all the electronic detonators in the blasting network, that is, the cuckoo clock calibration command sent in the step C1. The instruction is a global command, in addition to sequentially including the synchronous learning head and the clock calibration command word, there is a sub-calibration consisting of a preset downward calibration pulse number of 3⁄4 preset calibration pulses of T _B Waveform. The electronic detonator detonating device uses its own stable and accurate cuckoo clock source to transmit the above-mentioned paired calibration waveform for the counter inside the chip to segment the waveform. The central processor 2 inside the chip calculates the clock frequency f _{D of the} chip's own RC oscillator according to the count value, the preset number n _B of the lower calibration pulse, and the preset period T _B of the lower calibration pulse, and The result is stored inside the chip. Due to problems such as temperature drift, drift, and parameter changes of the RC oscillator, there are individual differences in the chirp clock frequency of each electronic detonator control chip in the blasting network. Therefore, a uniform, stable and accurate electronic detonator detonating device is used. Zhongyuan's calibration of the cuckoo clock of the chip is beneficial to eliminate the influence of the existence of individual differences on the delay accuracy of the blasting network and improve the delay accuracy of the blasting network.

[172] Corresponding to Embodiment 1 of the above-mentioned electronic detonator clock calibration process, in the electronic detonator control flow, the electronic detonator status readback process in step N7 can be performed as follows:

[173] Step R1, the central processor 2 determines whether to read back the status of the detonator according to the identity code of the detonator in the status readback instruction: if the status code of the detonator in the status readback instruction and the identity read in step N2 If the code matches, step R2 is performed; if not, step R3 is performed;

[174] Step R2, the central processor two-way electronic detonator detonating device sends the status information of the detonator;

[175] Step R3, ending the electronic detonator status readback process.

[176] In the above-described electronic detonator state readback process, the electronic detonator detonating device sends a status readback command to an electronic detonator in the blasting network as a single instruction for the electronic detonator. The instruction includes the identity code of the corresponding electronic detonator in addition to the synchronous learning head and the status readback command word as described above. The design of the process enables the electronic detonator detonating device to acquire the state of the electronic detonator, thereby enabling the device to more reliably control the operation of the detonator.

[177] Corresponding to Embodiment 1 of the electronic detonator clock calibration process, in the above-described electronic detonator control flow, the electronic detonator writing delay period in step N8 can be performed as follows:

[178] Step S1, the central processing unit 2 determines whether to write the extension of the detonator according to the identity code of the detonator in the deferred inter-turn instruction: if the ID code of the detonator in the deferred inter-turn instruction is read and the step N2 reads out If the identity code matches, proceed to step S2; if not, terminate the electronic detonator write deferral process; [179] Step S2, performing an electronic detonator delay diurnal data adjustment process according to the deferred diurnal data D _{Q in} the write deferred inter-turn instruction, and obtaining the adjusted deferred diurnal data D _{N ;}

[180] Step S3, writing the adjusted deferred data to the programmable delay module;

[181] Step S4, the central processor 2 sets the internal deferred time setting flag to the set deferred state; the central processor two-way electronic detonator detonating device sends the write deferral completion signal;

[182] Step S5, ending the electronic detonator writing deferral process.

[183] In the above-mentioned electronic detonator writing delay period, the electronic detonator detonating device sends a deferred inter-turn command to an electronic detonator in the blasting network, that is, an instruction sent by the detonating device in step F6. The instruction is a single instruction for the electronic detonator. The instruction includes the identity code of the corresponding electronic detonator and its deferred inter-day data D _{Q in} addition to the synchronous learning header and the write-delay inter-duration command word described above. After receiving the deferred data D _Q sent by the electronic detonator detonating device, the central processing unit first performs the electronic detonator delay according to the result of the electronic detonator clock calibration process, that is, the calculated detonator clock frequency f _D . During the diurnal data adjustment process, a new deferred diurnal data D _{N is} calculated _; then the adjusted deferred diurnal data D _{N is} written into the programmable deferred module. This achieves an online setting of the deferred time of the electronic detonator, thereby increasing the flexibility of use of the electronic detonator. Moreover, the deuterium clock frequency f _D calculated by the electronic detonator clock calibration process is adjusted to the deferred data 13⁄4 sent by the electronic detonator detonating device, and then written to the programmable delay module, which also ensures the extension of the electronic detonator Precision.

[184] In the above electronic detonator control flow, the implementation scheme 2 of the electronic detonator clock calibration process in step N6 can be performed as follows:

[185] Step Q1, the value of the number of calibration pulses to be sent is set to a value of a preset number of calibration pulses n _D , that is, k=n _D ;

[186] Step Q2, the central processor 2 determines whether to perform the calibration of the detonator according to the identity code of the detonator in the calibration command of the second clock: if the identification code of the detonator in the second calibration command is read out in step N2 If the identity code matches, step Q3 is performed; if not, step Q16 is performed;

[187] Step Q3, the central processor two-way counter writes a high-level width pre-designed value u _D of the upper calibration pulse;

[188] Step Q4, the central processing unit 2 sends a control signal to the communication interface circuit through the serial communication interface, so that the current consumed by the communication interface circuit on the signal bus increases; [189] Step Q5, sending a control signal to the counter to start the counter;

[190] Step Q6, the central processor 2 monitors whether the pre-designed value u _{D is} reached _: if it is, then steps are performed.

Q7; If not, continue to monitor and wait for arrival;

[191] Step Q7, sending a control signal to the counter to stop the counter;

[192] Step Q8, the central processor two-way counter writes the low-level width pre-designed value v _D of the upper calibration pulse;

[193] Step Q9, the central processing unit 2 sends a control signal to the communication interface circuit through the serial communication interface, so that the current consumed by the communication interface circuit on the signal bus is reduced;

[194] Step Q10, sending a control signal to the counter to start the counter;

[195] Step Q11, the central processor 2 monitors whether the pre-designed value v _D is reached _: if yes, proceed to step Q12; if not, continue to monitor and wait for arrival;

[196] Step Q12, sending a control signal to the counter to stop the counter;

[197] Step Q13, the value of the number of the upper calibration pulse to be sent is decremented by 1 as the value of the new k, gP, k=kl _;

[198] Step Q14, determining whether the value of k is 0: if it is 0, proceed to step Q15; if not, return to step Q3;

[199] Step Q15, the central processor 2 positions its internal cuckoo calibration flag to a calibrated state;

[200] Step Q16, End the calibration process of the electronic detonator clock.

[201] In the above-mentioned electronic detonator clock calibration process, the electronic detonator detonating device sends a cuckoo clock calibration command to an electronic detonator in the blasting network, that is, the cuckoo clock calibration command sent by the detonating device in step G5 or step M5 . The instruction is a single instruction, and includes the identity code of the corresponding electronic detonator in addition to the synchronous learning head and the clock calibration command word described above. After receiving the cuckoo clock calibration command 2, the detonator sends the up-alignment calibration to the electronic detonator detonating device according to the preset high-low level width and v _D of the upper calibration pulse and the preset number of cycles of the upper calibration pulse. Waveform. After receiving the pair of upper calibration waveforms, the electronic detonator detonating device calculates the chopping clock frequency f _{B of} the detonator, and adjusts according to the chopping clock frequency f _B and the initial deferred diurnal data D _Q corresponding to the detonator. Enter the new deferred data D _{f of} the detonator. This achieves an online calibration of the RC oscillator. Compared with the first embodiment, the central processor 2 inside the detonator does not need to have complicated calculation functions, thereby simplifying the logic design of the chip; on the other hand, The adjustment process for the delay period is The electronic detonator detonation device is carried out. Therefore, the detonation accuracy of the detonator can be flexibly adjusted according to the actual application requirements of the blasting engineering, which also improves the adaptability of the electronic detonator under different delay precision requirements.

[202] In the second embodiment of the electronic detonator clock calibration process, a preferred solution is: the value of the low-level width pre-designed value _Vd is greater than the value of the high-level width pre-designed value u _D ; and, low power The sum of the value of the flat width pre-designed value v _{D and} the value of the high-level width pre-designed value u _D is equal to the preset period T _D of the upper calibration pulse. The benefits are:

[203] 1. Since the electronic detonator transmits data to the electronic detonator detonating device in a current consumption manner, and the calibration pulse high level signal is transmitted on the transmitting pair, the current consumption increases, thereby requiring more consumption of the electronic detonator detonating device. energy. Therefore, reducing the width of the high level signal can reduce the energy consumption of the electronic detonator detonating device during the calibration of the chirp.

[204] 2. On the transmit pair, calibrate the pulse high level signal, the input of the rectifier bridge circuit in the electronic detonator control chip is short-circuited. Therefore, not only the charging process of the external energy storage device of the electronic detonator control chip will be stopped, but also the operation of the digital logic circuit inside the chip consumes energy in the energy storage device. When the low-level signal of the upper calibration pulse is sent, the input end of the rectifier bridge circuit is in an open state, and the energy storage device outside the chip can be continuously charged. Therefore, by reducing the pre-designed value of the calibration pulse high-level width and increasing the calibration pulse low-level width pre-design value v _D , the waveform is calibrated on the transmission pair, thereby reducing energy consumption in the energy storage device, It can increase the supplemental energy of the energy storage device, which improves the operational reliability of the electronic detonator control chip, reduces the current noise of the blasting network bus, and improves the stability of the blasting network.

[205] Corresponding to the second embodiment of the electronic detonator clock calibration process, in the above electronic detonator control process, the electronic detonator writing delay period in step N8 can be performed according to the following steps:

[206] Step Tl, the central processing unit 2 determines whether to write the extension of the detonator according to the identity code of the detonator in the deferred inter-turn instruction; if the derivation of the detonator's identity code in the deferred inter-turn instruction and the step 读取2 read out If the identity code matches, proceed to step Τ2; if not, end the electronic detonator write deferral process;

[207] Step Τ2, the central processor 2 writes the deferred inter-day data D _f in the write deferred inter-turn instruction to the programmable extension module;

[208] Step T3, the central processor 2 sets the internal deferred time setting flag to the set deferred state; The central processor two-way electronic detonator detonating device sends a write delay period completion signal;

[209] Step T4, End the electronic detonator write deferral process.

[210] Corresponding to the second embodiment of the electronic detonator clock calibration process, since the adjustment process of the deferred data is performed in the electronic detonator detonating device, for the chip, it is only necessary to directly delay the writing. The deferred data D _f in the inter-direct command can be written into the programmable module. This eliminates the need to design an arithmetic logic unit in the central processing unit 2 of the chip, which greatly simplifies the design of the chip.

DRAWINGS

1 is a schematic diagram showing the network structure of an electronic detonator detonating system according to the present invention;

2 is a general schematic view showing the functional configuration of the detonating device of the present invention;

_{3 is} a general block diagram of an electronic detonator control chip in the present invention;

4 is a block diagram showing the structure of a chip internal logic control circuit in the present invention;

[215] FIG. _{5 is} a first technical solution of the deferred device deferred setting process in the present invention;

Figure _{6 is} a flow chart showing the calibration process of the detonating device chopping time in the present invention;

Figure _{7 is} a flow chart showing the flow of the detonation device during the deferred period in the present invention;

[218] FIG. ₈ is a flow chart of the first scheme of the calibration process of the detonating device in the present invention;

₉ is a flow chart of a first scheme of the detonation process of the detonating device in the present invention;

[220] FIG. 10 is a schematic diagram showing the structure of a calibration command 1 of the present invention;

[221] FIG. 11 is a flow chart showing a flow of sending a calibration waveform of a detonating device according to the present invention;

12 is a flow chart of a second scheme of the calibration process of the detonating device in the present invention;

[223] FIG. 13 is a flow chart of the second scheme of the detonation process of the detonating device in the present invention;

[224] FIG. 14 is a second technical scheme of the deferred device deferral setting process in the present invention;

[225] FIG. 15 is a flow chart showing a process of deferring setting of a detonating device according to the present invention;

[226] FIG. 16 is a schematic diagram showing the structure of a global command in the present invention;

[227] FIG. 17 is a schematic diagram of a write deferred inter-turn instruction in the present invention;

18 is a schematic diagram showing the structure of a calibration command 2 of the cuckoo clock in the present invention;

19 is a schematic diagram showing the structure of a state readback instruction in the present invention;

20 is a schematic diagram of a control flow of an electronic detonator control chip according to the present invention;

21 is a flow chart of a synchronous learning process in the present invention; 22 is a schematic flow chart of Embodiment 1 of an electronic detonator clock calibration process according to the present invention;

23 is a schematic flow chart of Embodiment 2 of an electronic detonator clock calibration process according to the present invention;

24 is a flow chart showing the process of reading back state of an electronic detonator in the present invention;

25 is a schematic flow chart of Embodiment 1 of an electronic detonator writing delay period process according to the present invention;

26 is a schematic flow chart of Embodiment 2 of an electronic detonator writing delay period process according to the present invention;

[237] FIG. 27 is a schematic diagram showing voltage waveforms of a chip transmitting a pair calibration waveform and a logic control circuit outputted to a communication interface circuit in the present invention;

28 is a schematic diagram of a current waveform of a chip transmitting a pair calibration waveform and a communication interface circuit outputted to a signal bus according to the present invention;

29 is a schematic diagram of a chirping pulse outputted by an RC oscillator in the present invention;

Figure 30 is a flow chart showing the signal receiving process performed by the detonating device in the present invention.

Implementation

The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments.

[242] The electronic detonator detonating system of the present invention is composed of a detonating device 300 and one or more electronic detonators 400, which constitute a detonator network as shown in FIG. 1, and one or more electronic detonators 400 are connected in parallel by detonation. The device 300 is shown on the signal bus 500.

[243] In the above electronic detonator detonation system, the design of the detonating device is based on the patent application document 200810135028.

The technical solution disclosed in 0, the detonating device 300 of the solution includes a control module 301, a human-machine interaction module 302, a power management module 303, a signal modulation transmitting module 304, a signal demodulation receiving module 305, and a power source 306, see FIG. Shown. The control module 301 further includes a central processing unit 1 and a fixed processor. The technical solution of the detonating device constructs the basic framework of the electronic detonator detonating device, and realizes the basic functions of the detonating device such as the two-way communication with the electronic detonator and the detonating electronic detonator.

[244] In the above electronic detonator detonating system, the electronic detonator control chip in the electronic detonator 400 is further designed on the basis of the patent ZL200 820111269.7 and the patent application document 200810211374.2, and an electronic detonator control chip capable of performing the calibration of the cuckoo clock is given. 200, referring to FIG. 3, the chip 200 includes a rectifying bridge circuit 201, a igniting control circuit 202, an energy management module 204, a communication interface circuit 203, a nonvolatile memory 205, a cuckoo clock circuit 206, a power management circuit 207, and logic. The control circuit 208, and the cuckoo clock circuit 206 is taken as the RC oscillator 210, for improving the impact resistance of the electronic detonator control chip 200. The energy management module 204 may be composed of a charging circuit 401 and a safety discharge circuit 403, corresponding to the electronic detonator control chip technical solution given in the patent ZL20 0820111270.X; the energy management module 204 may also be the charging circuit 401 and the charging control circuit 402. And the safety discharge circuit 403, which corresponds to the electronic detonator control chip technical solution given in the patent ZL200820 111269.7; more preferably, the energy control module 204 can also be composed of the charging circuit 401, the safety discharge circuit 403 and the detection circuit, and the patent application The electronic detonator control chip technical solution given in the document 20 0810108689.4 corresponds to; or the energy management module 203 can also be composed of the charging circuit 401, the charging control circuit 402, the safety discharging circuit 403 and the detecting circuit, and the patent application file 200810108688.X The technical scheme of the electronic detonator control chip is given. The logic control circuit 208 further includes a programmable delay module 281, an input/output interface 282, a serial communication interface 283, a prescaler 284, a counter 287, and a central processing unit 285, as shown in FIG. The counter 287 is connected to the power output terminal of the power management circuit 207, and is powered by the power management circuit 207; one end is grounded; one end is connected to the central processing unit 285 via the internal bus 286, and the central processor 285 controls its working process and reads the counter. The count value in 287; the remaining end of counter 287 is coupled to central processor 285, programmable delay module 281, and prescaler 284, and is commonly coupled to RC oscillator 210, which provides the desired chirp signal for operation by RC oscillator 210. . The electronic detonator control chip 200 thus designed has better impact resistance and sufficient delay between turns. The chip 200 uses an RC oscillator as a chopper circuit to improve the impact resistance of the detonator. For the problem that the RC oscillator has frequency drift and frequency deviation, the present invention further designs to calibrate the cuckoo clock of the chip 200 by sending a control command to the chip 200 by the detonating device 300 outside the chip 200, thereby improving the detonating system. Delay the inter-turn accuracy.

[245] As an aspect of the technical solution of the present invention, there are two technical solutions for the detonating device to delay the setting process.

The first technical solution can be performed by referring to the process shown in FIG. 5:

[246] Step A, the control module 301 in the detonating device 300 performs a calibration process of the detonating device cuckoo clock;

[247] Step A2, performing the detonation device to write the deferred process;

[248] Step A3, outputting a list of error information to the human-machine interaction module 302, which is displayed by the human-machine interaction module 302; [249] Step A4, ending the deferred device deferral setting process.

[250] The first technical solution of the detonating device deferred setting process shown in FIG. 5 performs the detonating device chopping clock calibration process before performing the detonating device writing deferral process, and corrects the chopping frequency of the electronic detonator 400. The accuracy of each electronic detonator 400 in the blasting network is ensured, thereby improving the delay of the entire blasting network. Step A3 sends the deferred setting error information list to the human-computer interaction module 302 for display, so that the detonating device operator can determine the error according to the delay setting of the blasting network and the importance of the blasting hole of the detonator. The detonating device delays the setting process to ensure that all the electronic detonators 400 in the blasting network complete the deferral setting, or perform the next operation on the electronic detonator 400 in the blasting network that has completed the deferred setting. This design increases the flexibility of blasting construction control.

[251] In general, in conjunction with the main control flow of the electronic detonator detonating device given in the patent application document 200810135028.0, it is preferred to perform the deferred device deferral setting process after the execution of the detonation preparation task and before the execution of the demolition network charging task is completed. Therefore, the data interaction with the electronic detonator 400 during the execution of the process is always performed under the communication voltage, ensuring the security of the deferred setting process.

[252] In the deferred device deferred setting process shown in Fig. 5, the detonating device 校准 calibration process of step A1 can be performed according to the following steps, as shown in Fig. 6:

[253] Step B1, initializing the calibration process of the detonating device, that is, storing the total number of electronic detonators of the variable blasting network N, the number of erroneous electronic detonators, and the initial number of cycles into the buffer of the control module 301. use. And, obtaining the value as the value of the N;

[254] Step B2, the control module 301 determines whether the value of the cycle number and the value of the electronic calibration detonator of the calibration clock is 0: if the value or the value is 0, the calibration process of the detonating device is completed.

Otherwise continue to step B3;

[255] Step B3, performing a detonating device 吋 clock calibration process;

[256] Step B4, the value of the number of loops is decremented by 1, as the value of the new ^, ie \¥ ₁ =\¥ ₁ -1; and then returns to step B2.

[257] In the deferred device deferred setting process shown in Fig. 5, the detonating device writing deferral process in step A2 can be performed according to the following steps, as shown in Fig. 7:

[258] Step El, initializing the deferred device write deferral process, that is, storing the total number of electronic detonators of the variable blasting network N, writing the delay period, the number of electronic detonators E ₂ and the initial value of the cycle number W ₂ The cache of the control module 301 is inactive. And obtaining the value as the value of the N;

[259] Step E2, the control module 301 determines the value of the number of cycles W ₂ and the number of electronic detonators of the delay period during the write delay period. Whether the value is 0: If the value of W ₂ or the value of E ₂ is 0, then step E5 is performed; otherwise, step E3 is continued;

[260] Step E3, performing the detonation device to write the deferred process;

[261] Step E4, the value of the number of cycles W ₂ is decremented by 1, as the value of the new \¥ ₂ , that is, W ₂ = W ₂ -1; then returns to step E2;

[262] Step E5, ending the detonation process of the detonating device.

[263] In the above-described blasting device 校准 calibration process shown in FIG. 6 and the detonation device writing delay 吋 process shown in FIG. 7, respectively, a cycle number variable W nw _{2 is} designed, correspondingly controlling the step B3 detonating device 吋 clock calibration process and Step E3, the detonating device writes the number of runs of the deferred process, and exemplifies the process of automatically performing a plurality of chopping processes and writing the deferred inter-turn process by performing a detonating device deferral setting process, thereby simplifying the operation steps. It reduces the misoperation caused by cumbersome multiple human operations and improves the reliability of equipment operation. This is because, after each execution of the detonating device deferred setting process shown in FIG. 5, an error message list is output to prompt the selection of the next operation, and the transient system is faulty due to the instantaneous failure of the network. The clock is calibrated incorrectly or the possibility of delaying the inter-turn error is written. Therefore, the detonating device 300 is designed to automatically execute the preset number of cycles \\^ times the clock calibration process and the preset cycle times 3⁄4W ₂ write extensions During the daytime process, the operator's action on the device can be simplified, thereby improving the reliability of the operation of the detonating device. Referring to FIG. 6 and FIG. 7, when the detonating device 300 completes the preset number of cycles of the chime calibration process or the electronic detonator that does not have the chopping calibration error in the system, the detonating device chopping clock calibration process is ended; when the detonating device 300 is completed The preset number of cycles W ₂ writes the deferred process or the electronic detonator that does not have the delay of writing the delay in the system, and then terminates the detonation device to write the deferred process.

[264] In the priming calibration process of the detonating device shown in Fig. 6, the scheme of the detonating device 步骤 clock calibration process of step B3 can be carried out according to the following steps, as shown in Fig. 8:

[265] Step Cl, sending a clock calibration command one to the electronic detonators 400 in the blasting network;

[266] Step C2, the control module 301 waits to reach the preset delay interval ^: if it arrives, proceeds to step C3; if not, continues to wait for arrival;

[267] Step C3, the number of electronic detonators to be calibrated L is the value of the number of electronic detonators of the 吋 calibration error, that is, L=E!;

[268] Step C4, reading the identity generation of an electronic detonator 400 stored in the detonating device 300 in the blasting network code;

[269] Step C5, reading state information of the electronic detonator 400 stored in the detonating device 300;

[270] Step C6, determining whether the electronic detonator 400 is in a calibrated state according to the status information of the detonator: if it is a calibrated state, performing step C13; if it is an uncalibrated state, proceeding to step C7;

[271] Step C7, sending a status readback instruction to the electronic detonator 400;

[272] Step C8, the control module 301 performs a signal receiving process: if the information returned by the electronic detonator 400 is received

, proceed to step C9; if not, proceed to step C12;

[273] Step C9, the control module 301 saves the information returned by the electronic detonator, and determines whether the clock calibration flag of the electronic detonator is in a calibrated state: if it is a calibrated state, step C10 is performed; if it is not calibrated , step C12 is performed;

[274] Step C10, setting a clock calibration success flag to the electronic detonator 400 inside the detonating device 300;

[275] Step C11, decrementing the value of the number of false calibration electronic detonators by 1 as the new value, ie = -1

Then proceed to step C13;

[276] Step C12, placing an error calibration flag on the electronic detonator 400 inside the detonating device 300; then proceeding to step C13;

[277] Step C13, the value of the number L of electronic detonators to be calibrated is decreased by 1, as the value of the new L, that is, L=L-1;

[278] Step C14, determining whether the value of the number of electronic detonators to be calibrated is 0: If it is 0, proceeding to step C15

If not 0, return to step C4;

[279] Step C15, ending the calibration process of the detonating device.

[280] Corresponding to the first scheme of the detonating device 吋 clock calibration process shown in FIG. 8, in the detonation device writing deferral process in FIG. 7, the E3 detonating device writing deferral process can be performed according to the following steps. As shown in Figure 9:

[281] Step F1, the value of the number of electronic detonators R to be written in the deferred period is the value of the number of electronic detonators in the deferred period, that is, R=E ₂ ;

[282] Step F2, reading an identity code of an electronic detonator 400 stored in the detonating device 300 in the blasting network;

[283] Step F3, reading state information of the electronic detonator 400 stored in the detonating device 300;

[284] Step F4, determining, according to the status information of the detonator, whether the electronic detonator 400 is in a calibrated state: In the uncalibrated state, step F9 is performed; if it is in the calibrated state, step F5 is performed;

[285] Step F5, reading the deferred data D of the electronic detonator 400 stored in the detonating device 300. [286] Step F6, transmitting to the electronic detonator 400 a write delay period command including the above-mentioned deferred data 13⁄4

[287] Step F7, the control module 301 performs a signal receiving process: if the write delay period completion signal returned by the electronic detonator 400 is received, the electronic detonator 400 is internally written with the deferred success sign in the detonating device 300, and then Step F8 is performed; if not received, the deferred device 300 is internally written with the deferred error flag inside the detonator 300, and then step F9 is performed;

[288] Step F8, the value of the electronic detonator number of the deferred error is decremented by 1 as a new value, that is, 5 ₂ = -1;

[289] Step F9, the value of the number R of deferred electronic detonators to be written is decremented by 1, as the value of the new R, that is, R=R-1;

[290] Step F10, determining whether the value of R is 0: If it is 0, proceed to step F11; if not, return to step F2;

[291] Step Fl l, End the detonation device to write the deferred process.

[292] In the first scheme of the detonating device 校准 clock calibration process shown in FIG. 8, the cesium clock calibration command sent to all the electronic detonators 400 in the blasting network by performing step C1 is a global command. The command is composed of a preset number of m synchronous learning heads, a clock calibration command word and a lower calibration waveform, wherein the lower calibration waveform is preset by the preset number of downward calibration pulses by 3⁄4 preset periods. The pulse is constructed as shown in FIG. The detonating device 300 transmits the synchronous learning head and the lower calibration waveform by using its own stable and accurate chime source, and the counter 287 inside the chip 200 performs segmentation counting on the above-mentioned lower calibration waveform, and further calculates the chip 200 itself. The cuckoo clock frequency.

[293] The advantage of transmitting the synchronous learning header before sending the command word is: when the electronic detonator control chip 200 receives the edge signal of the synchronous learning head, the counter 287 inside the chip 200 is immediately activated for the synchronous learning head. Counting is performed; then, the central processing unit 285 inside the chip 200 calculates the clocks of the RC oscillators that the serial communication interface 283 should use corresponding to the preset communication baud rate and the preset sampling phase respectively. The number, thereby adjusting the data reception downtime and counting interval of the electronic detonator 400. See the synchronous learning process of the electronic detonator 400 shown in FIG. This can ensure that even if the RC oscillator has problems such as temperature drift, drift, parameter variation, etc., the electronic detonator control chip 200 using the RC oscillator 210 as the chopper circuit can still It is reliable enough to receive control commands sent from outside the electronic detonator 400.

[294] The downward calibration waveform in the first calibration command shown in FIG. 10 is sent by the control module 301 to perform the following detonating device calibration waveform transmission process, as shown in FIG.

[295] Step D1, the value of the number of the next calibration pulse to be sent is set to the value of the preset pair of lower calibration pulses n _B , 艮卩n=n _B ;

[296] Step D2, writing a low-level preset value v _B of the lower calibration pulse to the fixed buffer _;

[297] Step D3, sending a control signal to the signal modulation transmitting module 304 to output a falling edge signal;

[298] Step D4, sending a control signal to the fixed device to start the calibration device;

[299] Step D5, the CPU detects whether the length of the low-level signal output by the signal modulation transmitting module 304 reaches the low-level preset value v _{B :} if it arrives, proceeds to step D6; if not, continues Monitoring waiting to arrive;

[300] Step D6, sending a control signal to the fixed device to stop the calibration device;

[301] Step D7, writing a high-level preset value of the lower calibration pulse to the fixed buffer _3⁄4;

[302] Step D8, sending a control signal to the signal modulation sending module 304 to output a rising edge signal;

[303] Step D9, sending a control signal to the fixed device to start the calibration device;

[304] Step D10, the central processor monitors whether the length of the high-level signal output by the signal transmitting module 304 reaches a high-level preset value of _3⁄4: if it arrives, proceeds to step D11; if not, continues Monitoring waiting to arrive;

[305] Step D11, sending a control signal to the fixed device to stop the calibration device;

[306] Step D12, the value of the number n of the lower calibration pulse to be transmitted is decreased by 1, as a new value of n, that is, n=n-l;

[307] Step D13, determining whether the value of n is 0: If 0, proceed to step D14; if not, return to step D2;

[308] Step D14, ending the sending process of the calibration waveform of the detonating device.

[309] In the sending flow of the detonating device calibration waveform shown in FIG. 11, the value of the high-level preset value of the lower calibration waveform is greater than the value of the low-level preset value of the lower calibration pulse, and 3⁄4 The sum of the value and the value of ^ is equal to T _B , see the schematic diagram of the lower calibration waveform shown in FIG. In combination with the two implementations of the host communication interface disclosed in the patent application document 20081017241 0.9, which is composed of a unipolar communication interface or a bipolar communication interface, the advantage of designing the lower calibration pulse in such a scheme is: when the detonating device 300 is directed to the electronic device Ray The tube 400 transmits a high level calibration pulse 吋 in a state of supplying a forward voltage to the detonator 400; and when a low level calibration pulse 发送 is transmitted, it is in a state of stopping power supply to the detonator 400 or supplying a negative voltage to the detonator 400. Therefore, increasing the width of the calibration pulse high level, that is, prolonging the transmission of the high level signal, can prolong the power supply of the detonator 300 to the detonator 400, and reduce the power consumption of the internal energy storage device 600 of the electronic detonator 400. This is beneficial to improve the operational reliability of the internal control chip 200 of the electronic detonator 400, reduce the current noise of the blasting network bus, and improve the stability of the blasting network.

[310] In the first scheme of the detonating device chirp clock calibration process shown in Fig. 8, the state readback command sent to an electronic detonator in step C7 is a single instruction for the electronic detonator. The instruction is composed of a preset number of m synchronous learning heads, a status readback command word, and an identity code of the electronic detonator, as shown in FIG. By transmitting the command to the electronic detonator 400, the state of the electronic detonator 400 can be achieved by the detonating device 300, thereby enabling more reliable control of the detonator operation.

[311] In the process of writing the deferred period of the detonating device shown in FIG. 9, the write deferred inter-turn instruction sent to an electronic detonator in the blasting network in step F6 is a single instruction for the electronic detonator. The instruction is composed of a preset number of m synchronous learning heads, a write deferred inter-turn command word, an identity code of the electronic detonator, and an extended inter-day data of the electronic detonator, as shown in FIG. 17. The detonation device is shown in FIG. 9 to write the deferred inter-day process, and the electronic detonators 400 in the network are sequentially written into the deferred data, thereby completing the design of the detonator network delay. After receiving the deferred data sent by the detonating device 300, the central processing unit 285 inside the electronic detonator control chip 200 firstly performs the result of the electronic detonator clock calibration process shown in FIG. 22, that is, the calculated detonator clock. The frequency f _{D is} executed to perform an electronic detonator delay diurnal data adjustment process, and a new deferred diurnal data D _{N is} calculated _; then the adjusted deferred diurnal data D _{N is} written into the programmable delay module 281 inside the chip 200 .

[312] In the calibration process of the detonating device 吋 clock shown in Fig. 6, the detonating device 步骤 clock calibration process of step B3 can also be performed according to the steps of the second scheme, as shown in Fig. 12:

[313] Step Gl, the number of electronic detonators to be calibrated L is the value of the number of electronic detonators of the 吋 calibration error, that is, L=E!;

[314] Step G2, reading an identity code of an electronic detonator 400 stored in the detonating device 300 in the blasting network;

[315] Step G3, reading state information of the electronic detonator 400 stored in the detonating device 300; [316] Step G4, determining whether the electronic detonator 400 is in a calibrated state according to the status information of the detonator: if it is a calibrated state, step G12 is performed; if it is an uncalibrated state, proceeding to step G5;

[317] Step G5, sending a cuckoo clock calibration command 2 to the electronic detonator 400;

[318] Step G6, the control module 301 performs a signal receiving process: if the upper calibration waveform returned by the electronic detonator 400 is received, step G7 is performed; if not, the electronic detonator ₄₀₀ is disposed inside the detonating device 300.吋校准 calibration error flag, and then perform step G12;

[319] Step G7, setting a clock calibration success flag to the electronic detonator 400 inside the detonating device 300;

[320] Step G8, decrement the value of the electronic calibration detonator of the 吋 calibration error by 1, as the new value, ie = -1

[321] Step G9, counting the number of the preset pair of upper calibration pulses in the pair of upper calibration waveforms n _D preset calibration pulses of preset period T _D , the count value is recorded as F _{B ;}

[322] Step G10, based on the value of n _D, the T _D F _B and the calculating of the electronic detonator 400 inch clock frequency f _B;

[323] Step Gi l, storing the cuckoo clock information of the electronic detonator 400, the cuckoo clock information includes the value of the cuckoo clock frequency f _B ;

[324] Step G12, the value of the number L of electronic detonators to be calibrated is decreased by 1, as the value of the new L, that is, L=L-1;

[325] Step G13, determining whether the value of L is 0: If it is 0, proceed to step G14; if not, return to step G2;

[326] Step G14, ending the calibration process of the detonating device.

[327] Corresponding to the second scheme of the detonating device 校准 calibration process shown in FIG. 12, in the detonation device writing deferral process shown in FIG. 7, the detonating device writing deferral process in step E3 can be performed according to the following steps. , as shown in Figure 13:

[328] Step H1, the value of the number of electronic detonators R to be written during the deferred period is the value of the number of electronic detonators in the deferred period, that is, R=E ₂ ;

[329] Step H2, reading an identity code of an electronic detonator 400 stored in the detonating device 300 in the blasting network;

[330] Step H3, reading state information of the electronic detonator 400 stored in the detonating device 300;

[331] Step H4, determining, according to the status information of the detonator, whether the electronic detonator 400 is in a calibrated state: In the uncalibrated state, step H10 is performed; if it is in the calibrated state, step H5 is performed;

[332] Step H5, reading the deferred data D of the electronic detonator 400 stored in the detonating device 300. Reading the value of the chirp clock frequency of the electronic detonator 400 stored in the control module 301;

[333] Step H6, performing a detonation device delay diurnal data adjustment process, and calculating a new deferred diurnal data D _f according to the value of the above-mentioned chopping clock frequency ^ _;

[334] Step H7, 400 sends to the electronic detonator comprises an extension inch between said new write data D _f inches between the extension instruction;

[335] Step H8, the control module 301 performs a signal receiving process: if the write delay period completion signal returned by the electronic detonator 400 is received, the electronic detonator 400 is internally written with the deferred success sign in the detonating device 300, and then Step H9 is performed; if not received, the deferred device 300 is internally written with the deferred error flag inside the detonator 300, and then step H10 is performed;

[336] Step H9, decrementing the value of the number of electronic detonators for the deferred error during the period by 1, as the new value, ie = -1;

[337] Step H10, the value of the number of electronic detonators R to be deferred is decremented by 1, as the value of the new R, ie R=R-1

[338] Step Hl l, determine whether the value of R is 0: If it is 0, proceed to step H12; if not, return to step H2;

[339] Step H12, Ending the detonation device writes the deferred process.

[340] In the above-described detonating device 吋 clock calibration process shown in FIG. 12, the cesium clock calibration command 2 sent to an electronic detonator in step G5 is a single command for the electronic detonator. The command is composed of a preset number of m synchronous learning heads, a clock calibration command word and an identity code of the electronic detonator, as shown in FIG. After the detonating device 300 sends the cuckoo clock calibration command 2 to the electronic detonator 400, it waits for the electronic detonator 400 to return according to the high and low width of the preset upper calibration pulse and the preset number of cycles of the upper calibration pulse. Calibrate the waveform on the top. In conjunction with the operating principle of the slave data modulation module disclosed in the patent application document 200810172410.9, the electronic detonator 400 transmits the above-mentioned up-calibration waveform to the detonating device 300 in a manner that consumes current. After receiving the pair of upper calibration waveforms, the detonating device 300 calculates the chopping frequency f _{B of} the detonator 400. Process inch between detonating device 13 shown in FIG deferred write control module 301 to adjust the flow of data between the extension inch detonating device according to the clock frequency inch performed, among the adjustment should be written to give the detonator 400 inch Extended data D _f. Electronics After detonator control chip 200 receives data delayed inches between D _f, D _f need the data written directly to the interior of the extension module chip 200 programmable to 281. The principle of calculating the detonator chirp frequency f _B in the detonating device 300 is the same as the calculation performed inside the chip 200. The calculation of the chopping clock frequency in the detonating device 300 is advantageous for simplifying the design of the electronic detonator control chip 200.

[341] In the detonation device write deferral process shown in FIG. 13, the write deferral inter-turn instruction sent in step H7 is the same as the write deferred inter-turn instruction sent in step F6, as shown in FIG. The difference is that the deferred inter-day data in the write deferred inter-turn instruction sent in step H7 is the deferred inter-day data D _f obtained after the detonating device delays the diurnal data adjustment process.

[342] The deteriorating device deferred data adjustment process in step H6 can be performed according to the following principle: Since the original deferred data 13⁄4 stored in the detonating device 300 is based on the preset chopping frequency of the electronic detonator 400 (denoted as f _Q ) Calculated, the data D _Q expresses the value of D _Q /f _Q , and the electronic detonator control chip is calculated according to the chirp clock frequency f _B calculated by the detonating device chirp clock calibration process shown in FIG. The deferred diurnal data D _{f of} 200 should satisfy: D _Q /f _Q =D _f /f _B . Therefore, the adjusted deferred data D _f can be obtained according to the following formula _:

[343] D _f = D ₀ xf _B / f ₀

[344] The detonating device deferred setting process of the present invention can also be carried out according to the following second technical solution, as shown in FIG.

[345] Step L1, initializing the deferred device deferral setting process, that is, the total number of electronic detonators of the variable blasting network N, the number of erroneous electronic detonators of the 吋 calibration, the delay of the number of electronic detonators E ₂ and the cycle The initial value of the number of times W is stored in the buffer of the control module 301 for use; wherein, the value of the number of false calibration electronic detonators and the value of the electronic detonator number E ₂ during the write delay period are equal to the total number of electronic detonators of the blasting network N value;

[346] Step L2, determining whether the value of the cycle number W and the value of the E ₂ is 0: If the value of the value of W or the value of 0, then continue to perform step L5; otherwise continue to perform step L3;

[347] Step L3, the control module 301 performs a detonation device delay setting process;

[348] Step L4, the value of the number of cycles W is decreased by 1, as the value of the new W, that is, W=W-1; then returns to step L2;

[349] Step L5, the control module 301 outputs a list of error information to the human-machine interaction module 302, which is displayed by the human-machine interaction module 302. [350] Step L6, ending the deferred setting process of the detonating device.

[351] In the above scheme shown in Fig. 14, if all the detonators 400 in the network have successfully completed the setting of the deferred period, the detonation device is terminated. In addition, if the number of cycles has been completed and the detonation device delays the execution of the setting process, the cycle is terminated regardless of whether or not the detonator has been unsuccessfully set, and the error message list is output to the operator. Design variable cycle number W By controlling the number of runs of step L3, the execution of the detonation device delay setting process can be performed automatically by executing the detonation device deferred setting process, and the operation steps can be simplified as well.

[352] In the deferred device deferred setting process shown in Figure 14, step L3 can be performed as follows, as shown in Figure 15:

[353] Step Ml, the value of the set deferred electronic detonator S is set to the value of the number of electronic detonators of the 吋 calibration error, ie S=E!;

[354] Step M2, reading an identity code of an electronic detonator 400 stored in the detonating device 300 in the blasting network;

[355] Step M3, reading state information of the electronic detonator 400 stored in the detonating device 300;

[356] Step M4, determining whether the electronic detonator 400 is in a deferred state according to the status information of the detonator: if the deferred state is set, proceed to step M15; otherwise, proceed to step M5;

[357] Step M5, sending a chime calibration command 2 to the electronic detonator 400;

[358] Step M6, the control module 301 performs a signal receiving process: if the upper calibration waveform returned by the electronic detonator 400 is received, the clock calibration success flag is set in the electronic detonator 400 inside the detonating device 300, and then step M7 is performed. If not received, the electronic detonator 400 is set inside the detonator 300 calibration error flag, and then step M15;

[359] Step M7, decrement the value of the number of false calibration electronic detonators by 1 as the new value, ie = -1

[360] Step M8, the control module 301 counts the preset up-pair calibration pulse number in the upper calibration waveform 3⁄4 the upper calibration pulse of the preset period T _D , and the count value is recorded as F _{B ;}

[361] Step M9, according to the n _D, _D and F _B values of the T, the calculation of the electronic detonator 400 inch clock frequency f _B;

[362] Step M10, reading the deferred data of the electronic detonator 400 stored in the detonating device 300; [363] Step Mi l, performing the detonating device delay diurnal data adjustment process, according to the chopping clock frequency f _B Value is calculated The new extension inch between the value of the data D _f;

[364] Step M12, transmitting, to the electronic detonator 400, a write delay inter-turn instruction including the D _f ;

[365] Step M13, the control module 301 performs a signal receiving process: if the write delay period completion signal returned by the electronic detonator 400 is received, the electronic detonator 400 is internally written with the deferred success sign in the detonating device 300, and then Step M14 is performed; if not received, the electronic detonator 400 is internally written with an deferred error flag inside the detonating device 300, and then step M15 is performed;

[366] Step M14, the value of the number of electronic detonators that delays the deferred error is decremented by 1, as a new value, ie

=E ₂ -1 ;

[367] Step M15, the value of the number of deferred electronic detonators S to be set is decreased by 1, as the value of the new S, that is, S=S-1;

[368] Step M16, determining whether the value of S is 0: If it is 0, proceed to step M17; if not, return to step M2;

[369] Step M17, the process of deferring the detonation device is terminated.

[370] In the process of delay setting of the detonating device shown in FIG. 15 above, all the electronic detonators in the blasting network are completed one by one by performing a cesium clock calibration on an electronic detonator and then writing and deferring it. The deferred setting of 400. This omits the storage of the calculated detonator clock frequency, which simplifies the design.

[371] In the degenerative setting process shown in Fig. 15, the cuckoo clock calibration command 2 sent to an electronic detonator in step M5 is also a single command for the electronic detonator. The instruction is composed of a preset number of m synchronous learning heads, a clock calibration command word and an identity code of the electronic detonator, as shown in FIG.

[372] In the process of delay setting of the detonating device shown in FIG. 15, the write deferral inter-turn command sent to an electronic detonator in the blasting network in step M12 is a single instruction for the electronic detonator. The instruction is composed of a preset number of m synchronous learning heads, a write deferred inter-turn command word, an identity code of the electronic detonator, and deferred inter-day data of the electronic detonator, as shown in FIG. The deferred inter-day data in the write deferred inter-turn instruction is also the deferred inter-day data D _f obtained after the detonation device delays the diurnal data adjustment process.

[373] The signal receiving process in the above control processes can be carried out by referring to the technical solution disclosed in the patent application document 200810135028.0. The specific steps can be described as follows, as shown in FIG.

[374] Step I, calling the preset signal from the control module 301 to receive the super-inter-turn value Τ';

[375] Step Π, the detection control module 301 receives the data from the direction of the electronic detonator, whether it arrives The signal receives the super-inter-turn value τ': if it arrives, the end of the signal receiving process is terminated; if not, the step m is continued;

[376] Step m, detecting whether the control module 301 receives the serial signal sent by the signal conditioning circuit in the signal demodulation receiving module 305: if the serial signal is received, the serial signal is sampled and the electronic device is acquired. The information of the detonator is then returned to step Π; if the serial signal is not received, it returns to step π.

[377]

[378] As another aspect of the technical solution of the present invention, the control flow of the electronic detonator control chip 200 in the electronic detonator 400 can be performed according to the following steps, as shown in FIG. 20:

[379] Step Ν 1, the central processing unit 285 inside the chip 200 sends a control signal to the programmable delay module 281, so that the programmable delay module 281 outputs a signal, so that the ignition control circuit 202 is disconnected, and the ignition state is prohibited;

[380] Step Ν2, the central processing unit 285 reads the identity code of the electronic detonator 400 stored in the non-volatile memory 205;

[381] Step Ν3, the central processing unit 285 waits to receive the synchronous learning header sent by the electronic detonator detonating device 300: if received, proceeds to step Ν4; if not, continues to wait for reception;

[382] Step Ν4, the central processing unit 285 performs a synchronous learning process, and according to the received synchronous learning header, adjusts the number of clocks of the RC oscillator to be written into the prescaler 284, and the number of the clocks is the same Set the communication baud rate to correspond to the preset sample phase;

[383] Step Ν5, the central processing unit 285 waits to receive the command word sent by the electronic detonator detonating device 300: If the cuckoo clock calibration command word is received, enter the cuckoo clock calibration state, proceed to step Ν6; if the status readback command is received Word, enter the state readback state, continue to step Ν7; If the write delay period command word is received, enter the write delay period, continue to step Ν8; if the ignition command word is received, enter the ignition state, continue Carry out step Ν9;

[384] Step Ν6, perform the electronic detonator clock calibration process; then return to step Ν5;

[385] Step Ν 7, performing an electronic detonator status readback process; then returning to step Ν 5;

[386] Step Ν 8, perform an electronic detonator write deferral process; then return to step Ν 5;

[387] Step Ν9, performing an electronic detonator ignition process;

[388] Step Ν10, End this electronic detonator control process. [389] The control flow shown in FIG. 20 above achieves external on-line controllability of the chop clock calibration process, state readback process, write deferral process, and ignition process for the electronic detonator 400. details as follows:

[390] First, the electronic detonator detonating device 300 uses its own precise cuckoo clock to use the online command to perform the chopping clock calibration method to ensure the delay accuracy of the electronic detonator detonating network. The electronic detonator control chip 200 is calibrated to avoid the delay accuracy caused by factors such as temperature drift, drift, and parameter changes of the RC oscillator.

[391] Second, the electronic detonator detonating device 300 uses the electronic detonator state readback process to realize the readback of the chopping clock calibration state, the writing delay period, and other state information of the electronic detonator 400, thereby more reliably controlling the detonator. 400 work.

[392] Third, the above-mentioned electronic detonator detonating device 300 uses the electronic detonator to write the deferred inter-day process to realize the online setting of the deferred time of the electronic detonator 400. Further, the adjusted delayed inter-turn data may be written into the electronic detonator 400 according to the result of the electronic detonator clock calibration process, that is, the obtained accurate information of the electronic detonator. This increases the flexibility of use of the electronic detonator 400.

[393] Fourth, the above-mentioned electronic detonator detonating device 300 utilizes the electronic detonator ignition process to realize the control of the electronic detonator ignition process, so that the ignition is more reliable.

[394] In the electronic detonator control flow shown in FIG. 20 above, the synchronous learning process of step N4 is performed according to the following steps, as shown in FIG. 21:

[395] Step 01, the central processing unit 285 monitors whether the edge signal sent by the electronic detonator detonating device 300 is received: if it is received, proceed to step 02; if not, continue to monitor and wait for receiving;

[396] Step 02, sending a control signal to the counter 287, starting the counter 287;

[397] Step 03, the central processing unit 285 monitors whether another edge signal sent by the electronic detonator detonating device 300 is received: if received, proceed to step 04; if not, continue monitoring;

[398] Step 04, the central processing unit 285 reads the count value of the counter 287 at this moment, and saves the count value.

[399] Step 05, the central processing unit 285 determines whether the number of received edge signals reaches twice the preset number m of the synchronous learning head, that is, determines whether 2 m edge signals are received: if 2 m is received For the edge signal, proceed to step 06; if not, return to step 03;

[400] Step 06, sending a control signal to the counter 287, stopping the counter 287; [401] Step 07, the central processing unit 285 calculates the number of clocks of the RC oscillator that should be written into the prescaler 284 according to the count values stored in its internal buffer, and the number of clocks is communicated with the preset. The baud rate corresponds to the preset sample phase;

[402] Step 08, writing the value of the number of clocks into the prescaler 284;

[403] Step 09, End this synchronous learning process.

[404] The synchronous learning process shown in Fig. 21 above eliminates the influence of the frequency dispersion of the RC oscillator integrated in the chip 200 on the reliability of electronic detonator data reception. The electronic detonator detonating device 300 sends a command to the chip 200, and sends a preset number m synchronous learning heads before sending the command word, see the composition of the instructions shown in Figs. Inside the chip 200, when the edge signal of the synchronous learning head is received, the counter 287 inside the boot chip 200 counts the number of synchronous learning heads, since each synchronous learning head has a rising edge and a falling edge, Therefore, when 2m edge signals are received, m sync learning headers are received. After the synchronization learning head is received, the central processing unit 285 calculates the number of RC oscillators that the serial communication interface 283 should use corresponding to the preset communication baud rate and the preset sampling phase, thereby The data reception downtime and counting interval of the electronic detonator 400 are adjusted. This ensures that even if the RC oscillator has problems such as temperature drift, drift, parameter variation, etc., the electronic detonator control chip 200 incorporating the RC oscillator 210 can reliably receive the control command sent from the electronic detonator detonating device 300.

[405] In the electronic detonator control flow shown in Fig. 20, the implementation of the electronic detonator clock calibration process in step N6 can be performed as follows, as shown in Fig. 22:

[406] Step P1, the central processing unit 285 monitors whether the edge signal sent by the electronic detonator detonating device 300 is received: if received, proceeds to step P2; if not, continues to monitor waiting for reception;

[407] Step P2, sending a control signal to the counter 287, starting the counter 287;

[408] Step P3, monitoring whether the edge signal sent by the electronic detonator detonating device 300 is received: if it is received, proceeding to step P4; if not, continuing to monitor and waiting for reception;

[409] Step P4, reading the count value of the counter 287 at this time, and saving the count value to the cache inside the central processor 285;

[410] Step P5, the central processing unit 285 determines whether the number of received edge signals reaches twice the preset number of lower calibration pulses 3⁄4, that is, determines whether 2n _B edge signals are received: if 2n _B are received Edge signal, proceed to step P6; if not, return to step P3; [411] Step P6, send a control signal to the counter 287, stop the counter 287;

[412] Step P7, the central processing unit 285 presets the number of the next calibration pulses according to the count values in the counter 287.

3⁄4, and the preset period T _{B of} the pair of lower calibration pulses, calculating the value of the chopping clock frequency f _D of the RC oscillator 210; [413] Step P8, the central processing unit 285 sets its internal cuckoo clock calibration flag to Calibration status

[414] Step P9, ending the calibration process of the electronic detonator clock.

[415] In the electronic detonator clock calibration process shown in FIG. 22, the electronic detonator detonating device 300 sends a cuckoo clock calibration command to all the electronic detonators ₄₀₀ in the blasting network, that is, the cuckoo clock calibration command sent in the step C1. One. The command is a global command for all electronic detonators 400 in the blasting network, and in addition to the synchronous learning head and the cesium clock calibration command word, there is a preset period of the preset calibration pulse number of 3⁄4 preset cycles. The lower calibration waveform formed by the lower calibration pulse of T _B is as shown in FIG. The detonating device 300 transmits the above-mentioned sub-calibration waveform by its own stable and accurate cuckoo clock source, and the counter 287 inside the chip 200 performs segmentation counting on the waveform. The central processing unit 285 inside the chip 200 calculates the chirp clock frequency f _{D of the} chip's own RC oscillator 210 according to the count values, the preset number of the lower calibration pulses, and the preset period T _B of the lower calibration pulse. Referring to FIG. 29, the calculation result is stored inside the chip 200. Due to problems such as temperature drift, drift, and parameter changes of the RC oscillator, there may be individual differences in the chirp frequencies of the electronic detonator control chips 200 in the blasting network. Therefore, a uniform, stable and accurate electronic detonator detonating device 300 is used. The 吋 clock source calibrates the cesium clock of the chip 200, which is beneficial to eliminate the influence of the existence of individual differences on the delay precision of the blasting network, and improve the delay precision of the blasting network.

[416] The above calculation principle of the chopping clock frequency f _D can be described as follows:

[417] The count value N (N=N[1] of the number of 吋 clocks inside the chip for the diurnal n'xT _B ( _n '=l, 2, 3,..., n _B ) expressed by the lower calibration waveform. , N[2], N[3], ..., N[2n _B ] ), inversely proportional to the 吋 oscillator period 1/f of the RC oscillator 210, that is, proportional to the 吋 oscillator frequency 210 of the RC oscillator 210 , then there is n'xT _B = N/f, so: f = N / (n'xT _B ). Wherein the stored various count values 1 ^^ = ^ 1], ^ 2], ^ 3] ..., ^ 2 ¾]) of access, should preclude the use of computing inch pulse of the calibration The value of the number of cycles n' corresponds. Taking the lower calibration pulse of the first cycle of the chop clock calibration command shown in FIG. 10 as an example, when the edge signal 1吋 is received, the counter 287 is activated; when the edge signal 2吋 is received, the count of the engraving is read. The value N[l] is saved; when the edge signal is received 3吋, the count value N[2] of this engraving is read and saved, and the reception and counting of the lower calibration pulse by the first period are completed. In calculating the 吋 clock frequency 吋, the number of cycles n' should be taken as 1, and the count value N should be taken as N[2]. So on and so forth. In reality In order to improve the accuracy of the calculated chopping clock frequency, the values of several chopping clock frequencies can be calculated in stages to obtain an average of the chopping clock frequency f _D . The segmentation method may use a method of calculating a chop clock frequency at intervals of several cycles, or other methods based on this principle.

[418] Corresponding to Embodiment 1 of the electronic detonator clock calibration process shown in FIG. 22, in the electronic detonator control flow, the electronic detonator state readback process in step N7 can be performed according to the following steps, as shown in FIG. :

[419] Step R1, the central processing unit 285 determines whether to perform status readback on the detonator according to the identity code of the detonator in the status readback instruction: if the status code of the detonator in the status readback instruction and the identity read in step N2 If the code matches, step R2 is performed; if not, step R3 is performed;

[420] Step R2, the central processing unit 285 sends the status information of the detonator to the electronic detonator detonating device 300;

[421] Step R3, ending the electronic detonator status readback process.

[422] In the electronic detonator state readback process illustrated in Figure 24, the electronic detonator detonator 300 sends a status readback command to an electronic detonator in the blasting network as a single command for the electronic detonator. The instruction includes the identity code of the corresponding electronic detonator in addition to the synchronous learning head and the status readback command word as described above, as shown in FIG. The design of the process enables the electronic detonator detonating device 300 to acquire the state of the electronic detonator, thereby enabling the device to more reliably control the operation of the detonator 400. After receiving the status readback command, the electronic detonator 400 determines whether the identity code in the instruction matches its own identity code: if it matches, returns its own status information to the detonating device 300, including whether it has been calibrated, whether the extension has been written. The information is used for the detonating device 300 to more reliably control the operation of the detonator 400; if not, it is deemed that the state information of the detonator 400 is not required to be obtained, and no operation is performed.

[423] Corresponding to Embodiment 1 of the electronic detonator clock calibration process shown in FIG. 22, in the above-described electronic detonator control flow, the electronic detonator writing delay period in step N8 can be performed according to the following steps, as shown in FIG. 25 Shown as follows:

[424] Step S1, the central processing unit 285 determines whether to write the extension of the detonator according to the identity code of the detonator in the deferred inter-turn instruction: if the ID code of the detonator in the deferred inter-turn instruction is read and read out in step N2 If the identity code matches, proceed to step S2; if not, terminate the electronic detonator write deferral process;

[425] Step S2, performing an electronic detonator delay diurnal data adjustment process according to the deferred diurnal data D _{Q in} the write deferred inter-turn instruction, and obtaining the adjusted deferred diurnal data D _{N ;} [426] Step S3, the adjusted deferred data D _{N is} written into the programmable delay module 281;

[427] Step S4, the central processing unit 285 sets the internal deferred time setting flag to the set deferred state; the central processing unit 285 sends a write deferral completion signal to the electronic detonator detonating device 300;

[428] Step S5, ending the electronic detonator writing deferral process.

[429] In the electronic detonator writing delay period shown in FIG. 25, the electronic detonator detonating device 300 sends a deferred inter-turn instruction to an electronic detonator in the blasting network, that is, the instruction sent by the detonating device 300 in step F6. . The instruction is a single instruction for the electronic detonator. The instruction includes the identity code of the corresponding electronic detonator and the deferred inter-day data D _Q as shown in FIG. 17 in addition to the synchronous learning header and the write-delay inter-duration command word described above. After receiving the deferred data D _Q sent by the electronic detonator detonating device 300, the central processing unit 285 firstly performs the result of the electronic detonator clock calibration process shown in FIG. 23, that is, the calculated chirp frequency f of the local detonator 400. _D. Perform an electronic detonator deferred data adjustment process to calculate a new deferred daytime data DN _; then, the adjusted deferred inter-day data 126 is written into the programmable delay module 281. This achieves an on-line setting of the deferred time of the electronic detonator 400, thereby increasing the flexibility of use of the electronic detonator 400. Moreover, the 吋clock frequency f _D calculated by the electronic detonator 校准 calibration process is adjusted to the deferred data 126 sent by the electronic detonator detonating device 300 and then written to the programmable delay module 281, which also ensures the electronic detonator 400 delay accuracy.

[430] The above-mentioned electronic detonator deferred data adjustment process can be carried out according to the following principle: Since the deferred inter-day data in the write-delay inter-turn instruction is calculated according to the preset chirp frequency (denoted as f _Q ) of the electronic detonator 400 , the mean value of the expression is D _Q /f _Q ; then the deferred inter-day data should be written to the programmable delay module 281 based on the chopping clock frequency f _D calculated by the electronic detonator clock calibration process. Satisfied: Do/f _Q = D _N /f _D . Therefore, the adjusted deferred data D _{N :} D _N = D _Q xf _D / f _Q can be obtained according to the following formula.

[431] In the electronic detonator control flow shown in Figure 20, the implementation of the electronic detonator clock calibration process in step N6 can be performed as follows, as shown in Figure 23:

[432] Step Q1, the value of the number of calibration pulses to be sent is set to a value of a preset number of calibration pulses n _D ,

k=n _D ;

[433] Step Q2, the central processing unit 285 determines whether to perform the calibration of the detonator according to the identity code of the detonator in the calibration command 2: if the identification code of the detonator in the second calibration command is read out in step _N2 If the identity code matches, step Q3 is performed; if not, step Q16 is performed; [434] Step Q3, the central processing unit 285 writes a high-level pre-designed value of the upper calibration pulse to the counter 287;

[435] Step Q4, the central processing unit 285 sends a control signal to the communication interface circuit 203 through the serial communication interface 283, so that the current consumed by the communication interface circuit 203 on the signal bus 500 is increased;

[436] Step Q5, send a control signal to the counter 287, start the counter 287;

[437] Step Q6, the central processing unit 285 monitors whether the pre-designed value u _D is reached _: if yes, proceed to step Q7; if not, continue monitoring to wait for arrival;

[438] Step Q7, sending a control signal to the counter 287, stopping the counter 287;

[439] Step Q8, the central processing unit 285 writes a low-level pre-designed value v _D of the upper calibration pulse to the counter 287 _;

[440] Step Q9, the central processing unit 285 sends a control signal to the communication interface circuit 203 through the serial communication interface 283, so that the current consumed by the communication interface circuit 203 on the signal bus 500 is reduced;

[441] Step Q10, sending a control signal to the counter 287, starting the counter 287;

[442] Step Q11, the central processing unit 285 monitors whether the pre-designed value v _D is reached _: if yes, proceed to step Q12; if not, continue monitoring to wait for arrival;

[443] Step Q12, sending a control signal to the counter 287, stopping the counter 287;

[444] Step Q13, the value of the number k of the upper calibration pulse to be transmitted is decreased by 1, as the value of the new k, gP, k=k-l;

[445] Step Q14, determining whether the value of k is 0: If it is 0, proceed to step Q15; if not, return to step Q3;

[446] Step Q15, the central processing unit 285 positions its internal cuckoo calibration flag to a calibrated state;

[447] Step Q16, End the calibration process of the electronic detonator clock.

[448] In the electronic detonator 吋 calibration process shown in FIG. 23, the 雷校准 calibration command sent by the electronic detonator detonating device 300 to an electronic detonator in the blasting network is sent by the detonating device 300 in the step G5 or the step M5. The 吋 clock calibration instruction II. The instruction is a single instruction, and includes the identity code of the corresponding electronic detonator, in addition to the synchronous learning head and the clock calibration command word described above, as shown in FIG. After receiving the cuckoo clock calibration command 2, the detonator 400 follows the preset high and low level widths u _D and v _D of the upper calibration pulse and the preset number of cycles of the upper calibration pulse n _D to the electronic detonator detonating device 300. Send the pair of calibration waveforms. After the electronic detonator detonating device 300 receives the pair of calibration waveforms, the radar is calculated. The chopping clock frequency f _{B of the} tube 400 is adjusted according to the chopping clock frequency f _B and the initial deferred diurnal data D _Q corresponding to the detonator to obtain new deferred diurnal data D _f to be written into the detonator. The detonating device 300 can adjust the deferred data of the detonator immediately after the completion of the chopping clock calibration, or save the value of the chopping clock frequency first, and then wait for the extension of the detonator to perform the deferred data adjustment. .

[449] On-line calibration of the RC oscillator 210 is accomplished by performing the electronic detonator chime calibration process illustrated in FIG. The implementation of the electronic detonator clock calibration process shown in FIG. 23 is compared with the embodiment shown in FIG. 22. On the one hand, the central processing unit 285 inside the detonator 400 does not need to have complicated calculation functions, thereby simplifying the logic design of the chip 200. On the other hand, since the adjustment process for the deferred time is performed in the electronic detonator detonating device 300, the deferral accuracy of the detonator 400 can be flexibly adjusted according to the actual application requirements of the blasting engineering, which also improves the electronic detonator 400 in different delays. Adaptability under accuracy requirements.

[450] In the above-described electronic detonator clock calibration process shown in FIG. 23, a preferred solution is: the value of the low-level width pre-designed value v _D in the upper calibration pulse is greater than the value of the high-level width pre-designed value. And, the sum of the value of the low-level width pre-designed value v _{D and} the value of the high-level width pre-designed value is equal to the preset period T _D of the upper calibration pulse, as shown in FIGS. 27 and 28. The benefits are:

[451] 1. Since the electronic detonator 400 transmits data to the electronic detonator detonating device 300 in a current consumption manner, and the calibration pulse high level signal in the transmitting pair, the current consumption increases, thereby consuming the electronic detonator detonating device 300. More energy. Therefore, reducing the width of the high level signal can reduce the energy consumption of the electronic detonator detonating device 300 during the cesium clock calibration.

[452] 2. At the transmitting pair calibration pulse high level signal, the input terminal of the rectifier bridge circuit 201 in the electronic detonator control chip 200 is in a short circuit state. Thus, not only will the charging process to the external energy storage device 600 of the chip 200 cease, but the digital logic circuitry internal to the chip 200 will also consume energy in the energy storage device 600. When the upper calibration signal low level signal is transmitted, the input end of the rectifier bridge circuit 201 is in an open state, and the energy storage device 600 outside the chip 200 can be continuously charged. Therefore, by reducing the calibration pulse high-level width pre-design value u _D and increasing the calibration pulse low-level width pre-design value v _D , the waveform of the energy storage device 600 can be reduced in the transmission pair calibration waveform 吋. The consumption can increase the supplemental energy of the energy storage device 600, which improves the operational reliability of the electronic detonator control chip 200, reduces the current noise of the blasting network bus, and improves the stability of the blasting network.

[453] Corresponding to the embodiment of the electronic detonator chime calibration process shown in FIG. 23, the electron shown in FIG. 20 above In the detonator control process, the electronic detonator write deferral process in step N8 can be performed as follows, as shown in Figure 26:

[454] Step T1, the central processing unit 285 determines whether to write the extension of the detonator according to the identity code of the detonator in the deferred inter-turn instruction; if the ID code of the detonator in the deferred inter-turn instruction and the step Ν2 are read out If the identity code matches, proceed to step Τ2; if not, end the electronic detonator write deferral process;

[455] Step Τ2, the central processing unit 285 writes the deferred inter-day data D _f in the write deferred inter-turn instruction to the programmable extension module 281;

[456] Step T3, the central processing unit 285 sets the internal deferred time setting flag to the set deferred state; the central processing unit 285 sends a write deferral completion signal to the electronic detonator detonating device 300;

[457] Step Τ4, End the electronic detonator write deferral process.

[458] Corresponding to the embodiment of the electronic detonator clock calibration process shown in FIG. 23, since the process of adjusting the deferred data is performed in the electronic detonator detonating device 300, for the chip 200, only The deferred inter-day data D _f in the write deferred inter-turn instruction can be written into the programmable module 281. This eliminates the need to design an arithmetic logic unit in the central processor 285 of the chip 200, greatly simplifying the design of the chip 200.

[459] In the electronic detonator control flow shown in Fig. 20, the electronic detonator ignition process of step N9 is similar to the ignition process disclosed in the patent application document 20 0810211374.2. Gp, first, the central processing unit 285 sends a control signal to the programmable delay module 281 to start the programmable delay module 281; then, the central processing unit 285 waits for the delay to arrive, and if it reaches the deferred time, continues, if not, then Continuing to wait; Finally, the programmable delay module 281 outputs a signal to the ignition control circuit 202 such that the ignition control circuit 202 is closed and is in an ignition state. At this point, the ignition of the detonator 400 is completed.

Claims

Claim

[Claim 1] 1. An detonating device deferred setting process in an electronic detonator detonating system, the system consisting of an initiating device and one or more electronic detonators, one or more of the electronic detonators being connected in parallel The detonating device includes a control module, a human-machine interaction module, a power management module, a signal modulation transmitting module, a signal demodulation receiving module, and a power supply, and the control module includes a central processing unit and A fixed device, which is characterized by:

The detonating device deferred setting process is performed according to the following steps.

Step A, performing a calibration process of the detonating device 吋 clock;

Step A2, executing the detonating device to write the deferred process;

Step A3, outputting a list of error information to the human-computer interaction module, which is displayed by the human-machine interaction module;

Step A4, ending the deferred setting process of the detonating device.

2. The deferred device deferral setting process according to claim 1, wherein:

The step A1 is performed according to the following steps.

Step Bl, the total number of the variable electronic detonator blasting network N, the number of electrons inch clock error calibration cycles detonators _El and the initial value stored in the buffer control module stand; wherein the value of the acquired N The same value;

Step B2, the control module determines whether the value of the number of loops and the value are 0: if the value or the value is 0, the end of the detonating device is completed; otherwise, the step is continued. B3;

Step B3, performing a calibration process of the detonating device;

In step B4, the value is decremented by 1 as the value of the new ^, ie, \¥ ₁ =\¥ ₁ -1; and then the step B2 is returned.

3. The deferred device deferral setting process according to claim 2, wherein:

The step B3 is performed according to the following steps. Step CI, the control module sends a chime calibration command one to the electronic detonators in the blasting network;

Step C2, the control module waits to reach the preset delay interval ^: if it arrives, proceeds to step C3; if not, continues to wait for arrival;

Step C3, the value of the number L of the electronic detonator to be calibrated is the value, that is, L=; Step C4, reading the identity code of an electronic detonator in the blasting network stored in the detonating device;

Step C5, reading the status information of the electronic detonator stored in the detonating device, step C6, determining whether the electronic detonator is in a calibrated state according to the status information of the detonator: if it is in a calibrated state, performing steps C13; If it is not calibrated, proceed to step C7;

Step C7, sending a status readback instruction to the electronic detonator;

Step C8, the control module performs a signal receiving process: if receiving the information returned by the electronic detonator, proceeding to step C9; if not, performing step C12; step C9, the control module saves the electronic detonator returning Information, and determine whether the electronic calibration signal of the electronic detonator is in a calibrated state: if it is a calibrated state, step C10 is performed; if it is an uncalibrated state, step C12 is performed;

Step C10, setting the clock calibration success flag to the electronic detonator inside the detonating device, step C11, reducing the value by 1, as a new value, that is, = -1; then proceeding to step C13;

Step C12, setting a clock calibration error flag to the electronic detonator inside the detonating device; and then performing step C13;

Step C13, reducing the value of L by 1, as the value of the new L, that is, L=L-1;

Step C14, determining whether the value of the L is 0: If it is 0, proceeding to step C15

If not 0, return to step C4;

Step C15, ending the calibration process of the detonating device.

4. The deferred device deferral setting process according to claim 3, characterized in that:

The clock calibration command is composed of a preset number of m synchronous learning heads, a clock calibration command word and a lower calibration waveform;

The lower calibration waveform is composed of a preset pair of lower calibration pulses 3⁄4 of a pair of lower calibration pulses of a preset period T _B .

5. The deferred device deferral setting process according to claim 4, wherein:

The pair of lower calibration waveforms are sent by the control module to perform the following detonating device calibration waveform sending process,

Step D1, the value of the number of the lower calibration pulses to be sent is set to a value of the preset pair of lower calibration pulses 3⁄4, that is, n=n _{B ;}

Step D2, writing a low-level preset value v _B of the lower calibration pulse to the fixed device;

Step D3, sending a control signal to the signal modulation transmitting module to output a falling edge signal;

Step D4, sending a control signal to the fixed device to start the fixed device; Step D5, the central processor monitors whether the length of the low-level signal output by the signal modulation transmitting module reaches the low battery Flat width preset value v _{B :} If it arrives, proceed to step D6; if it does not arrive, continue monitoring and wait for arrival;

Step D6, sending a control signal to the fixed device to stop the fixed device; Step D7, writing a high-level preset value of the lower calibration pulse to the fixed device 3⁄4;

Step D8, sending a control signal to the signal modulation and transmitting module to output a rising edge signal;

Step D9, sending a control signal to the fixed device to start the fixed device; Step D10, the central processor monitors whether the length of the high level signal output by the signal modulation transmitting module reaches the high power Flat width preset _{3⁄4 :} if it arrives, then Go to step Dl l; if it does not arrive, continue to monitor and wait for arrival;

Step D11, sending a control signal to the fixed device to stop the fixed device; Step D12, decrementing the value of the number n of the lower calibration pulse to be transmitted as a new value of n, that is, n= Nl ;

Step D13, determining whether the value of n is 0: if it is 0, proceed to step D14; if not, return to step D2;

Step D14, ending the sending process of the calibration waveform of the detonating device.

6. The deferred device deferral setting process according to claim 5, characterized in that:

The value of the value of 3⁄4 is greater than the value of the v _B ;

The sum of the value of the 3⁄4 and the value of the v _B is equal to the T _B .

7. The deferred device deferral setting process according to claim 3, characterized in that:

The status readback instruction is sequentially composed of a preset number m of the synchronous learning head, a status readback command word, and an identity code of the electronic detonator.

8. The deferred device deferral setting process according to claim 2, wherein:

The step B3 is performed according to the following steps.

Step G1, the value of the number of electronic detonators to be calibrated is the value of the number of electronic detonators of the calibration clock, that is, L=;

Step G2, reading an identity code of an electronic detonator in the blasting network stored in the detonating device;

Step G3, reading the status information of the electronic detonator stored in the detonating device, step G4, determining whether the electronic detonator is in a calibrated state according to the status information of the detonator: if it is in a calibrated state, performing steps G12; If it is not calibrated, proceed to step G5;

Step G5, sending a chime calibration instruction two to the electronic detonator; Step G6, the control module performs a signal receiving process: if receiving the upward calibration waveform returned by the electronic detonator, performing step G7; if not, setting the chirp calibration of the electronic detonator inside the detonating device The error flag is then executed in step G12, step G7, and the electronic detonator is placed inside the detonating device with a clock calibration success flag step G8, and the value is decremented by 1 as a new value, ie, -1; step G9 And counting, on the upper calibration waveform, a preset number of upper calibration pulses n _D preset calibration pulses having a preset period T _D , and the count value is recorded as F _{B ;}

Step G10, based on the value of n _D, the T _D F _B and the calculating of the electronic detonator inch clock frequency f _B;

Step Gi l , storing the cuckoo clock information of the electronic detonator, where the cuckoo clock information includes the value of the chopping clock frequency;

Step G12, reducing the value of L by 1, as the value of the new L, that is, L=L-1;

Step G13, determining whether the value of L is 0: If it is 0, proceed to step G14; if not, return to step G2;

Step G14, ending the calibration process of the detonating device.

9. The deferred device deferral setting process according to claim 1, wherein:

The step A2 is performed according to the following steps.

In step E1, the initial value of the total number of electronic detonators of the variable blasting network, the number of electronic detonators E ₂ and the number of cycles W ₂ of the deferred network are stored in the buffer of the control module for use; wherein the value is obtained Same as the value of N;

Step E2, the control module determines whether the value of the cycle number W _{2 and} the value of the E ₂ is 0: if the value of the W ₂ or the value of the E ₂ is 0, step E5 is performed; Continue to step E3;

Step E3, executing the detonating device to write the deferred process;

In step E4, the value of the W ₂ is decremented by 1 as the value of the new \¥ ₂ , that is, \¥ ₂ =\¥ ₂ -1; Then return to the step E2;

Step E5, ending the detonation process of the detonating device.

10. The deferred device deferral setting process according to claim 9, wherein:

The step E3 is performed according to the following steps.

Step F1, the value of the number of electronic detonators R to be written in the deferred period is the value of the number of electronic detonators E ₂ in the write delay period, that is, R=E ₂ ;

Step F2, reading an identity code of an electronic detonator in the blasting network stored in the detonating device;

Step F3, reading the status information of the electronic detonator stored in the detonating device, step F4, determining whether the electronic detonator is in a calibrated state according to the status information of the detonator: if it is in an uncalibrated state, performing steps F8; if it is in the calibrated state, proceed to step F5;

Step F5, reading the deferred data D _{Q of} the electronic detonator stored in the detonating device _;

Step F6, sending a write delay period instruction including the 13⁄4 to the electronic detonator; Step F7, the control module performs a signal receiving process:

Receiving a write delay period completion signal returned by the electronic detonator, writing an extension diurnal success flag to the electronic detonator inside the detonator; and then decrementing the value by 1 as a new value, ie = -1;

If not received, the electronic detonator is internally written with an extension of the daytime error flag inside the detonating device;

Step F8, the value of the R is decreased by 1, as the value of the new R, that is, R=R-1;

Step F9, determining whether the value of R is 0: If it is 0, proceed to step F10; if not, return to step F2;

Step F10, ending the detonation process of the detonating device.

11. The deferred device deferral setting process according to claim 9, characterized in that In:

The step E3 is performed according to the following steps.

Step H1, the value of the number of electronic detonators R to be written in the deferred period is the value of the number of electronic detonators E ₂ in the write delay period, that is, R=E ₂ ;

Step H2, reading an identity code of an electronic detonator in the blasting network stored in the detonating device;

Step H3, reading the status information of the electronic detonator stored in the detonating device, step H4, determining whether the electronic detonator is in a calibrated state according to the status information of the detonator: if it is in an uncalibrated state, performing steps H9; If it is in the calibrated state, proceed to step H5;

Step H5, reading the deferred data D _{Q of} the electronic detonator stored in the detonating device; reading the value of the chopping clock frequency f _B of the electronic detonator stored in the control module;

Step H6, detonating device performing data alignment process between extension inch, calculates a new extension inch between the data D _f inches depending on the value of the clock frequency;

Step H7, sending a write delay inter-turn instruction including the D _f to the electronic detonator; Step H8, the control module performs a signal receiving process:

Step H9, reducing the value of the R by 1, as the value of the new R, that is, R=R-1;

Step H10, determining whether the value of R is 0: If it is 0, proceed to step H11; if not, return to step H2;

Step H11, ending the detonation process of writing the detonation device.

12. A deferred device deferred setting process in an electronic detonator detonating system, The system is composed of a detonating device and one or more electronic detonators, and one or more of the electronic detonators are connected in parallel on a signal bus led from the detonating device, the detonating device comprising a control module, a human-computer interaction module, and a power supply a management module, a signal modulation transmitting module, a signal demodulation receiving module, and a power supply, the control module comprising a central processing unit and a fixed device, wherein:

Step Ll, the total number of the variable electronic detonator blasting network N, the number of electrons inch clock alignment errors detonator _El, deferred write errors between the electronic detonator inch number of E ₂ and W cycles of the initial value stored in said cache control module stand Wherein the value and the value are equal to the value of the N;

Step L2, determining whether the value of the cycle number W and the value of the E ₂ is 0: if the value of the W or the value of the E ₂ is 0, proceed to step L5; otherwise continue to perform step L3;

Step L3, the control module executes a detonation device delay setting process;

Step L4, the value of the W is decremented by 1, as the value of the new W, that is, W=W-1; then the step L2 is returned;

Step L5, the control module outputs a list of error information to the human-machine interaction module, which is displayed by the human-machine interaction module;

Step L6, ending the deferred setting process of the detonating device.

13. The deferred device deferral setting process according to claim 12, wherein:

The step L3 is performed according to the following steps.

Step M1, setting the value of the set deferred electronic detonator number S to the value, that is, S=step M2, reading the identity code of an electronic detonator in the blasting network stored in the detonating device;

Step M3, reading the status information of the electronic detonator stored in the detonating device, step M4, determining whether the electronic detonator is set according to the status information of the detonator Deferred state: If the deferred state is set, proceed to step M15; otherwise, proceed to step M5;

Step M5, sending a calibration command 2 to the electronic detonator;

Step M6, the control module performs a signal receiving process:

Receiving a calibration calibration waveform returned by the electronic detonator, setting a clock calibration success flag to the electronic detonator inside the detonating device; and then performing step M7, if not received, the electronic device inside the detonating device Detonator set the clock calibration error flag; then perform step M15;

Step M7, the value is decremented by 1 as a new value, that is, = -1; Step M8, the control module sets a preset period of a preset pair of upper calibration pulses in the pair of upper calibration waveforms as a preset period of the calibration pulse counting T _D, the count value is referred to as a step M9 F _B, according to the value of n _D, the T _D F _B and the calculating of the electronic detonator inch clock frequency f _B;

Step M10, reading the deferred data D _{Q of} the electronic detonator stored in the detonating device _;

Step Mi l , performing a detonation device delay diurnal data adjustment process, and calculating a new deferred diurnal data D _f according to the value of the chopping clock frequency _;

Step M12, transmitted to the electronic detonator comprises an extension inch between the write instruction D _f; a step M13, the control module performs the signal receiving process:

Receiving the deferred period completion signal returned by the electronic detonator, writing an extension diurnal success flag to the electronic detonator inside the detonating device; and then performing step M14;

If not received, the electronic detonator is internally written with an extension of the daytime error flag; and then step M15 is performed;

In step M14, the value of the E ₂ is decremented by 1 as a new value, that is, 5 ₂ = -1; in step M15, the value of the S is decremented by 1, as the value of the new S, that is, S=S- 1 ; Step M16, it is determined whether the value of S is 0: If it is 0, then step M17; if not 0, then return to step M2;

Step M17, ending the detonation device extension setting process.

14. The detonation device delay time setting process according to claim 8 or 13, wherein:

The clock calibration command 2 is composed of a preset number m of the synchronous learning head, the clock calibration command word and an identity code of the electronic detonator.

15. The deferred device deferral setting process according to claim 10, 11 or 13, wherein:

The write delay period instruction is composed of a preset number m of the synchronous learning head, a write delay time command word, an identity code of the electronic detonator, and an extension time data of the electronic detonator.

16. An electronic detonator control flow in an electronic detonator detonation system, the system being comprised of a detonating device and one or more electronic detonators, one or more of the electronic detonators being connected in parallel on a signal bus drawn by the detonating device The electronic detonator includes an electronic detonator control chip; the chip includes a nonvolatile memory, a logic control circuit, and a clock circuit;

The logic control circuit comprises a programmable delay module, an input/output interface, a serial communication interface, a prescaler, a counter and a central processing unit 2, wherein the clock circuit is an RC oscillator,

It is characterized by:

The electronic detonator control process is carried out according to the following steps.

Step N1, the central processor 2 sends a control signal to the programmable delay module, so that the programmable delay module outputs a signal, so that the ignition control circuit is disconnected, and the ignition state is prohibited;

Step N2, the central processor 2 reads an identity code of the electronic detonator stored in the non-volatile memory;

Step N3, the central processing unit 2 waits to receive the electronic detonator detonating device to send

Correction page (Article 91) The synchronous learning head coming: if it is received, proceeding to step N4; if not, continuing to wait for receiving;

Step N4, the central processing unit 2 performs a synchronous learning process;

Step N5, the central processing unit 2 waits to receive the command word sent by the electronic detonator detonating device:

If the clock calibration command word is received, the clock calibration state is entered, and step N6 is continued;

If the status readback command word is received, the status is read back, and step N7 is continued;

If the write delay time command word is received, the write delay period is entered, and step N8 is continued;

If the ignition command word is received, the ignition state is entered, and the process proceeds to step N9; Step N6, the electronic detonator clock calibration process is performed; then, the process returns to the step N5; Step N7, the electronic detonator state readback process is performed; Step N5; Step N8, performing an electronic detonator write deferral process; then returning to step N5; Step N9, performing an electronic detonator ignition process;

Step N10, ending the electronic detonator control process.

The electronic detonator control process according to claim 16, wherein: the step N4 is performed according to the following steps,

Step 01: The central processor 2 monitors whether an edge signal sent by the electronic detonator detonating device is received: if received, step 02 is performed; if not, monitoring continues to be received;

Step 02: Send a control signal to the counter to start the counter; Step 03, the central processor 2 monitors whether an edge signal sent by the electronic detonator detonating device is received: If received, the Becker proceeds to step 04. If it is not received, continue to monitor;

Step 04, the central processor 2 reads the counter value of the counter at this moment, and saves the counter value;

Correction page (Article 91) Step 05: The central processor 2 determines whether the number of the received edge signals reaches twice the preset number m of the synchronous learning head, that is, determines whether 2 m edge signals are received: if received 2m edge signals, proceed to step 06; if not received, return to step 03;

Step 06, sending a control signal to the counter to stop the counter; Step 07, the central processor 2 calculates the RC oscillation written into the prescaler according to the count values stored in its internal buffer The number of clocks of the device, the number of clocks corresponding to the preset communication baud rate and the preset sample phase;

Step 08: Write the number of the clocks into the prescaler;

Step 09, end the synchronization learning process.

18. The electronic detonator control process according to claim 16, wherein: said step N6 is performed according to the following steps.

Step P1, the central processing unit 2 monitors whether the edge signal sent by the electronic detonator detonating device is received: if received, proceed to step P2; if not, continue monitoring;

Step P2, sending a control signal to the counter to start the counter; Step P3, monitoring whether another edge signal sent by the electronic detonator detonating device is received: if received, proceeding to step P4; if not, Then, the monitoring continues; step P4, reading the counter value of the counter at this time, and saving the count value to the internal cache of the central processor 2;

Step P5, the number of the two central processor determines that the received edge signal reaches the preset number of times of the calibration pulse, i.e., determines whether a received edge signal 2¾: Upon receiving the 2 _¾ Step signal P6; if not, return to step P3;

Step P6, sending a control signal to the counter to stop the counter; Step P7, the central processor 2 is based on the count values of the counter, 'the preset pair of lower calibration pulses 3⁄4, and the Presetting the period T _B , calculating a value of the chopping clock frequency f _D of the RC oscillator;

Correction page (Article 91) Step P8, the central processor 2 positions the internal clock calibration flag in its calibrated state;

Step P9, ending the electronic detonator clock calibration process.

19. The electronic detonator control process according to claim 16, wherein: the step N6 is performed according to the following steps.

Step Q1, the value of the number of the upper calibration pulse k to be sent is the value of the preset pair of upper calibration pulses, that is, k=n _D;

Step Q2: The central processor 2 determines whether to perform clock calibration on the detonator according to the identity code of the detonator in the clock calibration instruction 2:

If the identity code of the detonator in the second calibration command 2 matches the identity code read in the step N2, proceed to step Q3;

If not, proceed to step Q16;

Step Q3, the central processor 2 writes the high-level width pre-designed value u _D of the upper calibration pulse to the counter _;

Step Q4, the central processing unit 2 sends a control signal to the communication interface circuit through the serial communication interface, so that the current consumed by the communication interface circuit on the signal bus increases;

Step Q5, sending a control signal to the counter to start the counter; Step Q6, the central processor 2 monitors whether the pre-designed value u _D is reached _: if yes, proceed to step Q7; if not, continue The monitoring waits for the arrival; step Q7, sending a control signal to the counter to stop the counter; step Q8, the central processor 2 writes the low-level width pre-designed value of the upper calibration pulse to the counter v _D;

Step Q9: The central processing unit sends a control signal to the communication interface circuit through the serial communication interface, so that the current consumed by the communication interface circuit on the signal bus is reduced;

Step Q10, sending a control signal to the counter to start the counter; Step Q11, the central processor 2 monitors whether the pre-designed value v _D is reached _:

Front page (91) If yes, proceed to step Q12; if not, continue monitoring to wait for arrival;

Step Q12, sending a control signal to the counter to stop the counter; step Q13, decrementing the value of the number of upper calibration pulses k to be transmitted as a new value of k, that is, k=kl _;

Step Q14, determining whether the value of k is 0: if it is 0, proceed to step Q15; if not, return to step Q3;

Step Q15, the central processor 2 sets its internal clock calibration flag to a calibrated state;

Step Q16, ending the calibration process of the electronic detonator clock.

20. The electronic detonator control flow according to claim 19, wherein: the value of v _D is greater than the value;

The sum of the value of v _D and the value is equal to the T _D .

The electronic detonator control process according to claim 16, wherein: the step N7 is performed according to the following steps,

Step R1, the central processor 2 determines whether to perform status readback of the detonator according to the identity code of the detonator in the status readback instruction:

If the identity code of the detonator in the status readback instruction matches the identity code read in the step N2, proceed to step R2;

If not, proceed to step R3;

Step R2, the central processor 2 sends the status information of the detonator to the electronic detonator detonating device;

Step R3, ending the electronic detonator status readback process.

22. The electronic detonator control flow according to claim 16, wherein: the step N8 is performed according to the following steps,

Step S1, the central processor 2 determines whether to write the extension time to the detonator according to the identity code of the detonator in the write deferral time instruction;

If the identity code of the detonator in the write deferral command is consistent with the identity code read in step N2, proceed to step S2;

Correction page (Article 91) If not, terminate the electronic detonator writing extension time process;

Step S2: Perform an electronic detonator delay diurnal data adjustment process according to the deferred time data in the write deferral time instruction, and obtain the adjusted delay time data D _{N; and} step S3, write the adjusted delay time data D _N The programmable delay module; step S4, the central processor 2 sets the internal delay time setting flag position to the set deferred state; the central processor 2 sends the electronic detonator detonating device to the electronic detonator Write the extension time completion signal;

Step S5, ending the electronic detonator writing deferral process.

23. The electronic detonator control process according to claim 16, wherein: the step N8 is performed according to the following steps,

Step T1, the central processor 2 determines, according to the identity code of the detonator in the write deferral time instruction, whether to write the extension time to the detonator;

If the identity code of the detonator in the write deferral command is consistent with the identity code read in the step N2, proceed to step T2;

If not, the electronic detonator write deferral time process is ended; 'Step T2, the central processor 2 writes the deferred inter-day data in the write deferred inter-turn instruction to the programmable extension module;

Step T3, the central processor 2 sets the internal delay time setting flag position to the set deferred state; the central processor 2 sends the writing delay period to the electronic detonator Signal

Step T4, ending the electronic detonator writing delay time process.

Correction page (Article 91)