WO2010046638A1

WO2010046638A1 - Connected display pixel drive chiplets

Info

Publication number: WO2010046638A1
Application number: PCT/GB2009/002503
Authority: WO
Inventors: Jeremy Burroughes; Stephen Coats; Haydn Gregory; Euan Smith; Julian Carter
Original assignee: Cambridge Display Technology Limited
Priority date: 2008-10-23
Filing date: 2009-10-21
Publication date: 2010-04-29
Also published as: TW201027480A; GB0900627D0; GB2464564B; GB0819448D0; GB2464564A

Abstract

A backplane for an active matrix display comprises a plurality of chiplets for driving pixels, wherein each of the plurality of chiplets is connected logically to another chiplet in a single dimension to form a logical chain, with no orthogonal row connections between chiplets. According to this arrangement, it is not necessary to increase the number of external connections as the number of chiplet elements in a logical chain is increased.

Description

CONNECTED DISPLAY PIXEL DRIVE CHIPLETS

BACKGROUND

Recent years have seen very substantial growth in the market for displays as the quality of displays improves, their cost falls, and the range of applications for displays increases. This includes both large area displays such as for TVs or computer monitors and smaller displays for portable devices.

The most common classes of display presently on the market are liquid crystal displays and plasma displays although displays based on organic light-emitting diodes (OLEDs) are now increasingly attracting attention due to their many advantages including low power consumption, light weight, wide viewing angle, excellent contrast and potential for flexible displays.

The basic structure of an OLED is a light emissive organic layer, for instance a film of a poly (p-phenylenevinylene) ("PPV") or polyfluorene, sandwiched between a cathode for injecting negative charge carriers (electrons) and an anode for injecting positive charge carriers (holes) into the organic layer. The electrons and holes combine in the organic layer generating photons. In WO90/13148 the organic light- emissive material is a conjugated polymer. In US 4,539,507 the organic light-emissive material is of the class known as small molecule materials, such as ( 8-hydroxyquinoline) aluminium ( "Alq3" ). In a practical device one of the electrodes is transparent, to allow the photons to escape the device.

A typical organic light-emissive device ("OLED") is fabricated on a glass or plastic substrate coated with a transparent anode such as indium-tin-oxide ("ITO"). A layer of a thin film of at least one electroluminescent organic material covers the first electrode. Finally, a cathode covers the layer of electroluminescent organic material. The cathode is typically a metal or alloy and may comprise a single layer, such as aluminium, or a plurality of layers such as calcium and aluminium. In operation, holes are injected into the device through the anode and electrons are injected into the device through the cathode. The holes and electrons combine in the organic electroluminescent layer to form an exciton which then undergoes radiative decay to give light. The device may be pixellated with red, green and blue electroluminescent subpixels in order to provide a full colour display.

Full colour liquid crystal displays typically comprise a white-emitting backlight, and light emitted from the device is filtered through red, green and blue colour filters after passing through the LC layer to provide the desired colour image.

A full colour display may be made in the same way by using a white or blue OLED in combination with colour filters. Moreover, it has been demonstrated that use of colour filters with OLEDs even when the pixels of the device already comprises red, green and blue subpixels can be beneficial. In particular, aligning red colour filters with red electroluminescent subpixels and doing the same for green and blue subpixels and colour filters can improve colour purity of the display.

Downconversion, by means of colour change media (CCMs) for absorption of emitted light and reemission at a desired longer wavelength or band of wavelengths, can be used as an alternative to, or in addition to, colour filters.

One way of addressing displays such as LCDs and OLEDs is by use of an "active matrix" arrangement in which individual pixel elements of a display are activated by an associated thin-film transistor. The active matrix backplane for such displays can be made with amorphous silicon (a-Si) or low temperature polysilicon (LTPS). LTPS has high mobility but can be non-uniform and requires high processing temperatures which limits the range of substrates that it can be used with. Amorphous silicon does not require such high processing temperatures, however its mobility is relatively low, and can suffer from non-uniformities during use due to aging effects. Moreover, backplanes formed from either LTPS or a-Si both require processing steps such as photolithography, cleaning and annealing that can damage the underlying substrate. In the case of LTPS, in particular, a substrate that is resistant to these high-energy processes must be selected.

An alternative approach to patterning is disclosed in, for example, Rogers et al, Appl. Phys. Lett. 2004, 84(26), 5398-5400; Rogers et al Appl. Phys. Lett. 2006, 88, 213101- and Benkendorfer et al, Compound Semiconductor, June 2007, in which silicon on an insulator is patterned using conventional methods such as photolithography into a plurality of elements (hereinafter referred to as "chiplets") which are then transferred to a device substrate. The transfer printing process takes place by bringing the plurality of chiplets into contact with an elastomeric stamp which has surface chemical functionality that causes the chiplets to bind to the stamp, and then transferring the chiplets to the device substrate. In this way, chiplets carrying micro- and nano-scale structures such as display driving circuitry can be transferred with good registration onto an end substrate which does not have to tolerate the demanding processes involved in silicon patterning.

SUMMARY OF THE INVENTION

According to an embodiment of the invention, there is provided a method of connecting chiplet driver elements in an active matrix display, the method comprising: positioning a plurality of chiplets to form an active matrix area; establishing a plurality of connections linking chiplets in at least one logical chain, and wherein at least one connection is supplied with a data signal.

Preferably at least one connection is supplied with a synchronous clock signal.

Preferably at least one connection is supplied with a token signal. Preferably the token signal identifies a target chiplet within the logical chain for the data.

Preferably the token identifies a target area on the target chiplet.

Preferably the method further comprises establishing at least one orthogonal row connection configured to enable re-seeding of the token signal.

Preferably the at least one connection is selected from one or more of: GND₇ VDD.

Preferably each chiplet drives 6 pixels or subpixels.

Preferably the logical chain is connected in one dimension.

According to an embodiment of the invention, there is provided a backplane for an active matrix display comprising: a plurality of chiplets for driving pixels, wherein each of the plurality of chiplets is connected logically to another chiplet in a single dimension to form a logical chain, with no orthogonal row connections between chiplets.

Preferably the backplane comprises a plurality of logical chains.

Preferably the logical chain or logical chains are arranged in a regular 2-dimensional arrangement of chiplets.

Preferably the logical chain or logical chains are arranged to form a 2-dimensional grid of chiplets. The embodiments of the present invention advantageous for numerous reasons. For example, fewer connections are required in order to drive the pixels within the display, and there is no need for a regular grid since the chiplets are logically chained.

According to one embodiment, pixel chiplets are daisy chained on the data line to encode the location of a chiplet, thereby removing the need for a select line. According to one embodiment, this is done through addressing. According to another embodiment, this is done through a shift register, wherein the shift register is analogue or digital.

Throughout this specification, the term "control circuit" is used to refer to circuitry for programming the drive circuitry; "drive circuitry" is used to refer to circuitry for directly driving pixels of the display; and "display area" is used to refer to area defined by pixels of the display and associated drive circuitry.

Further advantages and novel features can be found in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention and as to how the same may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings, in which:

Figure 1 illustrates a device wherein the device is formed by firstly forming an anode on a substrate followed by deposition of an electroluminescent layer and a cathode;

Figure 2A shows an arrangement of a display pixel drive chiplet according to an embodiment of the invention; Figure 2B shows connected display pixel drive chiplets according to an embodiment of the present invention; and

Figure 3 shows chiplets connected in a single dimension according to an embodiment of the present invention.

DETAILED DESCRIPTION

Chiplet Material

The chiplets may be formed from semiconductor wafer sources, including bulk semiconductor wafers such as single crystalline silicon wafers, polycrystalline silicon wafers, germanium wafers; ultra thin semiconductor wafers such as ultra thin silicon wafers; doped semiconductor wafers such as p-type or n-type doped wafers and wafers with selected spatial distributions of dopants (semiconductor on insulator wafers such as silicon on insulator (e.g. Si-SiO2, SiGe); and semiconductor on substrate wafers such as silicon on substrate wafers and silicon on insulator. In addition, printable semiconductor elements of the present invention may be fabricated from a variety of nonwafer sources, such as a thin films of amorphous, polycrystalline and single crystal semiconductor materials (e.g. polycrystalline silicon, amorphous silicon, polycrystalline GaAs and amorphous GaAs) that is deposited on a sacrificial layer or substrate (e.g. SiN or SiO2) and subsequently annealed, and other bulk crystals, including, but not limited to, graphite, MoSe2 and other transition metal chalcogenides, and yttrium barium copper oxide.

The chiplets may be formed by conventional processing means known to the skilled person.

Preferably, each driver or LED chiplet is up to 500 microns in length, preferably between about 15-250 microns, and preferably about 5-50 microns in width, more preferably 5- 10 microns.

Transfer Process The stamp used in transfer printing is preferably a PDMS stamp.

The surface of the stamp may have a chemical functionality that causes the chiplets to reversibly bind to the stamp and lift off the donor substrate, or may bind by virtue of, for example, van der Waals force. Likewise upon transfer to the end substrate, the chiplets adhere to the end substrate by van der Waals force and / or by an interaction with a chemical functionality on the surface of the end substrate, and as a result the stamp may be delaminated from the chiplets.

Chiplet and Display Integration

The chiplets patterned with drive circuitry for addressing pixels or subpixels of a display may be transfer-printed onto a substrate carrying tracking for connection of the chiplets to a power source and, if required, drivers outside the display area comprising control circuitry for programming the chiplets.

To ensure accurate transfer onto a prepared end substrate, the stamp and end substrate may be registered by means known to the skilled person, for example by providing alignment marks on the substrate.

Alternatively, tracking for connection of the chiplets may be applied after the chiplets have been transfer printed.

In the case where the chiplets drive a display such as an LCD or OLED display, the backplane comprising the chiplets is preferably coated with a layer of insulating material to form a planarisation layer onto which the display is constructed. Electrodes of the display device are connected to the output of the chiplets by means of conducting through-vias formed in the planarisation layer.

Organic LED

In the case where the display is an OLED, the device according to the invention comprises a glass or plastic substrate 1 onto which the backplane (not shown) has been formed, an anode 2 and a cathode 4. An electroluminescent layer 3 is provided between anode 2 and cathode 4.

In a practical device, at least one of the electrodes is semi-transparent in order that light may be emitted. Where the anode is transparent, it typically comprises indium tin oxide. Preferably, the cathode is transparent in order to avoid the problem of light emitted from electroluminescent layer 3 being absorbed by the chiplets and other associated drive circuitry in the case where light is emitted through the anode. A transparent cathode typically comprises a layer of an electron injecting material that is sufficiently thin to be transparent. Typically, the lateral conductivity of this layer will be low as a result of its thinness. In this case, the layer of electron injecting material is used in combination with a thicker layer of transparent conducting material such as indium tin oxide.

It will be appreciated that a transparent cathode device need not have a transparent anode (unless, of course, a fully transparent device is desired), and so the transparent anode used for bottom-emitting devices may be replaced or supplemented with a layer of reflective material such as a layer of aluminium. Examples of transparent cathode devices are disclosed in, for example, GB 2348316.

Suitable materials for use in layer 3 include small molecule, polymeric and dendrimeric materials, and compositions thereof. Suitable electroluminescent polymers for use in layer 3 include poly(arylene vinylenes) such as poly(p-phenylene vinylenes) and polyarylenes such as: polyfluorenes, particularly 2,7-linked 9,9 dialkyl polyfluorenes or 2,7-linked 9,9 diaryl polyfluorenes; polyspirofluorenes, particularly 2,7-linked poly-9,9- spirofluorene; polyindenofluorenes, particularly 2,7-linked polyindenofluorenes; polyphenylenes, particularly alkyl or alkoxy substituted poly-l,4-phenylene. Such polymers as disclosed in, for example, Adv. Mater. 2000 12(23) 1737-1750 and references therein. Suitable electroluminescent dendrimers for use in layer 3 include electroluminescent metal complexes bearing dendrimeric groups as disclosed in, for example, WO 02/066552. Further layers may be located between anode 2 and cathode 3, such as charge transporting, charge injecting or charge blocking layers.

The device is preferably encapsulated with an encapsulant (not shown) to prevent ingress of moisture and oxygen. Suitable encapsulants include a sheet of glass, films having suitable barrier properties such as alternating stacks of polymer and dielectric as disclosed in, for example, WO 01/81649 or an airtight container as disclosed in, for example, WO 01/19142. A getter material for absorption of any atmospheric moisture and / or oxygen that may permeate through the substrate or encapsulant may be disposed between the substrate and the encapsulant.

Figure 1 illustrates a device wherein the device is formed by firstly forming an anode on a substrate followed by deposition of an electroluminescent layer and a cathode, however it will be appreciated that the device of the invention could also be formed by firstly forming a cathode on a substrate followed by deposition of an electroluminescent layer and an anode.

In many types of displays, each pixel is divided into single-colour regions that contribute to the displayed or sensed colour when viewed at a distance. Each single-colour region is a separately addressable "subpixel". In a typical colour display, each pixel comprises three subpixels; red, green and blue. The terms "pixel" and "subpixel" may therefore be interchanged in the context of this specification.

Figure 2A shows an arrangement of a display pixel drive chiplet according to an embodiment of the invention. In the arrangement shown, the chiplet 101 drives six pixels 102 and comprises ground (GND) and VDD lines and data lines D1-D3. These lines are common to all chiplets in a given column. In addition, the chiplet 101 further comprises common row connections 103 in order to connect the chiplet orthogonally to the next chiplet. According to this arrangement, it is necessary to increase the number of connections as the number of chiplet elements is increased (increase in connection density). For the avoidance of doubt, "column" and "row" as used herein are merely relative terms to indicate orthogonality.

Figure 2B shows connected display pixel drive chiplets according to an embodiment of the present invention. According to the example illustrated, the chiplet 101' drives six pixels 102'. As well as GND and VDD lines, the chiplet comprises a clock line 104', a token line 105' and a data line 106'. This arrangement enables chiplets to be connected in a single dimension, e.g. vertically, without the necessity for orthogonal select line connections, as shown in Fig. 3. The clock line 104' carries a clock signal used to coordinate the actions of two or more chiplets. The token line 105' is a "daisy-chained" line (i.e. without connections other than linear connections between chiplets) that carries a token from one chiplet in the chain to the next identifying the target for the data signal.

In the context of the present invention, the term "logical chain" is used to describe a series of chiplets connected one after the other by means of internal connections between the chiplets. The active matrix area may comprise one but more preferably a plurality of logical chains. According to one example of the logical chain is connected in one dimension between the bottom of one chiplet and the top of the subsequent chiplet in the chain (i.e. "vertically"). However, it should be noted that, according to embodiments of the present invention, it is not necessary to arrange the chiplets in any form of regular arrangement or grid, since they are connected logically in a daisy chain fashion. Thus, according to this chained arrangement, it is not necessary to increase the number of external connections as the number of chiplet elements in a logical chain is increased.

Those skilled in the art will appreciate that while this disclosure has described what is considered to be the best mode and, where appropriate, other modes of performing the invention, the invention should not be limited to the specific configurations and methods disclosed in this description of the preferred embodiment.

Claims

1. A method of connecting chiplet driver elements in an active matrix display, the method comprising: positioning a plurality of chiplets to form an active matrix area; establishing a plurality of connections linking chiplets in at least one logical chain, and wherein at least one connection is supplied with a data signal.

2. The method according to claim 1 wherein at least one connection is supplied with a synchronous clock signal.

3. The method according to claim 1 or 2 wherein at least one connection is supplied with a token signal.

4. The method according to claim 3 wherein the token signal identifies a target chiplet within the logical chain for the data.

5. The method according to any of claims 3 or 4 wherein the token identifies a target area on the target chiplet.

6. The method according to any of claims 1-5 further comprising establishing at least one orthogonal row connection configured to enable re-seeding of the token signal.

7 The method according to any preceding claim wherein the at least one connection is selected from one or more of: GND, V_DD.

8. The method according to any preceding claim wherein each chiplet drives 6 subpixels.

9. The method according to any preceding claim wherein the logical chain is connected in one dimension.

10. A backplane for an active matrix display comprising: a plurality of chiplets for driving pixels, wherein each of the plurality of chiplets is connected logically to another chiplet in a single dimension to form a logical chain, with no orthogonal row connections between chiplets.

11. A backplane according to claim 10 wherein the backplane comprises a plurality of logical chains.

12. A backplane according to claim 10 or 11 wherein the logical chain or logical chains are arranged in a regular 2-dimensional arrangement of chiplets.

13. A backplane according to claim 12 wherein the logical chain or logical chains are arranged to form a 2-dimensional grid of chiplets.