WO2010029138A3 - Method of etching using a multilayer masking structure - Google Patents

Method of etching using a multilayer masking structure Download PDF

Info

Publication number
WO2010029138A3
WO2010029138A3 PCT/EP2009/061776 EP2009061776W WO2010029138A3 WO 2010029138 A3 WO2010029138 A3 WO 2010029138A3 EP 2009061776 W EP2009061776 W EP 2009061776W WO 2010029138 A3 WO2010029138 A3 WO 2010029138A3
Authority
WO
WIPO (PCT)
Prior art keywords
etching
target layer
layer
array
oxide film
Prior art date
Application number
PCT/EP2009/061776
Other languages
French (fr)
Other versions
WO2010029138A2 (en
WO2010029138A9 (en
Inventor
Olivier Joubert
Thibaut David
Thierry Chevolleau
Gilles Cunge
Original Assignee
Commissariat A L'energie Atomique Et Aux Energies Alternatives
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat A L'energie Atomique Et Aux Energies Alternatives filed Critical Commissariat A L'energie Atomique Et Aux Energies Alternatives
Publication of WO2010029138A2 publication Critical patent/WO2010029138A2/en
Publication of WO2010029138A3 publication Critical patent/WO2010029138A3/en
Publication of WO2010029138A9 publication Critical patent/WO2010029138A9/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

The method of etching a target layer comprises the formation, on the target layer (1), of a multilayer structure (2) having an inorganic hard mask layer (4) which is placed on said target layer (1) and is itself covered by a mask (5) having an array of nanoscale features. The inorganic hard mask layer (4) comprises a thin metal oxide film with a thickness of 10 nm or less. The array of nanoscale features is transferred from the mask (5) to the thin metal oxide film (4) by first plasma etching under weak ion bombardment conditions.
PCT/EP2009/061776 2008-09-12 2009-09-10 Method of etching using a multilayer masking structure WO2010029138A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR08/05022 2008-09-12
FR0805022A FR2936094A1 (en) 2008-09-12 2008-09-12 ETCHING METHOD USING MULTILAYER MASKING STRUCTURE

Publications (3)

Publication Number Publication Date
WO2010029138A2 WO2010029138A2 (en) 2010-03-18
WO2010029138A3 true WO2010029138A3 (en) 2010-08-26
WO2010029138A9 WO2010029138A9 (en) 2010-10-28

Family

ID=40671438

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2009/061776 WO2010029138A2 (en) 2008-09-12 2009-09-10 Method of etching using a multilayer masking structure

Country Status (2)

Country Link
FR (1) FR2936094A1 (en)
WO (1) WO2010029138A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113517188A (en) * 2021-06-29 2021-10-19 上海华力集成电路制造有限公司 Patterning process method adopting multi-layer mask plate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020113310A1 (en) * 2000-10-31 2002-08-22 Kim Ji-Soo Conducting line of semiconductor device and manufacturing method thereof using aluminum oxide layer as hard mask
US20030064585A1 (en) * 2001-09-28 2003-04-03 Yider Wu Manufacture of semiconductor device with spacing narrower than lithography limit
US20040198065A1 (en) * 2003-04-04 2004-10-07 Sung-Kwon Lee Method for fabricating semiconductor device with fine patterns
WO2008070278A1 (en) * 2006-12-05 2008-06-12 International Business Machines Corporation Fully and uniformly silicided gate structure and method for forming same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020113310A1 (en) * 2000-10-31 2002-08-22 Kim Ji-Soo Conducting line of semiconductor device and manufacturing method thereof using aluminum oxide layer as hard mask
US20030064585A1 (en) * 2001-09-28 2003-04-03 Yider Wu Manufacture of semiconductor device with spacing narrower than lithography limit
US20040198065A1 (en) * 2003-04-04 2004-10-07 Sung-Kwon Lee Method for fabricating semiconductor device with fine patterns
WO2008070278A1 (en) * 2006-12-05 2008-06-12 International Business Machines Corporation Fully and uniformly silicided gate structure and method for forming same

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
KITAGAWA T ET AL: "ETCHING OF HIGH-K DIELECTRIC HFO2 FILMS IN BCL3-CONTAINING PLASMAS ENHANCED WITH O2 ADDITION", JAPANESE JOURNAL OF APPLIED PHYSICS, JAPAN SOCIETY OF APPLIED PHYSICS, JP LNKD- DOI:10.1143/JJAP.45.L297, vol. 45, no. 8, 1 March 2006 (2006-03-01), pages L297 - L300, XP001245515, ISSN: 0021-4922 *
LOWALEKAR V ET AL: "ETCHING OF ZIRCONIUM OXIDE, HAFNIUM OXIDE, AND HAFNIUM SILICATES IN DILUTE HYDROFLUORIC ACID SOLUTIONS", JOURNAL OF MATERIALS RESEARCH, MATERIALS RESEARCH SOCIETY, WARRENDALE, PA, vol. 19, no. 4, 1 April 2004 (2004-04-01), pages 1149 - 1156, XP008074957, ISSN: 0884-2914 *
PAULIAC-VAUJOUR S ET AL: "Improvement of high resolution lithography by using amorphous carbon hard mask", MICROELECTRONIC ENGINEERING, ELSEVIER PUBLISHERS BV., AMSTERDAM, NL, vol. 85, no. 5-6, 1 May 2008 (2008-05-01), pages 800 - 804, XP022678608, ISSN: 0167-9317, [retrieved on 20080229] *
ROBB F Y: "HYDROGEN PLASMA ETCHING OF ORGANICS", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOCIETY. MANCHESTER, NEW HAMPSHIRE, US, vol. 131, no. 7, 1 July 1984 (1984-07-01), pages 1670 - 1674, XP000841727, ISSN: 0013-4651 *

Also Published As

Publication number Publication date
FR2936094A1 (en) 2010-03-19
WO2010029138A2 (en) 2010-03-18
WO2010029138A9 (en) 2010-10-28

Similar Documents

Publication Publication Date Title
WO2009062123A3 (en) Pitch reduction using oxide spacer
WO2008016650A3 (en) Methods of forming carbon-containing silicon epitaxial layers
MY148830A (en) Method for plasma etching performance enhancement
WO2009085598A3 (en) Photoresist double patterning
WO2010014380A3 (en) Within-sequence metrology based process tuning for adaptive self-aligned double patterning
WO2008083304A3 (en) Method of making inorganic or inorganic/organic hybrid films
TW200834245A (en) Method for manufacturing semiconductor device with four-layered laminate
WO2009075793A3 (en) Controlling thickness of residual layer
WO2005091974A3 (en) Methods for the optimization of substrate etching in a plasma processing system
WO2008045202A3 (en) Method to deposit conformal low temperature sio2
WO2012058377A3 (en) Methods for etching oxide layers using process gas pulsing
WO2006118851A3 (en) Method of making scratch resistant coated glass article including layer(s) resistant to fluoride-based etchant(s)
WO2010065252A3 (en) Methods of fabricating substrates
WO2012150278A9 (en) Hierarchical carbon nano and micro structures
WO2006128028A3 (en) Wafer-level, polymer-based encapsulation for microstructure devices
WO2012093807A3 (en) Method and device for fingerprint resistant coating
TW200629374A (en) Patterning substrates employing multi-film layers defining etch-differential interfaces
WO2005038865A3 (en) Amorphous carbon layer to improve photoresist adhesion
TW200707540A (en) Method of controlling the critical dimension of structures formed on a substrate
WO2009078190A1 (en) Pattern forming method and pattern formed body
SG138523A1 (en) Method of integrating triple gate oxide thickness
WO2008111350A1 (en) Surface treatment method for phosphor and method for manufacturing flat display
WO2009085597A3 (en) Cd bias loading control with arc layer open
TW200729333A (en) Etching method and etching device
WO2008088831A3 (en) Coiled circuit device with active circuitry and methods for making the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09782889

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09782889

Country of ref document: EP

Kind code of ref document: A2