WO2010026064A1

WO2010026064A1 - Filtering device with a hierarchical structure, and reconfigurable filtering device

Info

Publication number: WO2010026064A1
Application number: PCT/EP2009/060845
Authority: WO
Inventors: Suresh Pajaniradja; Mickael Guibert; Renaud Schmit
Original assignee: Commissariat A L'energie Atomique
Priority date: 2008-09-05
Filing date: 2009-08-21
Publication date: 2010-03-11
Also published as: US8751553B2; FR2935850B1; EP2319177A1; US20110208795A1; JP2012502530A; EP2319177B1; FR2935850A1

Abstract

The invention relates to a filtering device with a DFSH hierarchical structure for carrying out linear filtering functions with finite impulse response (FIR) and with infinite impulse response (IIR), which can be combined with one or more devices of the same type, wherein said device includes at least first (1) and second (2) filtering modules (MF) including a means for carrying out filtering functions with N configurable coefficients. A first subset of the N coefficients of an MF module is configured so as to carry out non-recursive filtering functions, and a second subset of said coefficients can be configured so as to carry out recursive filtering functions, wherein one or more counter-reaction loops can be activated per MF module, at least one sample of the filtering result being generated at each clock cycle. The invention also relates to a DFR reconfigurable filtering device using at least two filtering devices with a DFSH hierarchical structure (51, 52).

Description

HIERARCHICAL STRUCTURE FILTERING DEVICE AND RECONFIGURABLE FILTERING DEVICE

The invention relates to a digital filtering device with a reconfigurable hierarchical structure and applies in particular to the fields of signal processing, image processing, filtering and telecommunications.

Linear filters are widely used in image processing, signal processing and telecommunications.

In image processing they can reduce noise, increase contrast, smooth, extract coarse features or extract the outlines of an image. For example, the operators of Sobel and Prewitt can detect the outlines of an image. A matrix convolution of the image is performed using a two-dimensional convolution mask, the mask being of size 3 × 3. This convolution is carried out in the discrete spatial domain and is implemented in practice by means of a finite impulse response FIR filter of order 3. Other more precise methods of contour detection use infinite impulse response filters NR. NR filters are more complex to implement than FIR filters because of their recursive characteristic. Indeed, the output of the filter depends on the input samples but also the previous results resulting from the filtering. In addition, the type of data supply must be different in order to present an anticausal flow at the input of the filter. By way of example, the Deriche and Shen filters, which are widely used in image processing, are NR filters of order 2 and order 1 respectively. The Deriche filter allows edge detection on a processed image based on gradient calculations. The gradient along the abscissa axis is calculated using a smoothing filter in the ordinate direction, then a drifting filter in the abscissa direction. Each of the two filters breaks down into a causal part and an anti-causal part. Another smoothing filter and another derivation filter are also needed to calculate the gradient along the y-axis. Four recursive filters are needed to perform contour detection with this method. It is increasingly common for a signal processing system to have the ability to perform several competing applications. In the case of an image processing system, the algorithms typically use several types of operations to be performed on the images, including linear filtering operations. Several types of filters can be computed and combined to extract useful information from the image. A hardware module having a high computing power while allowing flexibility to perform different functions is now particularly useful in an embedded system.

Existing solutions for performing linear filtering operations are typically performed using processors or dedicated architectures.

In the case of solutions based on embedded processors, it is possible to carry out linear filtering operations with general purpose processors, with signal processing processors known as DSPs, or with specific processors of the SIMD type. By their programmability, the use of processors allows a flexible implementation, but the computing power available is limited. Indeed, in order to perform N-length filtering, a conventional general-purpose processor typically requires 4xN clock cycles per image pixel to perform a convolution.

A DSP processor is more suitable for this kind of operation but requires N / 2 cycles per pixel of image. Due to its highly parallel structure, a SIMD processor is particularly suitable for linear convolution but less so for making recursive filters. This is due to the management of different types of data access (causal and anti-causal) as well as the previous dependency on recursive filters. In addition, this type of calculation requires significant precision and great computational dynamics. Embedded SIMD processors are limited in both respects.

An implementation based on a dedicated architecture optimizes processing times but is not flexible enough. It is difficult in this case to implement on the same architecture both FIR filters and NR filters while optimizing the cost of silicon. It appears that the existing solutions allow either great flexibility of implementation at the cost of low computational performance, or conversely good computing performance at the cost of limited flexibility of use.

An object of the invention is in particular to overcome the aforementioned drawbacks.

For this purpose, the object of the invention is a hierarchical structure filtering device DFSH making it possible to perform linear finite impulse response FIR and infinite impulse response NR functions and which can be combined with one or more devices of the same type, device comprising at least a first and a second filtering module MF comprising means for performing filtering functions with N configurable coefficients. A first subset of the N coefficients of an MF module is configured to perform non-recursive filtering functions, a second subset of said coefficients being configurable to perform recursive filtering functions, one or more counter-reaction that can be activated by FM module, at least one filter result sample being generated at each clock cycle. The device DFSH comprises at least one main input port for transmitting to the device a stream of samples to be filtered, said port being connected to the two MF filtering modules, a secondary input port connected to the first MF filtering module allowing transmitting a second sample stream to the device, a main output port for transmitting the result of the filtering operations at the device output after combining the output streams of each reconfigurable filtering module, a secondary output port for transmitting a result after filtering composed of a stream of samples taken at the output of the second MF filtering module (2), said port being connectable to the secondary input port (3) of another digital filtering device.

The flow of samples presented to the secondary input port is, for example, a flow of samples to be processed independent of the flow presented to the main input port. The stream of samples is, for example, a stream coming from another DFSH device, the two devices being connected in order to perform a filtering function of order greater than N.

The filtering device is configurable in at least three filtering configurations, the first configuration corresponding to an N / 2-order 2D NR filter, the second configuration corresponding to two N-order 2D FIR filters and the third configuration corresponding to a 2D FIR filter of order 2xN.

The values of the filter coefficients used by each MF filtering module are stored, for example, in programmable registers. Anti-causal sample flows are generated, for example, by LIFO circuits, said LIFO circuits being placed at the output of the first filtering module MF and at the input of the second filtering module MF. The data processed by said DFSH device may be, for example, in the integer format, fixed point format. The filtering device may comprise a synchronization module making it possible to automatically compensate the differences in latency between the outputs of the two filtering modules.

For example, each MF filtering module used by the device comprises at least N multipliers, N delay cells, two adders trees, a main input port, a secondary input port, a main output port and a secondary output port.

Each filtering module used by the device comprises, for example, a realignment function upstream of the main output port when the samples to be processed are represented in fixed-point format and a compensation function placed upstream of the secondary output port enabling balance the latencies introduced by multipliers and adders trees.

The routing of the data streams internally of the device is chosen, for example, using switching flip-flops.

The subject of the invention is also a reconfigurable filtering device DFR using at least two hierarchical structure filtering devices DFSH, said device comprising at least four input ports enabling one or more sample streams to be presented at the input of the device. filter, four output ports to present at the output of the device or the flow resulting from the filtering operation or operations carried out by the device, a reconfigurable switching circuit making it possible, on the one hand, to route the input streams either to the main input ports or to the secondary input ports of the input port; either of the DFSH devices, and secondly to route the available results to the main or secondary output ports of the DFSH devices either at the output of the DFR device or to the main input ports at the secondary of a DFSH device. other DFSH devices.

The invention has the particular advantage of proposing a solution that makes it possible to implement several types of filters on the same architecture, on the one hand FIR finite impulse response filters and on the other hand infinite impulse response filters RII. The order and size of the filters is configurable and allows to use the same architecture in the context of competing applications. Another advantage of the invention is that the proposed architecture allows efficient and fast execution of the filter functions even when the size of the filters is important. It is therefore possible to process, for example, images of significant resolution.

The invention is useful in the context of the implementation of several types of signal processing algorithms while optimizing the implementation cost and reducing the silicon occupation of the systems using the invention.

Other features and advantages of the invention will become apparent with the aid of the following description given by way of non-limiting illustration, with reference to the appended drawings in which:

FIG. 1 illustrates an example of a hierarchical structure filtering device according to the invention, said device being designated by the acronym DFSH; FIG. 2 shows an exemplary N-coefficient reconfigurable filtering module used by the hierarchical structure filtering device DFSH, said module being designated by the acronym MF; FIG. 3 illustrates an example of a reconfigurable filtering device using several DFSH devices, said device being designated by the acronym DFR.

FIG. 1 shows an exemplary filtering device with a reconfigurable hierarchical structure DFSH according to the invention. In this example, the device is composed of two MF reconfigurable filter modules N coefficients 1, 2 representing the computing core of the device. Each of these modules is composed of a hardware circuit for performing linear filtering functions with N coefficients. These MF modules may be configured to produce FIR finite impulse response filters or NR infinite impulse response filters and produce a result sample at each clock cycle. An MF module comprising N coefficients is capable of producing the N multiplications and N-1 additions of a filter, recursive or not, in a single clock cycle. The sample streams arrive at the rate of one sample per clock cycle and the MF module produces a sample result per clock cycle. Thus, the circuit makes it possible to perform filtering calculations in parallel and as fast as the clock frequency allows. The same function can be performed on CPU type programmable processors but said CPUs can not produce a sample result every clock cycle.

The DFSH device furthermore comprises two input ports, namely a main input port 4 and a secondary input port 3.

The main input port 4 makes it possible to receive the stream of the input samples to be filtered, the stream possibly being composed, for example, of the pixels of an image.

The secondary input port 3 can be used in two ways. In a first use, the secondary input port 3 is used to receive a second stream of samples to be processed in parallel with the first, for example a stream of pixels corresponding to a second image to be processed. In a second use, the secondary input port is used to receive partial filtering results when multiple DFSH devices are used in series.

In addition, the DFSH device includes two output ports, namely a main output port 11 and a secondary output port 12. The main output port 1 1 transmits at the output of the device the sample results of the filtering operations.

The secondary output port 12 can be used in two ways. In a first configuration, the secondary output port 12 is used to transmit the results of the second module MF 2 at the output of the device. This secondary port 12 may be used as a second filter output when the device is configured to perform multiple filters in parallel. In a second configuration, the secondary output port 12 transmits at the output of the device the samples presented to the main input port 4. This configuration is chosen especially when the device DFSH is combined with one or more DFSH devices of the same type.

As previously explained, the device DFSH consists of two MF modules 1, 2 performing the filtering operations. Each MF module has the ability to perform FIR or NR type filtering depending on how it has been configured. When the modules are configured to produce NR filters, LIFO circuits 5, 7, an acronym derived from the last "Last In First Out", are used to create anti-causal data sources. Thus, a DFSH device is capable of performing in a single pass and simultaneously a recursive causal treatment, that is to say a treatment whose results depend on the input samples and the past outputs, but also an anti-recursive processing. causal, that is, a treatment whose results depend on input samples and future outputs. LIFO circuits are memory components for reversing the order of samples. For example, at the output of the circuits LIFO 5, 7, a flow e ₀ , ei, ... e _n is output in the order e _n , e _n- i, ... ei, e ₀ . This inversion is essential for recursive treatments such as Deriche or Shen, for example. The LIFO circuits are based on memory elements of sufficient capacity to store all the input samples e ₀ , ei, ..., e _n For example, in an image processing type application, at least one Image line can be memorized.

A synchronization module 9 makes it possible to automatically compensate for the latency differences between the outputs of the two MF modules 1, 2 before they are processed by an adder / subtractor 10. The resulting samples are then directed to the main output port 1 1. The DFSH device is configurable in the sense that each MF module is itself configurable. Moreover, the routing of the data streams in the DFSH device is also configurable thanks to switching components 6, 8, 13. The given DFSH device example makes it possible to produce different filtering schemes depending on the configuration of the devices. interconnections of the device and the MF modules 1, 2.

If the DFSH device is used in image processing applications, the device allows 1D filtering, i.e., line-by-line image processing. 2D filtering can also be done by re-injecting the previous column by column results into the input of the DFSH device. Indeed, when the 2D convolution mask is decomposable into two convolution masks 1D, the 2D filtering operation is equivalent to two 1D filtering operations. The DFSH device can be parameterized to perform at least three filtering configurations in accordance with FIG. two filter passes.

A first configuration makes it possible to produce a 2D NR filter of order N / 2. For this, it can be configured in the following way: the two MF modules 1, 2 are configured in recursive mode with their activated feedback loops; the two LIFO circuits 5, 7 are activated; the main input port 4 is used and passes through the first module MF 1 to perform a causal recursive processing whose order of the samples is inverted by the first circuit LIFO 5 disposed at the output of the first module MF; the stream of samples presented to the main input port 4 is inverted by the second LIFO circuit 7 and passes through the second module MF 2 for carrying out an anti-causal treatment; the causal and anti-causal treatments are synchronized by the synchronization module 9 and combined by the adder / subtractor 10, and the result samples are directed to the main output port 11; a second calculation run is performed on the result samples from the MF modules with appropriate coefficients in order to realize the 2D NR function of order m.

A second configuration makes it possible to produce two 2D FIR filters of order N, which means that two separate sources can be processed simultaneously by the device. As part of an image processing application, two images can be processed in parallel. For this, the DFSH device is configured as follows: the two MF modules 1, 2 are configured in non-recursive mode without feedback loop activated. The first FM module 1 is configured to perform a processing on the samples presented on its secondary input port, and the second module MF 2 is configured to perform a processing on the samples presented on its main input port; - the two LIFO circuits 5, 7 are not activated; the two multiplexers 6, 8 are configured to bypass the LIFO circuits; a flow of samples is presented at the level of the secondary input port 3 and passes through the first module MF 1, said module carrying out the processing corresponding to the first filter

FIR; the synchronization module 9 is configured to allow only the flow coming from the first FM module 1 to pass through one of its outputs, the second output being forced to 0. the adder 10 transmits the unchanged stream of output samples from the first MF 1 module to the main output port

1 1; an input sample stream presented at the main input port 4 and independent of the stream presented at the secondary input port 3 is transmitted to the second module

MF 2 to realize the second 2D FIR filter; a second pass on the previous results in these modules with appropriate coefficients realizes the 2D FIR function of order N. A third configuration allows to realize a 2D order FIR filter

2 × N. In this case, only one source can be processed in two filter passes, but the filtering length is twice as large as in the second configuration. Two N-independent independent 2D FIR filters are made when the DFSH device is configured as follows: the two MF modules 1, 2 are cascaded in non-recursive mode without activating a feedback loop; the first MF module 1 is configured to perform sample processing presented on its main input port; the second module MF 2 is configured to perform a processing on the samples presented at its secondary input port; the secondary output of the first module MF 1 is activated and is connected to the secondary input of the second module MF 2; LIFO circuits 5, 7 are not activated; the multiplexers 6, 8 are configured so that the samples bypass the LIFO circuits; the samples of the source to be filtered are presented at the main input port 4, the samples then pass through the first module MF 1 and then the second module MF 2 to carry out FIR filtering treatment of order 2N; the result sample stream leaves the second module MF 2, passes through the multiplexer 13 and is presented to the secondary output port 12; a second pass of the previous results reinjected in the port 4 in these modules with appropriate coefficients of MF 1 and MF2 realizes the 2D FIR function of order 2N.

By combining the use of several DFSH devices, it is possible to make filters longer than 2xN.

FIG. 2 shows an example of a reconfigurable filtering module MF that can be used by the device DFSH as illustrated by FIG. module makes it possible to perform filtering functions with N coefficients a- _\ 40 to a _N 41. Among these N coefficients, k are non-recursive and m are recursive 31 and N = m + k. The module therefore makes it possible to perform filtering functions FIR of order N or of filtering NR of order m. It is possible to configure a feedback loop very precisely by choosing the values of the coefficients a ^ to a _m . It is also possible to activate several return loops on different coefficients a- _\ to a _m .

An FM module includes two input ports, a main input port 36 and a secondary input port 37. It further includes two output ports, a main output port 38 and a secondary output port 39. .

The samples to be filtered are presented at the main input port 36 of the MF module. At each clock cycle, a result sample is available at the main output port 38. The MF module is composed of shift register banks 42 and N multiplying circuits 43 for weighting the samples delayed by the filter coefficients. . The values of said coefficients are stored in programmable registers.

The intermediate results obtained after applying the delays and weighting of the input samples are summed using adder trees 32, 33 respectively for the non-recursive part 30 and the recursive part 31 of the filter. The result of the output of the two trees is then added 44 and processed by a realignment function 34 in the case where the module processes data in fixed-point format. The implementation of multipliers 43 and adders 32, 33 is performed, for example, with combinational circuits having "pipeline" stages to increase the rate of the clock.

A feedback loop 45 makes it possible to reinject the results of the filtering at the input of the recursive part 31 of the filter. This return channel is used only when the module is configured to perform NR filtering. The feedback loop is reconfigurable, which makes it possible to adjust the depth of the recursive portion 31 of the filter. As previously explained, the values of the filter coefficients are programmable. They can therefore be chosen according to the targeted application. It is also possible to increase the order of the filter to be achieved by using two MF modules connected to each other. If it is possible to perform an N-order FIR filtering function with a module, it is also possible, for example, to perform a 2xN order FIR filtering function using two MF modules. The module therefore comprises a main input-output torque 36, 38 and a secondary input-output torque 37, 39 used when several MF modules are combined, as is the case for the DFSH device of FIG. 1. The latencies multipliers and adder trees are balanced by a compensation function 35 inputting the output 46 of the recursive portion 31 of the filter. The result after compensation is presented at the secondary output port 39 of the first MF module to be reinjected at the secondary input port 37 of the second MF module.

In case the MF module is configured to perform a filter

FIR, the function performed is as follows:

F _πR (e _ι ) = Σ a _J xe _ι _ _J (1)

where the input samples to be filtered are denoted βj and the coefficients of the FIR filter are denoted a _j .

This function makes it possible to configure the coefficients to execute a 1 D filter. If the target application requires the implementation of a 2D filter, the coefficients will be readjusted and the results of the first filtering will be reinjected at the input port. main 36 of the module.

In the case where the module is configured to produce a filter NR, the function performed is as follows:

F _UR (e,) = Σ a _{m +]} xe _x _ _} + Σ a _m _ _{J + 1} x F _m (e ^) (2) the input samples to be filtered are denoted βi, the first m coefficients ai of NR filter corresponding to the recursive part of the filter and the following k to the non-recursive part. Figure 3 shows an example of a reconfigurable filtering device

DFR 50. Two DFSH devices 51, 52 are used as basic reconfigurable elements. The combination of these elements makes it possible to increase the size of the filter to be made or to carry out several distinct filtering functions simultaneously.

This DFR device makes it possible to process in particular data in the integer format, in the fixed-point format or in the floating-point format. The size and format of the data to be processed depends on the choice of implementation. The device can therefore process, for example, high dynamic data from a video sensor.

The two hierarchical structure digital filtering devices 51, 52 are connected to each other by means of an 8x8 53 switching module. This module 53 is reconfigurable and makes it possible to route the flows presented to the input ports of the device 54, the intermediate results DFSH devices and outputs 55. Input streams 54 are directed to either the main input ports 56, 58 or to the secondary input ports 57, 59 of either of the 51 or 52 of the devices. FSHD. The results available on the main output ports 60, 62 or secondary 61, 63 are routed either at the output of the DFR device 55 or to the main or secondary input ports of the other DFSH device. This second option makes it possible to increase the size of the filtering function to be performed.

The switching module 53 is programmable and allows a flexible use of the computing resources 51, 52. It should be noted that the more the switching module 53 is flexible, that is to say that it can be programmed from Many different ways, plus its silicon surface cost is high. An 8x8 switching module, also called, in the English terminology "switch 8x8", manages eight inputs and eight outputs. Thus, DFSH input streams, output streams, and intermediate results are routed according to the intended use of the device. The routing module can be implemented, in particular, using a "crossbar" circuit offering a large maximum. It is also possible to synthesize an 8x8 switch to part, for example, several 2x2 switch.

The exemplary DFR device according to the invention illustrated by FIG. 3 can be used in particular in an on-board image processing system requiring a high computing power. It was emphasized previous that the switching module 53 allows flexible use of the device. The device is capable of executing up to four linear filters of size N simultaneously. But it can also be configured to make two 2xN length filters or a 4xN length filter. Thus, this device is effective especially in the context of stereoscopic video systems because two independent images can be processed in X and Y simultaneously with two filters allocated to each of the images.

A DFR module comprises, for example, 4 inputs and 4 sample flow outputs, the input streams being routable to the two main input ports and the two secondary input ports of the DFSH devices included in the DFR device. . The DFR device can thus be configured into 4 independent recursive filters simultaneously processing 4 independent sample streams. Indeed, the MF modules included in the DFSH devices comprise means for performing the recursive filter function from a sample stream, that is to say a weighted sum with looped result. As a DFSH module 51, 52 has 2 independent inputs and 2 outputs, it is possible to make 2 independent recursive filters. Thus, by combining two DFSH modules, a DFR module makes it possible to configure 4 independent and simultaneous recursive filters, the processing flow rate for each output being one sample per clock cycle.

A device of the DFR type is reconfigurable but is not microprogrammed. In other words, it is not dependent on a microcode. An external device such as a CPU can initially configure the 8x8 53, DFSH 51, 52, MF switch modules, turnouts and multiplicative constants of the MF modules through a simple configuration interface. Once the configuration is complete the execution of the filters is autonomous and automatic. The circuit responds only to the input data stream. It is the input streams that trigger the filtering calculation and not an external CPU.

Claims

CLAIMS - DFSH hierarchical structure filtering device for performing FIR finite impulse response and infinite impulse response NR linear filtering functions that can be combined with one or more devices of the same type, said device comprising at least a first (1 ) and a second (2) MF filtering module comprising means for performing filtering functions with N configurable coefficients, said device being characterized in that a first subset of the N coefficients of an MF module is configured so performing non-recursive filtering functions, a second subset of said coefficients being configurable to perform recursive filtering functions, one or more feedback loops that can be activated per FM module, at least one result sample filtering being generated at each clock cycle, the DFSH device comprises at least: a main input port (4) for transmitting to the device a flow of samples to be filtered, said port being connected to the two MF filtering modules (1, 2); a secondary input port (3) connected to the first MF filter module (1) for transmitting a second sample stream to the device; a main output port (1 1) for transmitting the result of the filtering operations at the output of the device after combining (10) the output streams of each reconfigurable filtering module; a secondary output port (12) for transmitting a result after filtering composed of a stream of samples taken at the output of the second MF filtering module (2), said port being connectable to the secondary input port (3) another digital filtering device. Filtering device according to claim 1 characterized in that the flow of samples presented to the secondary input port (3) is a stream of samples to be processed independent of the flow presented at the main port of entry (4). - Filtering device according to claim 1 characterized in that the flow of samples is a stream from another device DFSH, the two devices being connected in order to perform a higher order filtering function N. - Device filtering device according to any one of the preceding claims, characterized in that it is configurable in at least three filtering configurations, the first configuration corresponding to a 2D NR filter of N / 2 order, the second configuration corresponding to two 2D FIR filters. of order N and the third configuration corresponding to a 2D FIR filter of order 2xN. - Filtering device according to any one of the preceding claims characterized in that the values of the filter coefficients used by each MF filtering module are stored in programmable registers. Filtering device according to any one of the preceding claims, characterized in that anticausal sample flows are generated by LIFO circuits (5, 7), said LIFO circuits being placed at the output of the first MF filtering module (1). and at the input of the second MF filtering module (2). - Filtering device according to any one of the preceding claims characterized in that the data processed by said DFSH device can be in the integer format, fixed-point format. - Filtering device according to any one of the preceding claims, characterized in that it comprises a synchronization module (9) for automatically compensating latency differences between the outputs of the two filter modules (1, 2). - Filtering device according to any one of the preceding claims characterized in that each MF filtering module (1, 2) used by the device comprises at least N multipliers (43), N delay cells (42), two shafts adders (32, 33), a main input port (36), a secondary input port (37), a main output port (38) and a secondary output port (39). 0- filtering device according to claim 9 characterized in that each filtering module (1, 2) used by the device comprises a realignment function (34) upstream of the main output port (38) when the samples to be treated are represented in a fixed-point format and a compensation function (35) located upstream of the secondary output port (39) for balancing the latencies introduced by the multipliers (43) and the adders trees (32, 33). 1 -Dispositif filter according to any preceding claim characterized in that the routing of data flows internally of the device is selected using switching flip-flops (6, 8, 45, 48). 2- DFR reconfigurable filtering device using at least two DFSH hierarchical structure filtering devices (51, 52) as defined in any one of the preceding claims, said device being characterized in that it comprises at least: four ports input device (54) for presenting at the input of the device one or more streams of samples to be filtered; four output ports (55) for presenting at the output of the device the stream or flows resulting from the filtering operation or operations performed by the device; a reconfigurable switching circuit (53) for firstly routing the input streams (54) to either the main input ports (56, 58) or the secondary input ports (57, 59) of one (51) or the other (52) DFSH devices, and secondly to route the available results to the ports of primary (60, 62) or secondary (61, 63) outputs of the DFSH devices either at the output of the DFR device (55) or at the primary to secondary input ports of other DFSH devices.