WO2010020168A1

WO2010020168A1 - Td-scdma signal detection method and apparatus

Info

Publication number: WO2010020168A1
Application number: PCT/CN2009/073306
Authority: WO
Inventors: 肖海勇
Original assignee: 中兴通讯股份有限公司
Priority date: 2008-08-18
Filing date: 2009-08-17
Publication date: 2010-02-25
Also published as: CN101656552A; CN101656552B

Abstract

The invention discloses a Time-Division Synchronization Code Division Multiple Access (TD-SCDMA) signal detection method and apparatus, wherein the method includes: implementing the channel estimation of the training sequence signal separated from the received signal, and then obtaining the channel estimation result of time domain; denoising the signal of the two data portions, and obtaining the time domain signal of the two data portions; implementing the signal estimation of the channel estimation result of time domain and the time domain signal of the two data portions with Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT), and obtaining the estimated chip signal; descrambling and dispreading the estimated chip signal, and obtaining the detection result of all the transmitted symbols; soft-demodulating the obtained detection result, and then transmitting it to the transmission channel. By the invention it does not need complicated operation of matrix inversion or Cholesky decomposition, and does not need complicated operation of code-activation detection, to detect the timeslot data of TD-SCDMA system, and thus the control and calculation complexity of system implementation is greatly reduced.

Description

The present invention relates to the field of communications technologies, and in particular, to a time division-synchronous code division multiple access signal detection method and detection apparatus. BACKGROUND OF THE INVENTION The Time-Division Synchronization Code Division-Multiple-Access (TC-SCDMA) standard is a synchronous time-division 3G technology proposed by China. The slot structure of TD-SCDMA is shown in Fig. 1. 10ms radio frame, each radio frame is divided into two 5ms subframes, and each subframe is divided into 7 data slots and uplink and downlink synchronization slots. Each data slot is further divided into two 352 chip data areas, a 144 chip training sequence (midamble) and a 16 chip guard interval. In the downlink channel, the data in the data area can be spread by using an Orthogonal Variable Spreading Factor (OFDM) code with a spreading factor of 16 or 1, and the transmission is synchronized after scrambling. The midamble part uses a fast Fourier Transform (FFT) method for channel estimation based on a special cyclically shifted non-spread spectrum sequence. For the data part, due to the synchronization of data and the existence of guard interval, joint detection algorithm (Joint Detection, called JD) can be used for estimation. After estimating the channel using the received data of the midamble part, due to the multipath delay of the wireless channel, the data area and the midamble part are mutually coexisting at the boundary between the two, since the midamble and the channel are known, in the joint detection. To effectively use this part of the data, you need to first perform the midamble interference cancellation on this part of the data, and then use the joint detection algorithm to detect the signal. The system formula for joint detection is as follows: e = A d + n where e is the received signal, d is the transmitted symbol for all code channels of all users, n is the noise, and A is the system matrix with the following block diagonal Toeplize form:

1 P27493

Where each block V on the diagonal is the same, the number of columns in each block is the sum of the code channels of all users, and one column of each block is a signature signature of one code channel, that is, the spread code of the code channel is scrambled dot product. Convolution with the channel impulse response, other specific details of the above formula can be referred to the relevant literature, and will not be described in detail herein. The joint detection algorithm is the zero-forcing (ZF) algorithm or the minimum mean square error (MMSE) algorithm of the above system equation. The formula of the ZF algorithm is as follows: d = (A ^H A)- ^l A ^H e

The formula of the MMSE algorithm is as follows: d = (A ^H A + a ² iy ^l A ^H e Usually adopts the MMSE algorithm. It can be seen that the implementation of the joint detection algorithm requires inversion of a huge matrix. Due to the partitioning of the A matrix For diagonal structures, the inversion can be approximated by a relatively small matrix using the Cholesky decomposition method. However, the hardware control implementation is still very complicated, and the joint detection algorithm needs to know the code currently used by all users in each time slot. Therefore, an additional code activation detection module needs to be added to detect the activation code channel of each time slot, which further increases the complexity of the system, and the accuracy of code activation detection is difficult to guarantee, which may affect the robustness of the system.

2 P27493 SUMMARY OF THE INVENTION In view of the problem that the downlink time slot signal detection technology is too high in the TD-SCDMA system existing in the prior art, and the control and complexity cost is too high in hardware implementation, the present invention aims to provide a time division- Synchronous code division multiple access signal detection method and detection device to solve at least the above problems

In order to achieve the above object, according to an aspect of the present invention, a time division-synchronous code division multiple access signal detecting method is provided. The time-division-synchronous code division multiple access signal detection method according to the present invention includes: Step A: performing channel estimation on the training sequence signal separated from the received signal to obtain a time domain channel estimation result; Step B: pairing two data The area signal is subjected to denoising processing to obtain time domain signals of two data areas; Step C: performing signal analysis on time domain channel estimation results and time domain signals of two data areas by using fast Fourier transform and fast inverse Fourier transform Estimating processing, estimating the chip signal; Step D: performing descrambling and despreading the estimated chip signal to obtain detection results of all transmitted symbols; Step E: performing soft demodulation on the obtained detection result, and transmitting to the transmission channel. Preferably, the foregoing step B specifically includes: Step B1: canceling interference of the training sequence signal on the signals of the two data areas according to the time domain channel estimation result and the known training sequence signal; Step B2: canceling the two data after interference The zone signals are separately smeared to obtain time domain signals of the two data zones. Preferably, in the above step B1, after the interference of the training sequence signal with the signals of the two data areas is eliminated, the received signal of the following form is obtained:

3 P27493

Where r is the first data zone signal or the second data zone signal after the interference of the training sequence is eliminated, H is the Toeplize matrix with the same diagonal elements, s is the chip signal sent by the originating end, and n is the noise interference. Preferably, in the above step B2, the smear processing is performed according to the following formula:

The towel τ' is the first data zone signal or the second data zone signal after trailing processing, Η' is a cyclic matrix, and η' is noise interference. Preferably, when the zero-forcing algorithm is adopted, the foregoing step C specifically includes: performing fast Fourier transform on the time domain channel estimation result to the frequency domain to obtain a frequency domain channel estimation result; and performing fast time domain signals of the two data areas. Fourier transform to the frequency domain to obtain frequency domain signals of two data regions; divide the frequency domain signals of the two data regions subjected to fast Fourier transform and the frequency domain channel estimation results respectively; As a result, the inverse fast Fourier transform is performed to the time domain, and the chip signal is estimated.

4 Ρ27493 Preferably, when the minimum mean square error algorithm is used, and the estimated noise power is also outputted in the above step A, the step C specifically includes: performing fast Fourier transform on the time domain channel estimation result to the frequency domain, The frequency domain channel estimation result is obtained; the frequency domain channel estimation result is respectively subjected to modulo square and conjugate processing; the frequency domain channel power spectrum DC component obtained by modulo squared is added to the estimated noise power; ^) is conjugated The result of the processing is divided by the result of the addition; after the fast Fourier transform is performed on the time domain signals of the two data areas to the frequency domain, the frequency domain signals of the two data areas are respectively separated from the result of the point division. After multiplying point by point, the result of the point multiplication is subjected to fast Fourier transform to the time domain, and the chip signal is estimated. According to another aspect of the present invention, a time division-synchronous code division multiple access signal detecting apparatus is provided. A time division-synchronous code division multiple access signal detecting apparatus according to the present invention includes: a signal separating unit, a channel estimating unit, a noise removing processing unit, a signal estimating unit, and a descrambling and despreading unit, wherein the signal separating unit is configured to receive the received signal The signal separates the training sequence signal that is not interfered by the data signal and the two data areas of the trained sequence signal. The channel estimation unit is configured to perform channel estimation on the separated training sequence signal to obtain time domain channel estimation. Result: a denoising processing unit, configured to perform denoising processing on two data area signals to obtain time domain signals of two data areas; and a signal estimating unit for using fast Fourier transform and inverse fast Fourier transform The time domain channel estimation result output by the channel estimation unit and the time domain signal of the two data areas output by the denoising processing unit perform signal estimation processing to estimate a chip signal; and a descrambling despreading unit for estimating the signal estimation unit The chip signal is descrambled and despread, and the detection result of all transmitted symbols is obtained. a soft demodulation unit, configured to perform soft demodulation on the detection result obtained from the descrambling despreading unit

5 Ρ27493 Send to the transmission channel. Preferably, the denoising processing unit specifically includes: an interference cancellation module and a smear processing module, wherein the interference cancellation module is configured to cancel the training sequence signal to the two data areas according to the time domain channel estimation result and the known training sequence signal The signal traverse processing module is configured to perform smearing processing on the two data area signals after interference cancellation to obtain time domain signals of two data areas. Preferably, when the zero-forcing algorithm is adopted, the signal estimating unit specifically includes: a first fast Fourier transform module, a second fast Fourier transform module, a point dividing module, and an inverse fast Fourier transform module, and a towel thereof a fast Fourier transform module, configured to perform fast Fourier transform on the time domain channel estimation result outputted by the channel estimation unit to the frequency domain, and output the obtained frequency domain channel estimation result to the point division module; a transforming module for performing fast Fourier transform on the time domain signals of the two data areas output by the denoising processing unit to the frequency domain, and outputting frequency domain signals of the two data areas to the point dividing module; a dividing module, configured to perform point division processing on the frequency domain signals of the two data regions obtained from the second fast Fourier transform module and the frequency domain channel estimation results obtained from the first Fourier transform module, and output points The result is added to the inverse fast Fourier transform module; the inverse fast Fourier transform module is used to perform the inverse fast Fourier transform on the point division result obtained from the point division module to the time domain, A chip count signal. Preferably, when the minimum mean square error algorithm is adopted, the signal estimating unit specifically includes: a first fast Fourier transform module, a second fast Fourier transform module, a modulo square module, an adding module, a conjugate processing module, a point division module, a point multiplication module, and an inverse fast Fourier transform module, where the first fast Fourier transform module is configured to perform fast Fourier transform on the time domain channel estimation result output by the channel estimation unit to the frequency domain, And outputting the obtained frequency domain channel estimation result to the modulo square module and the conjugate module; and the second fast Fourier transform module is configured to output the two data areas of the noise removing processing unit

6 Ρ27493 The domain signal is fast Fourier transformed into the frequency domain, and the obtained frequency domain signals of the two data areas are output to the point multiplication module; the modulo square module is used for the frequency domain obtained from the first fast Fourier transform module The channel estimation result is modulo squared, and the result of modulo squared is output to the adding module; the adding module is used for obtaining the DC component of the frequency domain channel power spectrum obtained from the modulo square module and the channel estimating unit. Estimating the noise powers, and outputting the added results to the point division module; the conjugate processing module for conjugate processing the frequency domain channel estimation results obtained from the first fast Fourier transform module, and The result after the yoke is output to the point division module; the point division module is used for dividing the result of the output of the conjugate processing module and the output of the addition module, and outputting the result of the point division to the point multiplication module; a module for multiplying a frequency domain signal of two data regions obtained from the second fast Fourier transform module by a point division result obtained from the point division module, and outputting the result of the dot multiplication An inverse fast Fourier transform module; an inverse fast Fourier transform module for performing a fast Fourier transform on the point multiplication result obtained from the point multiplication module to the time domain, and estimating the chip signal. The soft demodulation unit is configured to perform soft demodulation on the detection result obtained from the descrambling and despreading unit, and then send the result to the transmission channel. According to the solution provided by the present invention, the time slot data of the TD-SCDMA system is detected, and only the FFT and IFFT (Inverse Fast Fourier Transform, ) idling inverse Fourier transform are needed for the signal and the channel, plus some additional Auxiliary operation and descrambling despreading can be completed without complicated matrix inversion or Cholesky decomposition operation, and complex code activation detection operations are not required, which can greatly reduce the control and computational complexity of the system implementation. Other features and advantages of the invention will be set forth in the description in the description which follows. The objectives and other advantages of the invention will be realized and attained by the <RTI

P27493 BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In the drawings: FIG. 1 is a timing-synchronous code division multiple access signal detecting method according to a first embodiment of the method of the present invention.

2 is a schematic diagram of a time division-synchronous code division multiple access signal detection method according to Embodiment 2 of the present invention; FIG. 3 is a time division-synchronous code division multiple access according to Embodiment 1 of the apparatus according to the present invention; FIG. 4 is a schematic structural diagram of a time division-synchronous code division multiple access signal detecting apparatus according to Embodiment 2 of the apparatus according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention provides a method based on fast Fourier transform, considering that the complexity of the downlink time slot signal detection technology in the existing TD-SCDMA system is too high, and the control and complexity cost is too high in hardware implementation. The zero-forcing (ZF) and minimum mean square error (MMSE) chip-level signal detection scheme can greatly reduce the control and computational complexity of the system implementation. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. Method Embodiment 1 Firstly, a method provided by an embodiment of the present invention will be described in detail with reference to FIG. 1 and FIG. As shown in FIG. 1, FIG. 1 is a schematic flowchart of a time-division-synchronous code division multiple access signal detecting method according to Embodiment 1 of the present invention, which may specifically include the following steps: Step 101: Receive output from a matched filter The signal is first separated and separated.

128 midamble signals that are basically unaffected by data signals and two parts are affected by midamble signals

8 P27493 4 especially data signals (the first data area has a total of 367 chip data, including 15 chip data whose tail is interfered by the midamble signal; the second data area has 367 chip data, including the head interfered by the midamble signal 15 chip data). Step 102: Perform channel estimation on the midamble signal by using frequency domain estimation commonly used in the industry and inverse transform to the time domain to obtain a time domain channel estimation result. Step 103: Eliminate interference of the midamble signal on the tail of the first data area and the head of the second data area by using the time domain channel estimation result and the known midamble signal, that is, cancel 15 data chips at the end of the first data area. Interference of 15 data chips of the header of the second data area;

It can be seen that the matrix W becomes a cyclic matrix. Since the circulant matrix can be diagonalized using the DFT matrix:

9 P27493 H' = D ^H AD ( 3 )

D is the DFT matrix, ^ is the diagonal matrix, so that the FFT method can be used to estimate the signal s : s = D ^H {Dr'IDh) _{( 4 )} h is the first column, / represents the corresponding phase of the two vectors except. The following steps 105 to 108 use equations (3) and (4) to estimate the signal. Step 105: After filling the time domain channel estimation result with 0, the FFT is used to transform into the frequency domain (filling 0 to the same length as the data) to obtain the frequency domain channel estimation result. Step 106: Convert the two pieces of data after the smear processing into the frequency domain by using FFT, to obtain frequency domain signals of the two data areas. Step 107: The frequency domain channel estimation result of step 105 is respectively divided by the frequency domain signals of the two data areas of step 106, and the point division refers to the division of each frequency point result. Step 108: The point division result of the two data areas is respectively converted to the time domain by IFFT, and the data at this time has restored orthogonality, and the chip signal S is estimated. Step 109: After estimating the chip signal ^, since the orthogonality of the signals between the code channels is recovered, the descrambling despreading code of each code channel can be used to descramble and despread the chip signal ^, respectively The detection result of all transmitted symbols. Step 110: Perform soft demodulation on the detection result and send it to the transmission channel for corresponding processing. The second embodiment of the present invention is a detailed description of the ZF signal detection method based on the fast Fourier transform. Another method of the embodiment of the present invention, that is, the fast Fourier transform based MMSE signal detection method will be described in detail below with reference to FIG.

10 P27493 As shown in FIG. 2, FIG. 2 is a schematic flowchart of a time-division-synchronous code division multiple access signal detecting method according to Embodiment 2 of the method of the present invention, which specifically includes the following steps: Step 201: Midamble part of a matched filter output signal Separated from the data part, the midamble part is pure 128 pieces of chip data which are basically undisturbed by data, and the data part includes two data areas interfered by the midamble signal, and there are 367 pieces of chip data respectively. Step 202: The midamble signal performs channel estimation on the channel in the frequency domain, inversely transforms the noise into the time domain, and outputs the estimated noise power. Step 203: After the time domain channel estimation result is filled in 0, the FFT is transformed into the frequency domain (filling 0 to the same length as the data) to obtain a frequency domain channel estimation result. Step 204: Perform modulo squared on the frequency domain channel estimation result to obtain a frequency domain channel power word DC

Step 205: Add the DC component of the frequency domain channel power word and the noise power point by point. Step 206: Take a conjugate of the frequency domain channel estimation result of step 203. Step 207: The conjugate result of step 206 is divided by point by the addition result of step 205. Step 208: Perform interference cancellation on the separated two data regions according to the frequency domain channel estimation result estimated in step 203 and the known midamble signal, and the first data region needs to eliminate the interference of the last 15 chips. The two data areas need to eliminate the interference of the first 15 chips. Step 209: Superimpose the last 15 chip data of the two data areas to the first 15 chips. Step 210: Perform FFT on the two parts of the smeared data to the frequency domain. Step 211: The result of step 210 is multiplied by the point-by-point result of step 207. Step 212: Transform the point multiplication result IFFT of step 211 into the time domain, and the data at this time has restored orthogonality. Step 213: The solution of the IFFT result is solved by using the solution 4 and the despreading code of each code channel, and the detection result of all the transmitted symbols is obtained. Step 214: Perform soft demodulation on the detection result, and send the soft demodulated result to the transmission channel for subsequent processing.

11 P27493 When the time slot data of the TD-SCDMA system is detected by using the method provided by the embodiment of the present invention, the channel is converted into a cyclic matrix by processing the signal smear, and the orthogonality of the signal can be recovered by using mature FFT and IFFT operations; The signal of all transmitted symbols is obtained by descrambling and despreading the signal for restoring orthogonality; and no matrix inversion or Cholesky decomposition operation is required, and the complexity is low, which is convenient for control implementation; no code activation is required for each time slot signal The detection operation further reduces the complexity and improves the robustness of the system. According to an embodiment of the present invention, there is also provided a computer readable medium having stored thereon computer executable instructions for causing a computer or processor to perform, for example, when executed by a computer or processor Preferably, one or more of the above-described method embodiments can be performed in the processing of the steps shown in FIGS. 1 and 2. Apparatus Embodiment 1 The apparatus according to the embodiment of the present invention will be described in detail below with reference to FIGS. 3 and 4. As shown in FIG. 3, FIG. 3 is a schematic structural diagram of a time division-synchronous code division multiple access signal detecting apparatus according to Embodiment 1 of the present invention, which may specifically include: a signal separating unit, a channel estimating unit, a noise removing processing unit, The signal estimation unit and the solution 4 are particularly despreading units, wherein the denoising processing unit specifically includes: an interference cancellation module and a smear processing module; the signal estimation unit specifically includes: a first fast Fourier transform module, a second fast Fourier transform module, and a point division The module and the fast Fourier transform module, or the signal estimation unit specifically includes: a first fast Fourier transform module, a second fast Fourier transform module, a modulo square module, an add module, a conjugate processing module, a point division module, and a point multiplication Module and Fast Fourier Transform module. The various parts of the device are described in detail below. The signal separation unit performs signal separation on the received signal output from the matched filter, and separates 128 midamble signals that are substantially unaffected by the data signal and two data signals that are interfered by the midamble signal. The channel estimation unit performs channel estimation on the training sequence signal separated from the received signal, and outputs the obtained time domain channel estimation result to the signal estimation unit. The denoising processing unit performs denoising processing on the two data area signals to obtain time domain signals of the two data areas, and outputs the obtained time domain signals of the two data areas to the signal estimating unit. The denoising processing unit specifically includes: an interference cancellation module and a smear processing module, and the interference cancellation module cancels interference of the training sequence signal on the signals of the two data areas according to the time domain channel estimation result and the known training sequence signal, and eliminates interference The latter two data area signals are output to the trailing processing module, and the trailing processing module

12 P27493 The block performs tailing processing on the two data area signals after the interference cancellation, and obtains the time domain signals of the two data areas. The signal estimating unit estimates the chip signal by performing signal estimation processing on the time domain channel estimation result output by the channel estimation unit and the time domain signal of the two data areas output by the denoising processing unit by using the fast Fourier transform and the fast Fourier transform. The signal estimation unit specifically includes: a first fast Fourier transform module, a second fast Fourier transform module, a point division module, and an inverse fast Fourier transform module, where the first fast Fourier transform module performs the time domain channel estimation result output by the channel estimation unit Fast Fourier transform to the frequency domain, and output the obtained frequency domain channel estimation result to the point division module; the second fast Fourier transform module performs fast Fourier transform to the frequency domain of the time domain signals of the two data areas output by the denoising processing unit And the frequency domain signals of the two data areas obtained are output to the point division module. The dot division module performs point division processing on the frequency domain signals of the two data regions obtained from the second fast Fourier transform module and the frequency domain channel estimation results obtained from the first Fourier transform module, and outputs the point division result to the fast Fourier inverse The transform module; the inverse fast Fourier transform module performs the inverse fast Fourier transform to the time domain respectively from the two point division results obtained by the point division module, and estimates the chip signal to the solution 4 despreading unit. The descrambling despreading unit performs descrambling and despreading the chip signal estimated by the signal estimating unit, obtains detection results of all transmitted symbols, and outputs the detection result to the soft demodulating unit. The soft demodulation unit performs soft demodulation on the detection result obtained from the descrambling despreading unit, and then sends the detection result to the transmission channel for correlation processing. FIG. 4 is a schematic structural diagram of a time division-synchronous code division multiple access signal detecting apparatus according to Embodiment 2 of the present invention, wherein the channel estimation unit performs channel estimation while still performing channel estimation. When the estimated noise power is output, the signal estimating unit specifically includes: a first fast Fourier transform module, a second fast Fourier transform module, a modulo square module, an adding module, a conjugate processing module, a point dividing module, a point multiplication module, and a fast Fourier An inverse transform module, wherein the first fast Fourier transform module performs fast Fourier transform on the time domain channel estimation result output by the channel estimation unit to the frequency domain, and outputs the obtained frequency domain channel estimation result to the modulo square module and the conjugate module The modulo squaring module modulates the frequency domain channel estimation result obtained from the first fast Fourier transform module, and outputs the modulo squared result to the adding module; the adding module will obtain the modulo square module Frequency domain channel power i dc component and estimated noise power obtained from channel estimation unit point by point Canada, and the phase

13 P27493 The added result is output to the point division module; the conjugate processing module conjugates the frequency domain channel estimation result obtained from the first fast Fourier transform module, and outputs the conjugated result to the point division module; the point division module will The result output by the conjugate processing module is subjected to point division processing and the result of the addition module output, and the result of the point division is output to the point multiplication module; the second fast Fourier transform module outputs the two data areas of the denoising processing unit The domain signal is fast Fourier transformed into the frequency domain, and the obtained frequency domain signals of the two data areas are output to the point multiplication module; the frequency domain signals of the two data areas obtained from the second fast Fourier transform module are respectively obtained by the point multiplication module The point division result obtained from the point division module is multiplied point by point, and the result of the point multiplication is output to the inverse fast Fourier transform module; finally, the two point multiplication results obtained from the point multiplication module by the inverse fast Fourier transform module respectively Performing a fast Fourier transform to the time domain, estimating the chip signal to the descrambling and despreading unit. The specific implementation process of the device provided by the embodiment of the present invention has been described in detail in the foregoing method, and details are not described herein again. In addition, the descrambling despreading and soft demodulation processing in the embodiments of the present invention have mature solutions in the prior art, and will not be discussed in detail herein. In summary, the embodiment of the present invention provides a detection scheme for a time division-synchronous code division multiple access signal, and when the time slot data of the TD-SCDMA system is detected by using the method and apparatus of the embodiment of the present invention, the signal is tailed. The process converts the channel into a cyclic matrix, and the orthogonality of the signal can be recovered by using mature FFT and IFFT operations; the detection signal of the transmitted symbol used is obtained by descrambling and despreading the signal for restoring orthogonality; and no matrix inversion or Cholesky decomposition operation, low complexity, easy to control implementation; no need to perform code activation detection on each time slot signal, further reducing complexity and improving system robustness. In addition, the implementation of the present invention does not modify the system architecture and the current processing flow, is easy to implement, facilitates promotion in the technical field, and has strong industrial applicability. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device to store them in a storage device for execution by the computing device. Alternatively, they may be fabricated into individual integrated circuit modules, or a plurality of modules or steps may be fabricated into a single integrated circuit module. Thus the invention is not limited to any specific combination of hardware and software.

14 P27493 The above is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or within the technical scope disclosed by the present invention. Alternatives are intended to be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the claims.

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Claims

A method for detecting a time-division-synchronous code division multiple access signal, wherein the method comprises: Step J _rr : .2l A: After obtaining a channel estimation from a training sequence signal separated from a received signal, Domain channel estimation result;

Step B: Denoising the signals of the two data areas to obtain time domain signals of the two data areas;

Step C: Using a fast Fourier transform and an inverse fast Fourier transform to perform signal estimation processing on the time domain channel estimation result and the time domain signals of the two data regions, and estimating the chip signal; Step D: evaluating the code The slice signal is descrambled and despread, and the detection result of all transmitted symbols is obtained;

Step E: The obtained detection result is soft demodulated and then sent to the transmission channel. The method according to claim 1, wherein the step B specifically includes:

Step B1: canceling interference of the training sequence signal on the signals of the two data areas according to the time domain channel estimation result and the known training sequence signal;

Step B2: Perform tailing processing on the two data area signals after interference cancellation to obtain time domain signals of the two data areas. The method according to claim 2, wherein in step B1, the interference of the training sequence signal on the signals of the two data regions is eliminated, and the received signal in the following form is obtained: k

r = = Hs + n = K '■■

h

Where r is the first data zone signal or the second data zone signal after the interference of the training sequence is eliminated, H is the Toeplize matrix with the same diagonal element, s is the chip signal sent by the originating end, and n is the noise interference.

16 P27493

4. The method according to claim 3, wherein in step B2, the smear processing is performed according to the following formula:

Where r' is the first data zone signal or the second data zone signal after trailing processing, Η' is a cyclic matrix, and η' is a noise dry 4 especially. The method according to any one of claims 1 to 4, wherein, when the zero-forcing algorithm is employed, the step C specifically includes:

Performing fast Fourier transform on the time domain channel estimation result to the frequency domain to obtain a frequency domain channel estimation result;

Performing fast Fourier transform on the time domain signals of the two data areas to the frequency domain to obtain frequency domain signals of the two data areas;

The frequency domain signals of the two data regions subjected to the fast Fourier transform are separately selected from the frequency domain channel estimation results; the obtained point division results are respectively subjected to inverse fast Fourier transform to the time domain, and the chip is estimated. signal.

The method according to any one of claims 1 to 4, wherein, when a minimum mean square error algorithm is employed, and the estimated noise power is also output while performing channel estimation in the step, the step C specifically includes:

Performing modulo square and conjugate processing on the frequency domain channel estimation results respectively;

a frequency domain channel power spectrum DC component obtained by modulo squared and an estimated noise power phase force port;

^! Dividing the result of the conjugate processing and the result of the addition;

17 P27493 After the fast Fourier transform is performed on the time domain signals of the two data areas to the frequency domain, the frequency domain signals of the two data areas are respectively multiplied by the point division result, and the result of the point multiplication is quickly performed. Fourier inverse transforms into the time domain to estimate the chip signal.

A time division-synchronous code division multiple access signal detecting apparatus, the apparatus comprising: a signal separating unit, a channel estimating unit, a noise removing processing unit, a signal estimating unit, and a descrambling and despreading unit, wherein

The signal separating unit is configured to separate the received signal into two data areas that are not subjected to the training signal of the data signal and the training sequence signal;

The channel estimation unit is configured to perform channel estimation on the separated training sequence signal to obtain a time domain channel estimation result;

The denoising processing unit is configured to perform denoising processing on two data area signals to obtain time domain signals of two data areas;

The signal estimation unit is configured to use a fast Fourier transform and an inverse fast Fourier transform to output a time domain channel estimation result of the channel estimation unit and a time domain of two data regions output by the denoising processing unit The signal is subjected to signal estimation processing, and the chip signal is estimated; the descrambling and despreading unit is configured to perform descrambling and despreading the chip signal estimated by the signal estimating unit, to obtain a detection result of all the transmitted symbols;

The soft demodulation unit is configured to perform soft demodulation on the detection result obtained from the descrambling and despreading unit, and then send the result to the transmission channel.

The apparatus according to claim 7, wherein the denoising processing unit comprises: an interference cancellation module and a smear processing module, where

The interference cancellation module is configured to eliminate interference of the training sequence signal on the signals of the two data areas according to the time domain channel estimation result and the known training sequence signal;

The smear processing module is configured to perform smearing processing on the two data area signals after interference cancellation to obtain time domain signals of the two data areas.

The device according to claim 7 or 8, wherein the signal estimating unit comprises: a first fast Fourier transform module, a second fast Fourier transform module, Point division module and inverse fast Fourier transform module, wherein

The first fast Fourier transform module is configured to perform fast Fourier transform on the time domain channel estimation result output by the channel estimation unit to the frequency domain, and obtain the obtained frequency domain channel.

18 Ρ27493 The estimated result is output to the point dividing module;

The second fast Fourier transform module is configured to perform fast Fourier transform on the time domain signals of the two data areas output by the denoising processing unit to the frequency domain, and obtain frequency domains of two data regions. Signal output to the point division module;

The point dividing module is configured to perform frequency domain signals of two data regions obtained from the second fast Fourier transform module and frequency domain channel estimation results obtained from the first Fourier transform module, respectively Point dividing processing, and outputting the point division result to the inverse fast Fourier transform module; the inverse fast Fourier transform module is configured to perform inverse fast Fourier transform on the point division result obtained from the point division module In the time domain, the chip signal is estimated. The device according to claim 7 or 8, wherein the signal estimation unit comprises: a first fast Fourier transform module, a second fast Fourier transform module, and a minimum mean square error algorithm, a modulo square module, an addition module, a conjugate processing module, a point division module, a point multiplication module, and an inverse fast Fourier transform module, wherein

The first fast Fourier transform module is configured to perform fast Fourier transform on the time domain channel estimation result output by the channel estimation unit to the frequency domain, and output the obtained frequency domain channel estimation result to the fetching a modular square module and the conjugate module;

The second fast Fourier transform module is configured to perform fast Fourier transform on the time domain signals of the two data areas output by the denoising processing unit to the frequency domain, and obtain frequency domains of two data regions. Signal output to the point multiplication module;

The modulo squaring module is configured to perform modulo squaring on the frequency domain channel estimation result obtained from the first fast Fourier transform module, and output the modulo squared result to the adding module;

The adding module is configured to add a frequency domain channel power spectrum DC component obtained from the modulo square module and an estimated noise power obtained from the channel estimating unit, and output the added result to the point dividing module;

The conjugate processing module is configured to perform conjugate processing on the frequency domain channel estimation result obtained from the first fast Fourier transform module, and output the conjugated result to the point dividing module;

The point division module is configured to perform point division processing on a result output by the conjugate processing module and a result output by the addition module, and output a result of the point division to the point multiplication module;

19 P27493 The point multiplication module is configured to multiply the frequency domain signals of the two data regions obtained from the second fast Fourier transform module and the point division result obtained from the point division module, and multiply the points by points. The result is output to the inverse fast Fourier transform module;

The inverse fast Fourier transform module is configured to perform inverse fast Fourier transform on the point multiplication result obtained from the point multiplication module to the time domain, and estimate a chip signal;

20 Ρ27493