WO2010018620A1 - Plasma display device - Google Patents

Abstract

In order to assure a sufficient address drive period and a sustain drive period, a plasma display device performs control for simultaneous parallel execution of an address drive operation of one display line in each of subfields (SF1 to SF5) constituting one field (1F) and a sustain drive operation in at least one of display lines where the address drive operation has been already performed. That is, the address drive operation is performed by a skip scan in a unit of a predetermined display lines and the sustain drive operation is controlled so that the sustain drive period lengths are different between adjacent display lines.

Description

Plasma display device

The present invention relates to a flat display device such as a display device (plasma display device: PDP device) including a plasma display panel (PDP), and more particularly to a driving method and a driving circuit (driver) for gradation display.

Flat display devices using flat display panels, such as PDP devices, have been replaced by conventional cathode ray tubes and are being put into practical use over a wide range from small to large, and are becoming popular. Particularly in large fields, PDPs have been commercialized as the mainstream of popularization by utilizing the characteristics of the principle configuration. In order to promote further widespread use in the future, it is desired to further reduce the price of the device itself, further improve display performance, and further improve other functions. Furthermore, there is an increasing demand for reducing the impact on various environmental loads, including EMI, etc., and further reduction of these is required for widespread use in general households in the future. ing.

The gradation display method (driving method) in the conventional mainstream PDP apparatus is based on a subfield method, an ADS (address display separation) method, or the like. In this method, a reset driving period and address driving are performed in a field (also referred to as a frame) associated with a PDP screen (display area) and display time, and a plurality of subfields (also referred to as subframes) constituting the field. The period has a sustain (sustain) driving period separated in time. An arbitrary gradation display is performed by controlling the number of pulses (sustain voltage pulses) applied to the electrodes (display electrodes) in the sustain drive period. One field (field period) needs to be repeated at, for example, 60 Hz or more in order to prevent display flickering. For this reason, the time allowed for one field is limited to, for example, within 16.7 ms (milliseconds). It has been.
JP 2007-171285 A

The conventional technology of the PDP device (gradation display method based on the subfield method and ADS method) performs control in a time-series manner with drive timings that are clearly divided into drive periods such as reset, address, and sustain. Therefore, although there is a feature that the control is relatively easy, on the other hand, it is necessary to secure each time for a series of time series driving, and there is a disadvantage that the time of each subfield becomes long.

In addition, since there is a time restriction as described above (time of one field: within 16.7 ms), if the time of the subfield (subfield period) becomes long, the number of subfields constituting the field decreases. For this reason, there is a problem that a sufficient number of gradations cannot be obtained.

Furthermore, if an attempt is made to prioritize and secure the number of subfields in order to secure the number of gradations, the time allocated to each drive in each drive period such as reset, address, and sustain becomes insufficient. As a result, the operation margin and the driving stability are deteriorated, and a problem that a problem such as erroneous display easily occurs.

Also, from another angle, in the ADS system, in the performance required for the driving power source required for each driving, the driving period is clearly divided as described above, and is supplied from each driving power source. The period during which the current flows is also clearly divided. As a result, there is a disadvantage that the fluctuation component of the current value becomes large. If the current fluctuation component (ripple current) of the power supply is large, it is necessary to provide a control circuit such as a stabilization circuit that covers the maximum value (peak current) of the fluctuation component and a circuit material of a wiring system with a large capacity. Complicated, expensive and disadvantageous in cost. Furthermore, the increase in the peak current component increases the emission of noise signals from the drive circuit system, which can easily cause malfunctions in circuit control, and the influence of the radiation of electromagnetic field energy on the surrounding environment is large. There is a problem that it is easy to become.

Therefore, with the aim of solving the above problems, the present applicant has previously proposed a new driving method as disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2007-171285).

In Patent Document 1, the sustain discharge drive after address drive is continuously performed for each scan line by independent control for each scan line, and the sustain discharge drive and address drive between different scan lines are simultaneously performed in parallel. By the operation to be performed in this manner, the drive method has improved the time utilization efficiency to the ultimate by eliminating the need for an independent sustain discharge period as in the prior art. However, in the configuration of the drive circuit, a cost problem remains to be realized due to the necessity of a high breakdown voltage drive element in which a scan voltage and a sustain discharge voltage are added for each scan electrode line.

The present invention has been made in view of the above problems, and its main object is related to a PDP device, and proposes a new method capable of solving the above-described problems, and provides gradation display performance and panel drive characteristics. It is to provide a technology that can realize improvement and the like.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows. In order to achieve the above object, a typical embodiment of the present invention is a PDP device including a PDP and a PDP drive circuit device (circuit unit) for driving and controlling the PDP, and has the following configuration. It is characterized by having.

The present invention provides a new driving method capable of improving various display performances by improving the driving circuit and driving method of the PDP device, and a PDP device to which the driving method is applied.

The PDP apparatus of this embodiment has the following configuration, for example. The PDP device includes a plurality of first electrodes (Y electrodes) and second electrodes (X electrodes) extending in a first direction, and a plurality of third electrodes (address electrodes) extending in a second direction intersecting the first direction. Each of the plurality of first electrodes and the second electrode is composed of a pair of first and second electrodes adjacent to each other, and each of the plurality of display lines and each of the plurality of third electrodes A PDP having a display cell in an intersecting region, a first drive circuit that drives the plurality of first electrodes, a second drive circuit that drives the plurality of second electrodes, and the plurality of second electrodes as a circuit unit. A third drive circuit that drives the three electrodes; and a control circuit that controls the first, second, and third drive circuits.

And this PDP device, together with an operation (address) for applying a third voltage to the third electrode to be selected at every predetermined timing (T) in order to select the display cell and start discharging, In order to maintain the discharge of the display cell while performing the address driving operation for performing the scanning operation of applying the first voltage to the first electrode or the second electrode of the display line to be selected, A sustain driving operation is performed in which a second voltage is applied to a pair of the first electrode and the second electrode adjacent to each other in one or more display lines that have been subjected to the address driving operation among non-selected display lines. Thereby, the control circuit controls each of the drive circuits so that the address drive operation and the sustain drive operation are executed in parallel. The first and second electrodes are used for both maintenance and scanning.

In the PDP apparatus, the scanning operation in the address driving operation is performed by interlaced scanning in units of a predetermined number of display lines (g) with respect to an array of a plurality of display lines on the screen of the panel. The control circuit may be configured so that the number (SN) of applying the pulse of the second voltage in the sustain driving operation can be different between all adjacent display lines in the plurality of display lines. The drive circuit is controlled.

More specifically, the simultaneous and parallel driving, for example, scans (addresses), for example, the first electrode of the first line at a first timing, and then at a second timing, the predetermined number of times from the first line. (G) The second electrode of the second line jumped in units is scanned (addressed) and simultaneously the first electrode of the first line is maintained and driven. Next, at the third timing, the first electrode of the third line jumped from the second line by a predetermined number (g) is scanned (addressed) and at the same time, the second electrode of the first and second lines is scanned. And so on.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. According to a typical embodiment of the present invention, it is possible to provide a new system that can solve the above-described problems related to a PDP apparatus, and can realize improvement in gradation display performance and panel drive characteristics.

In particular, as a PDP device, a simple and low-cost drive circuit configuration enables address drive and sustain drive to be performed at the same time, thereby ensuring a sufficient address drive period and sustain drive period. The gradation display performance is improved, enabling a brighter, more vivid and smooth display.

It is a figure which shows an example of the basic structure of PDP with which the PDP apparatus of Embodiment 1 of this invention is provided. FIG. 3 is a diagram showing a field configuration in a first basic configuration of the driving method according to the first embodiment. It is a figure which shows about 1st subfield (SF1) among the subfield structures in the 1st basic composition of the drive system of Embodiment 1. FIG. It is a figure shown about 2nd subfield (SF2) among the subfield structures in the 1st basic composition of the drive system of Embodiment 1. FIG. It is a figure shown about the 5th subfield (SF5) among the subfield structures in the 1st basic composition of the drive system of Embodiment 1. FIG. FIG. 10 is a diagram showing a field configuration in a second basic configuration of the driving method according to the first embodiment. It is a figure which shows about 1st subfield (SF1) among the subfield structures in the 2nd basic composition of the drive system of Embodiment 1. FIG. It is a figure shown about 2nd subfield (SF2) among the subfield structures in the 2nd basic composition of the drive system of Embodiment 1. FIG. It is a figure shown about the 5th subfield (SF5) among the subfield structures in the 2nd basic composition of the drive system of Embodiment 1. FIG. 1 is a diagram illustrating a configuration of a PDP device according to a first embodiment. FIG. 3 is a diagram illustrating a circuit configuration example of a Y electrode and an X electrode driver IC in the PDP device according to the first embodiment. 6 is a diagram illustrating an example of a first drive waveform in Embodiment 1. FIG. 6 is a diagram illustrating an example of a second drive waveform in the first embodiment. FIG. It is a figure shown about the field structure in the drive system of Embodiment 2 of this invention. It is a figure shown about the 1st subfield (SF1) among the subfield structures in the drive system of Embodiment 2. It is a figure shown about the 2nd subfield (SF2) among the subfield structures in the drive system of Embodiment 2. FIG. It is a figure shown about the 6th subfield (SF6) among the subfield structures in the drive system of Embodiment 2. FIG. It is a figure shown about the 11th subfield (SF11) among the subfield structures in the drive system of Embodiment 2. It is a figure which shows the structure of the PDP apparatus of Embodiment 2. FIG. It is a figure which shows the wiring of Y electrode and X electrode driver IC with respect to PDP in the PDP apparatus of Embodiment 2, and a connection structure. FIG. 6 is a diagram illustrating a circuit configuration example of a Y electrode and an X electrode driver IC in the PDP device according to the second embodiment. FIG. 10 is a diagram illustrating a connection configuration example of a driver IC and a control logic circuit in the PDP device according to the second embodiment. It is a figure which shows the case of SF1 as an example of the drive waveform in Embodiment 2. FIG. It is a figure which shows the case of SF2 as an example of the drive waveform in Embodiment 2. FIG. It is a figure which shows the case of 1SUS of SF1 as a drive waveform control timing in Embodiment 2. FIG. It is a figure which shows the case of 2SUS of SF1 as a control timing of the drive waveform in Embodiment 2. FIG. It is a figure which shows the case of 1024SUS of SF1 as a drive waveform control timing in Embodiment 2. FIG. It is a figure shown about the field structure in the drive system of Embodiment 3 of this invention. It is a figure shown about the 1st subfield (SF1) among the subfield structures in the drive system of Embodiment 3. It is a figure shown about the 2nd subfield (SF2) among the subfield structures in the drive system of Embodiment 3. It is a figure shown about the 6th subfield (SF6) among the subfield structures in the drive system of Embodiment 3. It is a figure shown about the 12th subfield (SF12) among the subfield structures in the drive system of Embodiment 3. FIG. 10 is a diagram illustrating a wiring and connection configuration of a Y electrode and an X electrode driver IC with respect to a PDP in the PDP device of the third embodiment. It is a figure which shows the case of SF1 as an example of the drive waveform in Embodiment 3. FIG. It is a figure which shows the case of 1SUS of SF1 as a drive waveform control timing in Embodiment 3. FIG. FIG. 10 is a diagram illustrating a circuit configuration example of a Y electrode and an X electrode driver IC in the PDP device according to the fourth embodiment. FIG. 10 is a diagram illustrating a connection configuration example between a driver IC and a control logic circuit in a PDP device according to a fourth embodiment. FIG. 16 is a diagram illustrating a case of SF1 of 1 SUS as a drive waveform control timing in the fourth embodiment. FIG. 16 is a diagram showing a case of 2SUS of SF1 as a drive waveform control timing in the fourth embodiment. FIG. 16 is a diagram illustrating a case of SF1 496SUS as a drive waveform control timing in the fourth embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The PDP apparatus according to the first embodiment of the present invention, its drive circuit, drive system, and the like will be described with reference to FIGS. The first embodiment shows a basic and fundamental configuration.

<1-1: PDP>
FIG. 1 shows an example of a basic structure of a PDP 10 provided in the PDP apparatus of the present embodiment. Only a portion corresponding to a collection of cells of each color R (red), G (green), and B (blue) associated with a pixel is schematically shown. This PDP 10 is a three-electrode type, a surface discharge / AC drive type, for example, a stripe-shaped partition wall structure. The areas Cr, Cg, and Cb are associated with cells (light emitting areas) of each color. For the sake of explanation, as shown in the figure, the x direction (first direction: horizontal direction in the screen (display line direction)), y direction (second direction: vertical direction in the screen (display column direction)), z direction (Third direction: direction perpendicular to the screen (thickness) direction).

The present PDP 10 is configured by combining two structures (11, 12) mainly including two glass substrates 1, 5 on the front side and the back side. The first structure 11 and the second structure 12 are overlapped and their outer peripheral portions are sealed, and the region between the structures is evacuated and filled with discharge gas, thereby forming a discharge space 30 inside. This PDP 10 is configured.

In the first structure (front substrate structure) 11, a plurality of pairs of display electrodes (X electrodes, Y electrodes) used for display discharge (sustain discharge) are formed on the glass substrate 1 in parallel with the x direction. Has been. The display electrode includes an X electrode (first electrode) (represented by X) and a Y electrode (second electrode) (represented by Y) that are used for both sustain drive and scan drive. Both X and Y electrodes can be used for scanning driving. The display electrode (X, Y) is composed of, for example, a transparent electrode 2a and a bus electrode 2b. The transparent electrode 2a forms a cell discharge gap by a pair. The bus electrode 2b is linear and connected to the drive circuit side. A line (display line) is formed by adjacent pairs of X and Y. The display electrodes (X, Y) are covered with the dielectric layer 3 and the protective layer 4.

In the second structure (rear substrate structure) 12, a plurality of address electrodes (represented by A) for address driving are formed on the glass substrate 5 in parallel with the y direction intersecting the x direction. The address electrode A is covered with, for example, a dielectric layer 7, and striped partition walls (ribs) 8 extending in the y direction, for example, are formed on the dielectric layer 7. The barrier rib 8 partitions the discharge space 30 corresponding to the cell (discharge region). In the region between the barrier ribs 8 on the dielectric layer 7, phosphors 9 (9 r, 9 g, 9 b) for light emission of R, G, and B are exposed for each display column so as to be exposed to the discharge space 30. It is formed separately.

, Not only the structure of the PDP 10 but also various detailed structures are possible depending on the driving method. For example, it is of course applicable to a two-electrode type / AC drive type PDP. For example, a lattice-shaped partition wall 8 structure including a partition wall portion extending in the x direction is also possible. For example, a so-called ALIS method is also possible. In this case, a display line is constituted by a pair of all adjacent display electrodes (X, Y), and an image displayed on the screen includes a field for driving odd lines and an even line. Displayed by interlaced driving with the driving field.

<1-2: Drive system (1)>
FIGS. 2 to 3 schematically show a basic configuration (principal configuration) in driving of the entire field (represented by F) and subfield (represented by SF) in the PDP apparatus and drive system of the first embodiment. ing. In FIG. 2, in order to explain the principle operation of the present system, the configuration of lines (represented by L), groups (represented by G), regions (represented by B), and driving in the fields (F) and SF. An outline of timing is shown. FIG. 3 shows the drive timing of each SF. # Indicates an identification number.

FIG. 2 shows a case where the line (L) group constituting the display area (screen) of the PDP 10 has 20 lines L1 to L20 to be driven. In this case, the gradation display driving method is a case where the number of sustain driving numbers (SN) regarding the sustain driving is five (SN: 1, 2, 4, 8, 16). In this case, the number of SFs constituting one field (F) is five (SF: SF1 to SF5). The gradation expression is based on a power of 2.

The number of sustain drives (SN) is the number of times of application of pulses (sustain voltage pulses) in the sustain drive in SF and line units (SUS number), and is associated with time, brightness, etc. due to sustain discharge light emission.

Since there are five types of sustain drive numbers (SN), 32 gradation display by the power of 2 is possible. Further, in order to realize five types of SNs, a five-divided configuration in which 20 lines of a screen are divided into five groups (also referred to as divided groups, drive groups, etc.) consisting of a plurality of lines dispersed by interleaving G: G1 to G5 To drive. The number of divided groups and interlaced scanning units are 5, and the number of lines constituting one group is 4. The group G is a unit of division related to the sustain drive, and a predetermined SN is associated with each group G.

The groups G1 to G5 divided in accordance with the five types of sustain drive numbers SN are assigned to the lines L1 to L20 from the top of the screen for each line from the top. For example, the first line L1 belongs to the first group G1, the second line L2 belongs to the second group,..., The fifth line L5 belongs to the fifth group G5. L6 is assigned as the first group, and so on. For example, the first group G1 is composed of four lines L1, L6, L11, and L16 dispersed by 5-line jumping.

The scanning operation is performed by interlaced scanning in units of a predetermined number of lines with respect to the arrangement of a plurality of lines on the screen. Control is performed so that the number of sustain drives SN in the sustain drive operation can be made different between all adjacent lines.

For all 20 lines on the screen, there are four areas B: B1 to B4 that are divided into 5 groups as areas (B) consisting of adjacent lines. The region B is composed of a set of five types of lines belonging to G: G1 to G5 in adjacent lines. For example, the first region B1 is composed of five adjacent lines L1 to L5.

In such a configuration of group G, SF1 to SF5 with a time of 1SF: 3.333 ms are equally allocated to a drive time of 1F: 16.667 ms, and driving for each SF is performed.

2, the vertical line indicates the reset drive timing, the circle indicates the scan drive timing (address drive timing), and the horizontal line indicates the sustain drive timing and period. Reset is performed at the beginning of the SF for all lines. Scanning (addressing) is performed in order of group G and in line order for each group G. The sustain drive is performed in a period of SN of the group G unit immediately after scanning (address).

FIG. 3A shows the configuration of SF1 (first SF of 1F), FIG. 3B shows the configuration of SF2 (next SF), and SF3 to SF4 are hereinafter omitted, and FIG. The structure of SF5 (the last SF of 1F) is shown. More specifically, each SF is composed of three types of driving, namely, reset driving (indicated by R), address driving (indicated by A), and sustain driving (indicated by S). Each drive timing (unit of time) (represented by T) is time-controlled by T0 to T21, for example.

In FIG. 3A, in the first driven SF1, reset driving R is performed for all lines (L1 to L20) at the leading timing T0. Thereby, the state of all the cells is set to the initial state all at once. The same applies to the subsequent SF2 to SF5, and the reset drive R is performed at T0. This period (T0) is referred to as a reset driving period (represented by Tr). Tr is, for example, 0.1 ms.

After the reset drive R (Tr), a period in which the operations of the address drive A (including the scan drive) and the sustain drive S are sequentially performed for each line is entered. The period (T1 to T21) is referred to as an address / sustain drive period (represented by Tas). Tas is, for example, 3.233 ms.

In the address driving A, the selection operation (scanning) for the line by the display electrode (X, Y) pair and the selection operation (address) for the address electrode A are performed at the same timing for the cell to be selected. That is, the application of a pulse (scanning voltage pulse) to the X electrode or the Y electrode and the application of a pulse (address pulse) to the address electrode A are performed at the same timing. In the sustain drive S, a sustain discharge operation is performed on the line selected by the display electrode (X, Y) pair for the cell selected by the address drive A. That is, the application of alternately inverted pulses (sustain voltage pulses) to the X electrode and Y electrode of the line is repeated for SN.

In the period Tas of SF1, driving is started from G1 in the order of G1 to G5 in the above five types of groups G1 to G5. In the first G1, address drive A is continuously performed for the lines L1, L6, L11, and L16. Therefore, address drive A is first performed on L1 at timing T1 (first timing in Tas). Thereafter, at the next T2, address drive A is performed for L6, which is a line (after 5 lines) jumped from L1 in units of 5 lines. Similarly, address drive A is performed for L11 at T3 and L16 at T4. This completes the address drive A for all the lines of G1. Thus, the number of interlaced scanning units is adjusted to a value equal to 5 which is the number of divided groups. Thereby, it is possible to sequentially drive the lines of each group without missing.

Next to the driving of the group G1, the address driving A for the next group G2 (L2, L7, L12, L17) is started from the timing T5. By performing interlace scanning every 5 lines in the same manner from L2 adjacent to (below) the previous L1, address driving A to all the lines of G2 is completed at T5 to T8.

Similarly, G3 (L3, L8, L13, L18) is driven at T9 to T12, G4 (L4, L9, L14, L19) is driven at T13 to T16, and G5 (L5, L10, L19, T20 to T20). L15, L20) are driven. At L20 of the last T20, address drive A for all lines is completed.

One of the features is the address drive A based on the interlaced scanning. Apart from that, a further feature is that the sustain drive S is continued in parallel with the timing immediately after the address drive A for the line for which the address drive A has been completed at a certain timing (simultaneously with the operation of other lines). ) To do. In addition, the number of times (SN) of the sustain drive S is controlled to be different for each group G. In SF1, according to the order (G1 to G5) of the group in which the address drive A is started, for SN, for example, G1: 16 times, G2: 8 times, G3: 4 times, G4: 2 times, G5: 1 times, etc. In this way, the method is set by a power of 2.

Supplementally, as a characteristic operation, L6 is address-driven A at T2, and at the same time, the sustain drive S is simultaneously performed in parallel with L1 that has already been address-driven A at T1. Similarly, address drive A is performed on L11 at T3, and at the same time, sustain drive S is simultaneously performed on L1 and L6 that have already been addressed at T1 and T2. Further, when viewed from one line L, the address drive A is performed at the timing T of the interlaced scanning, and each sustain drive S is performed at the subsequent timing corresponding to the predetermined SN. Such an operation (address drive A + sustain drive S) is repeated until the necessary timing (T21).

At the timing T21 at the end of SF1 (the last in Tas), only the sustain drive S for the last line L20 of the address drive A is performed, and all the operations in the periods Tas and SF1 are completed as described above.

Next, the driving of SF2 shown in FIG. 3B is started, and each driving is performed by the reset driving period Tr and the address / sustain driving period Tas basically in the same manner as SF1 (FIG. 3A). As one of the characteristics, in SF2, the order of the group that performs address driving A with Tas is different from the order in SF1. For example, in SF2, the address drive A is started in the order of G2, G3, G4, G5, and G1 (a form in which the start group is shifted backward by one and after the final group (G5) returns to the first (G1)). That is, at T1 of SF2, address drive A is started from L2 of G2. In accordance with this, the number of sustain drives (SN) for each group is set as G2: 16 times, G3: 8 times, G4: 4 times, G5: 2 times, and G1: 1 times. That is, the number (SN) of sustain driving S for each line of SF2 is different from that of SF1. Specifically, the driving contents are shifted by one line between SF1 and SF2.

Thereafter, similarly in SF3, SF4, and SF5, driving is performed by changing the order of the groups in which the address driving A is started between different SFs and assigning different SNs to the respective groups. For example, driving is performed in order from G3 in SF3, G4 in SF4, and G5 in SF5. When the driving of SF5 shown in FIG. 3C is finished, the driving of one field is finished.

As described above, at the end of one field, the above five types of sustain drive numbers (SN: 16, 8, 4, 2, 1) are evenly distributed to all the groups G1 to G5 (FIG. 2). . For example, in L1 of G1, SN is 16, 1, 2, 4, 8 in order from SF1 to SF5. As a result, 32 (2 to the 5th power) gradation display drive, which is the number (31) plus 1 (black display portion) obtained by adding these SNs, is enabled for all lines. That is, by selecting ON / OFF of the sustain drive S at each timing T of each line L (cell) of each SF of the field, gradation display in 32 stages is possible.

As described above, when the sustain drive number SN of each drive group is set as a continuous numerical value from a small power value of 2 by zero and a natural number N, how to determine the number of groups at this time is as follows. It seems to be. That is, in relation to the maximum number of gradations (K) determined by the addition of the number of pulses of the sustain drive S within a certain driving period (field), the natural number N is 2 with respect to the maximum number of gradations (K). By selecting a value equal to the minimum N when K is larger than the Nth power (K <2 to the Nth power), the necessary minimum number of groups can be determined. In the present example, the maximum number of gradations due to the addition of SN is 31, the fifth power of 2 is 32, and the necessary minimum number of groups is N = 5.

If the sustain drive number SN of each drive group is set to include values other than the above (other than consecutive numbers from small to large powers of 2 by zero and natural number N), This is not always the minimum number of groups required.

Further, in this example, in each SF: SF1 to SF5, each timing (drive time unit) is set to T21. It is also possible to appropriately increase the number of sustain drives (SN) by further increasing the number of timings (T). In that sense, the degree of freedom with respect to the settable number of gradation display driving numbers is great.

<1-3: Drive system (2)>
Next, in FIGS. 4 to 5, the second basic configuration relating to the field and the SF based on the basic configuration of the driving method described above is similarly shown. FIG. 4 shows the configuration of the field, and FIG. 5 shows the configuration of each SF. In the second basic configuration, for the case of 22 lines, which is two more than the number of lines (20) in the basic configuration described above, five types of sustain drive numbers (SN) are similarly assigned, and five groups G1. Through G5 and 1F are driven by the configuration of 5SF (SF1 to SF5), 32 gradation display is realized.

As shown in FIG. 4, when groups G1 to G5 are assigned in order from the top to the arrangement of all lines L1 to L22, areas B1 to B4 (L1 to L20) are the same as the first basic configuration (FIG. 2). Although the same, for example, only the groups G1 and G2 are allocated to the remaining two lines L21 and L22, thereby newly generating a region B5 different from the other regions.

In this case, how to drive the new area B5 becomes an issue, and the details are shown in FIG. Since the number of lines is 22, the number of timings (T) in the period Tas needs to be 22 plus 1 at least 23.

Then, as shown in FIG. 5, as driving for the lines L21 and L22, each driving is performed as included in the groups G1 and G2 of the region B5 in each SF. L21 is included in G1, and L22 is included in G2. For example, in SF1 shown in FIG. 5A, SN = 16 is assigned to L21 of G1, and SN = 8 is assigned to L22 of G2. In SF2 shown in FIG. 5B, SN = 1 is assigned in L21 of G1, and SN = 16 is assigned in L22 of G2. Similarly, in SF5 shown in FIG. 5C, SN = 8 is assigned to L21 of G1, and SN = 4 is assigned to L22 of G2. As described above, the region B5 (the region remaining when all lines are divided by the number of groups) is handled as being included in the groups G1 and G2 as in the other regions B1 to B4. The number of sustain drives (SN: 16, 8, 4, 2, 1) is equally distributed to the area B5, thereby enabling 32 gradation display driving as with the lines of other areas.

<1-4: PDP device>
Next, FIGS. 6 to 7 show the configuration of the PDP apparatus that realizes the above-described gradation driving method in the first embodiment. FIG. 6 shows a configuration of main parts including a basic PDP and a PDP drive circuit device in the PDP device. FIG. 7 shows a configuration example of the driver IC of the display electrode (X, Y).

In FIG. 6, on the address electrode A side, an address electrode drive circuit for applying an address voltage waveform (address pulse) for each address electrode A is provided as an address driver IC (Da) 130 for each of a plurality of circuits (for each of a plurality of electrodes). ) Integrated and connected. For the display electrodes (Y electrode, X electrode), there are circuits (X electrode drive circuit, Y electrode drive circuit) for applying a scan voltage waveform (scan pulse) and a sustain voltage waveform (sustain pulse) for each electrode. These are integrated for each of a plurality of circuits (each of a plurality of electrodes) and connected as a Y electrode driver IC (Dy) 110 and an X electrode driver IC (Dx) 120.

Dy110 includes a sustain drive circuit unit for individually sustaining and driving each Y electrode, and a scan drive circuit unit for individually scanning and driving. The Dx 120 includes a sustain drive circuit unit for individually maintaining and driving each X electrode, and a scan drive circuit unit for individually scanning and driving. The Da 130 includes a circuit unit for individually address driving each address electrode.

The address drive is performed by applying the address pulse to the address electrode A by Da 130 and the scan pulse to the Y electrode by Dy 110 or applying the scan pulse to the X electrode by Dx 120 at the same timing. Realized. The sustain drive is realized by performing the application of the sustain pulse to the Y electrode by Dy 110 and the application of the sustain pulse to the X electrode by Dx 120 at alternate timings.

The electrodes of the PDP 10 (normal configuration) have n X electrodes (X1 to Xn), Y electrodes (Y1 to Yn), and m address electrodes (A1 to Am). A line (Li) is constituted by a pair of the X electrode (Xi) and the Y electrode (Yi). Between the lines is a non-display portion.

The Y electrode group and the Dy 110 are connected and connected between the terminals by the connecting portion 51. The X electrode group and the Dx 120 are connected and connected between the terminals by the connecting portion 52. The connection parts 51 and 52 are modules by a flexible substrate, for example.

In Dy110 and Dx120, drive voltage supply for supplying each voltage for scanning drive and sustain drive (scan voltage, sustain voltage) to the high-potential side and low-potential side power terminals (PH, PL). Circuits (Cyp141, Cxp142) are connected. The circuit (Cyp141, Cxp142) is connected to reset voltage waveform generation circuits (Cyr151, Cxr152) for applying a common reset driving voltage waveform to each line.

A Y electrode side drive voltage supply circuit (Cyp) 141 is connected to the outside of Dy110. A Y electrode side reset voltage waveform generation circuit (Cyr) 151 is connected to Cyp 141 (PL side). An X electrode side drive voltage supply circuit (Cxp) 142 is connected to the outside of Dx120. An X electrode side reset voltage waveform generation circuit (Cxr) 152 is connected to Cxp 142 (PL side).

The circuit units (110, 120, 130, 141, 142, etc.) are connected to the control circuit 101, etc. The control circuit 101 generates and outputs a drive control signal for controlling each of the circuit units based on an interface signal (data signal, clock signal, synchronization signal, etc.) input from the outside. This control is, for example, on / off switching control of the switch element. A scan voltage and a sustain voltage are supplied to each driver IC (Dy110, Dx120) by controlling the switch elements (SWX1 to SWX4, SWY1 to SWY4, etc.) built in each drive voltage supply circuit (Cyp141, Cxp142). Is done. Then, in conjunction with the output control of each driver IC, an operation of selectively applying a voltage waveform to each electrode of the PDP 10 is performed.

In Cyp 141, a circuit portion including SWY1 connected to the ground (GND) and SWY3 connected to the sustain voltage power supply (Vs) as a PH side circuit, and a scanning voltage power supply (−Vd) as a PL side circuit. And a circuit portion including SWY2 connected to GND and SWY4 connected to GND. In Cxp142, a circuit part including SWX1 connected to GND and SWX3 connected to the sustain voltage power supply (Vs) as a circuit on the PH side, and a scanning voltage power supply (−Vd) as a circuit on the PL side are connected. And a circuit portion including SWX4 connected to GND. Each switch element (such as SWX1) is configured by a MOS transistor or the like. At the time of drive control, the switch element is controlled to be on (conducting) / off (cut off) for a predetermined period, whereby a potential having a predetermined pulse width is supplied.

In the configuration example of FIG. 6, not only the switch elements (SWY1 and the like) but also the reset voltage waveform generation circuits (Cyr151 and Cxr152) are built in the X and Y drive voltage supply circuits (Cyp141 and Cxp142). However, the present invention is not limited to this, and it is possible to simplify the configuration by incorporating the reset circuit on only one side of X and Y by devising the waveform configuration.

<1-5: Driver IC>
FIG. 7 shows the configuration of each driver IC (Dy110, Dx120) for the Y electrode and the X electrode. Dy110 and Dx120 have the same configuration. For each output (OUT1 to OUThg) associated with the electrodes (X, Y) of the PDP 10, an output circuit (output stage buffer circuit (OB)) 202 is provided. For each output circuit 202, two types of switch elements, a high-side switch element (HSW) and a low-side switch element (LSW), are provided, and the power supply terminal sides of the plurality of HSWs are connected in common to provide a high-potential-side power supply terminal (PH ), And the power supply terminal sides of the plurality of LSWs are connected in common and are drawn out as low potential side power supply terminals (PL).

In front of each output circuit 202 (switch element), a shift register, a latch circuit, a gate circuit (G) 63, and the like are arranged as logic circuits for controlling them, and between the gate circuit (G) 63 and the HSW. Is provided with a level shift circuit (LS) 64.

As the shift register and latch circuit, there are provided shift register / latch circuits that are independent for scan drive control and sustain drive control. That is, a scan drive shift register / latch circuit (SCAN-SL) 61 and a sustain drive shift register / latch circuit (SUS-SL) 62 are provided, and are connected to the gate circuit (G) 63, respectively. As a result, the scanning drive and sustain drive operations can be performed independently for X and Y, respectively. Reference numeral 201 denotes a logic circuit (shift register / latch circuit) unit including SCAN-SL61 and SUS-SL62.

The SCAN-SL61 has C1: scan drive shift register / latch control signal as input, D1in: scan drive shift register data input, and scan drive shift register data output (D1out) as output. The SUS-SL 62 has C2: sustain drive shift register / latch control signal as input, D2in: sustain drive shift register data input, and sustain drive shift register data output (D2out) as output. Further, CG: a gate control signal is provided as a control input of the gate circuit (G) 63.

<1-6: Drive waveform (1)>
FIG. 8 shows an example of a basic drive waveform (first drive waveform) in the PDP device and the drive method of the first embodiment. From the top, the waveform applied to the address electrodes A (A1 to Am) and the waveform applied to each line L (X electrode-Y electrode) are shown. Note that a hatched rectangle in the waveform of the address electrode A represents an ON or OFF pulse for each address electrode. FIG. 8 shows an enlarged view of the vicinity of the first drive timing in the case of driving by skipping scanning sequentially from the upper line of the screen.

In the first reset driving period Tr (T0), first (first half), the Y electrode side reset voltage waveform generation circuit (Cyr) 151 is operated, and then rises in a ramp shape via the LSW of Dy110 and peaks. A positive reset voltage waveform reaching a voltage (Y lamp voltage) Vry is applied to all Y electrodes. Thereafter, at the next timing (second half), by operating the X electrode side reset voltage waveform generation circuit (Cxr) 152, the voltage rises in a ramp shape via the LSW of Dx120 and reaches the peak voltage (X lamp voltage) Vrx. The positive polarity reset voltage waveform leading to is applied to all X electrodes.

Next, the address / sustain drive period Tas starts, and address / sustain drive is sequentially performed on the electrodes of each line at each timing (T). The enclosure of A corresponds to the address drive A and S described above (FIGS. 3 and 5), and the enclosure of S corresponds to the sustain drive S described above.

First, address drive A is performed on line L1 at timing T1. Here, a scanning voltage (-Vd) is applied to the Y electrode of L1. For this reason, the LSW connected to the Y electrode Y1 of Dy110 is turned on, and at the same time, SWY2 of the drive voltage supply circuit (Cyp141) is turned on to supply the scanning voltage (−Vd) to the low potential side power supply terminal (PL). Further, SWY1 is turned on to connect the GND potential to the high potential side power supply terminal (PH). Thereby, a scanning voltage pulse (−Vd level) is applied to the selected Y electrode Y1. Simultaneously with the application of the scanning voltage pulse (−Vd), the address voltage pulse (Va level) is applied to the selected address electrode A by the Da 130. As a result, wall charges are formed for the selected cells on the line L1, and the address driving A of T1 is completed.

Next, a transition is made to the sustain light emission state by the sustain drive S in order to invert the wall charges formed by the address drive A one after another. Therefore, at timing T2, a sustain voltage pulse (Vs level) is applied to the Y electrode Y1 by Dy110. In this operation, HSW connected to the Y electrode Y1 of Dy110 is turned on, and at the same time, SWY3 of the drive voltage supply circuit (Cyp141) is turned on to supply the sustain voltage (Vs) to the high potential side power supply terminal (PH). Further, the SWY4 is turned on to connect the GND potential to the low potential side power supply terminal (PL). Thus, a sustain voltage pulse (Vs level) is applied to the Y electrode Y1.

Thereafter, at the next timing T3, as the subsequent sustain drive S, a sustain voltage pulse (Vs level) is applied to the X electrode X1 inverted from the Y electrode Y1 of T2 by Dx120. In the operation of Dx120, similarly to the operation on the Dy110 side, it is possible by controlling the switch element in the output stage in Dx120 connected to the X electrode X1 and the switch element in the drive voltage supply circuit (Cxp142). . The operation (sustain drive S) with respect to L1 (Y1, X1) is similarly performed for the number of sustain drives (SN) at each subsequent timing T. As a result, the sustain voltage pulse (Vs level) is alternately applied to the line (X, Y), and the wall charges are successively inverted, so that the sustain light emission state is continued. For example, in the selected cell in L1, an address discharge occurs between the address electrode and the Y electrode Y1 at T1, a first sustain discharge occurs between Y1 and X1 at T2, and at T3, between the same electrodes. A second sustain discharge occurs. In the line L1, since SN = 16, eight sustain voltage pulses (Vs level) are applied to the Y electrode and the X electrode respectively using 16 timings (T), and luminance for 16 units is obtained.

Hereinafter, the address voltage and pulse are represented by Va, the scanning voltage and pulse are represented by −Vd, and the sustain voltage and pulse are represented by Vs.

After address drive A is performed on Y1 at timing T1, as described above (FIGS. 2 and 4), at the next timing T2, interlaced scanning, which is this feature, is performed. Therefore, the next address drive A is performed on the line (L1 + g) jumped by the predetermined jump unit number (g) from the line (L1) driven at the previous T1. For example, g is 5 in the case of FIG. 2, L1 + g is L6, L1 + 2g is L11, and L1 + 3g is L16.

At this time (T2), the sustain voltage pulse (Vs) is applied to, for example, the Y electrode Y1 of the line L1 on which the address drive A (scanning drive) is performed at the previous timing T1. Therefore, the driver IC Dy110 that performs this operation and the drive voltage supply circuit (Cyp141) therefor are already used. Therefore, the operation on the Y electrode side cannot apply the scan voltage (−Vd) for the address drive A (scan drive) at T2 to the Y electrode.

Therefore, as a feature, at this timing T2, an operation of applying a scanning voltage (-Vd) from the circuit on the opposite X electrode side is performed. That is, in the first T1, one of the Y electrode sides in the display electrode (X, Y) pair, for example, is address driven A (scanning drive), but in the next T2, the other X electrode side in the display electrode (X, Y) pair Are driven by address driving A (scanning driving). Similarly, at the subsequent timings, the electrodes to be driven are alternated between X and Y.

At T2, the LSW connected to the X electrode X1 + g of Dx120 is turned on, and at the same time, SWX2 of Cxp142 is turned on to supply the voltage -Vd to the terminal PL, and SWX1 is turned on to connect the GND potential to PH. . As a result, the voltage −Vd is applied to the selected X1 + g electrode. At this time, by applying the voltage Va to the selected address electrode A, wall charges are formed in the selected cells on the line L1 + g, and the address driving A is finished.

In the same manner, the line L1 + g is shifted to the sustain light emission state by the sustain drive S. At T3, Vs is applied also to X1 + g in parallel with the application of Vs to X1 of the line L1 that has undergone address driving A. Therefore, each HSW connected to X1 and X1 + g of Dx120 is turned on, at the same time, SWX3 of Cxp142 is turned on to supply voltage Vs to terminal PH, and SWX4 is turned on to connect GND potential to terminal PL. To do. Thereby, the pulse Vs is applied to X1 and X1 + g.

At this timing T3, address drive A is simultaneously performed for L1 + 2g, which is the third line of interlaced scanning. Therefore, the pulse −Vd is applied to the Y electrode Y1 + 2g opposite to the X electrode. This operation is the same as the driving of L1 described above.

At the next timing T4, address drive A is performed for the L1 + 3g line, which is the fourth line of interlaced scanning. Therefore, the pulse −Vd is applied to the X electrode X1 + 3g opposite to the Y electrode. At the same time, since the sustain drive S is performed on the scanned L1, L1 + g, L1 + 2g, the pulse Vs is similarly applied to Y1, Y1 + g, Y1 + 2g.

As described above, the address / sustain drive operation to the lines (L1 to L1 + 3g) of the predetermined group (G1) can be performed simultaneously and in parallel. Such driving is the same for other groups of lines thereafter. As a result, a normal display operation is performed for all lines on the screen of the PDP 10.

The push-pull output type simple used for the main drive circuit on the display electrode (Y, X) side by the circuit configuration of the PDP device and the address / sustain drive control system as described above. The driver circuit (Dy110, Dx120) can be configured by a driver IC of various types. At the same time, the withstand voltage of the output circuit (202) of the drive circuit can be realized if there is a withstand voltage that guarantees the higher voltage level of the scan voltage | Vd | or the sustain voltage | Vs |. As a result, a small and low-cost driver IC can be used, and the entire drive circuit can be reduced in size and cost.

<1-7: Drive waveform (2)>
FIG. 9 shows a second example (second drive waveform) of basic drive waveforms in the first embodiment. In the second drive waveform, as in the first drive waveform described above (FIG. 8), address drive A is performed by interlaced scanning of group lines every time the timing T is switched. The difference is that the drive width (pulse width) of one voltage waveform (sustain voltage pulse Vs) of sustain drive S is expanded to 2 timings (2T), which is twice that of the first drive waveform. It is assumed that switching control is performed every 2T. In the first drive waveform, the alternate application of the scanning voltage −Vd and the sustain voltage Vs to the display electrode pair (Y electrode and X electrode) is switched every 1T, but in the second drive waveform, 2T It will be switched every time.

Also, an electrode to be scanned is selected in accordance with the sustain drive S method. That is, in the address drive A at timings T1 and T2, the pulse -Vd is applied to Y1 and Y1 + g on the Y electrode side with respect to L1 and L1 + g which are the first and second lines of scanning, and timings T3 and T4 In the address drive A, a pulse −Vd is applied to X1 + 2g and X1 + 3g on the X electrode side with respect to L1 + 2g and L1 + 3g which are the third and fourth lines of scanning.

At timings T3 and T4, in parallel with the operation of the address drive A, the sustain voltage pulse Vs is continuously applied to Y1 and Y1 + g that have been address driven A on the Y electrode side. In other words, one sustain voltage pulse Vs having a pulse width of 2T is applied at a timing of 2T including T3 and T4. Similarly, at subsequent timings T5 and T6, the pulse Vs is similarly applied continuously to X1, X1 + g, X1 + 2g, and X1 + 3g on the X electrode side.

This example is an example in which the sustain voltage pulse Vs is switched every 2T. However, the present invention is not limited to this, and it is of course possible to further increase the pulse width by further increasing the number of timings as a continuous application unit of the pulse Vs.

By extending the width of the sustain voltage pulse as described above, even if there is an unstable factor such as variation in the wall charge formed by the address drive A, the inversion drive operation is ensured and the stabilization is achieved. Therefore, the operation margin can be improved, erroneous display due to a discharge error or the like can be prevented, and the display quality can be improved.

In the first embodiment, the first driving waveform and the second driving waveform described above may be configured to operate using only one or both may be selectively used.

(Embodiment 2)
Next, the PDP apparatus according to Embodiment 2 (Configuration A) of the present invention, its drive circuit, drive system, and the like will be described with reference to FIGS. The second embodiment shows a more specific embodiment based on the configuration of the first embodiment. In the second embodiment, 11 divisional drive groups G (G1 to G11) with respect to 1080 lines constituting the screen of the PDP 10, 11 types of sustain drive numbers SN corresponding to 11 groups, and 1 field of 11SF (SF1 To SF11) is applied. Thereby, 2048 gradation display (including black display) is realized.

<2-1: Drive system>
FIG. 10 is a list showing an example of field SF, configuration of drive group G, and allocation of sustain drive number SN to each drive group G for each SF in the second embodiment. A shaded portion (SN = 1024) indicates a drive group at a position where address drive is first started in each SF. The head scanning line number (L #) indicates the head scanning line in each SF. For example, in SF1, L1 of G1 is the first scanning line, and SN = 1024 in G1.

The number of drive groups (G) related to sustain drive is 11 (G1 to G11), and 11 types of sustain drive numbers (SN: 1, 2, 4, 8,..., 1024) are assigned to these. The gradation expression is based on a power of 2. By driving eleven SFs: SF1 to SF11 in one field, these 11 types of sustain drive numbers SN are equally allocated to each group G to realize 2047 gradation display (excluding black display).

In the comparison with the maximum number of gradations (K) described above, the number of groups 11 selected here is set so that the sustain drive number SN of each group is set to only a power of 2 by zero and a natural number. The natural number N is equal to the minimum N (2047 <2 to the eleventh power) when the Nth power of 2 is larger, and is the minimum necessary number of groups.

In this case, when all 1080 lines are divided into 11 groups, 98 areas (B1 to B98) each consisting of 11 adjacent lines and a 99th one area (B99) consisting only of two lines (L1079, L1080). And divided. Therefore, the driving method of the second basic configuration (FIGS. 4 and 5) is applied.

11A to 11D schematically show the application timings of reset driving, address driving, and sustain driving for each SF in the field (the expression is the same as in FIG. 2). (A) shows SF1, (b) shows SF2, (c) shows SF6, and (d) shows a configuration example of SF11. Each SF is, for example, 1.515 ms. The numbers enclosed in the frames indicate the number of sustain drives SN set for the group.

First, in FIG. 11A, in the first SF1, after common reset driving (vertical line, R1), address / sustain driving (circle and horizontal line) is started, and G1, G2,. ..., address driving (marked with a circle) is performed in the order of G11. R1 is the reset drive timing of SF1. Address driving of each group is performed by interlaced scanning in units of 11 lines, and immediately after each address driving, sustain driving (horizontal line) with the sustain driving number SN set for each group is performed. The SN for each group is set so that more SNs are applied from the group in which address driving is started earlier. That is, the values of SN = 1024, 512,..., 1 are applied to the order of G1, G2,. R2 is the reset driving timing of the next SF2.

In FIG. 11B, in the next SF2, the common reset driving (R2) is similarly performed, and then the address / sustain driving is similarly started. However, the order of groups different from SF1, that is, G2, Address driving is performed in the order of G3,..., G11, G1, and sustain driving for which SN = 1024, 512,..., 1 is set is performed similarly to the arrangement in SF1. .

The same applies to the subsequent SF3,..., SF6 (FIG. 11 (c)),..., SF11 (FIG. 11 (d)). As a result, at the end of one field, SN: 1024, 512,..., 1 are evenly assigned to all 11 groups. Therefore, by maintaining (adding) those SNs, a maximum of 2047 can be maintained and driven for all lines.

<2-2: PDP device>
FIG. 12 shows a configuration example of a PDP apparatus that implements the second embodiment. In the present PDP apparatus, as a part different from the configuration of FIG. 6 described above, the arrangement of the display electrode pairs on the screen is an inverted repetition of (X, Y) as the structure of the PDP 10. That is, in order from the top, L1 (X1, Y1), L2 (Y2, X2), L3 (X3, Y3), L4 (Y4, X4),... The number of display lines is 1080 as described above (L1080 (Xn = X1080, Yn = Y1080)). Dy110 and Dx120 are circuit configurations corresponding to the PDP10 structure. With this configuration, as will be described later, useless capacity charging / discharging power between display lines is reduced.

<2-3: Driver IC>
FIG. 13 shows an arrangement connection configuration of Y and X electrode driver ICs (Dy110, Dx120) with respect to the PDP 10. FIG. 14 shows a circuit configuration of one driver IC 301 (Dy110, Dx120). FIG. 15 shows a connection circuit configuration between the driver IC 301 and an external control logic circuit.

13, the present configuration shows a case where a plurality of driver ICs 301 having 72-bit outputs are used and 15 each of the driver ICs 301 are used for the Y and X electrodes (72 × 15 = 1080). For example, in the lines L1 to L72 of the PDP 10, the output of the first driver IC (# 1) 301 on the Dy110 side is connected to the Y electrodes (Y1 to Y72) in a straight line at the connection portion 51, and the X electrodes (X1 to X72) are connected. ), The output of the first driver IC (# 1) 301 on the Dx120 side is straight-wired at the connection portion 52.

14 shows a circuit configuration of one driver IC 301 based on FIG. The driver IC 301 has a 72-bit output (OUT1 to OUT72), and in a portion corresponding to the 201 (61, 62), a scan drive shift register (SCAN-SR) 71 corresponding to the SCAN-SL61 and a scan drive A latch (SCAN-LAT) 72 and a sustain drive shift register (SUS-SR) 81 and a sustain drive latch (SUS-LAT) 82 corresponding to the SUS-SL62 are provided.

SCAN-SR71 has scan-CLK (clock) and scan-Din (data) as input, and scan-Dout (data) as output. A scan-LAT (latch) is provided as an input to the SCAN-LAT72. SUS-SR81 has sus-CLK (clock) and sus-Din (data) as inputs, and sus-Dout (data) as outputs. It has sus-LAT (latch) as an input of SUS-LAT82. Further, the control input of the gate circuit (G) 63 includes scan-STB (scan drive strobe) and sus-STB (sustain drive strobe).

FIG. 15 shows a connection circuit configuration of 15 driver ICs 301 (IC # 1 to # 15) and a control logic circuit (included in the control circuit 101). As signals from the control logic circuit, clock signals CLK (scan-CLK, sus-CLK) and data signals Din (scan-Din) to the shift registers (71, 81) for scan driving and sustain driving of the driver IC 301 are used. , Sus-Din), the latch signal LAT (scan-LAT, sus-LAT) to the respective latch circuits (72, 82) is inputted, and the gate is built in the output stage buffer circuit (output circuit 202) Strobe signals STB (scan-STB, sus-STB) are input to the circuit unit (63), respectively.

These signals are used in a potential floating state when a high voltage is applied to the driver IC 301 itself. Therefore, it is input to the photocoupler 501 for potential level conversion, and the output is connected to each driver IC 301 (IC # 1 to # 15).

The clock signal CLK, latch signal LAT, and strobe signal STB output from the photocoupler 501 are connected in parallel to all 15 driver ICs 301, respectively.

The data signal Din is connected only to the first driver IC # 1 as serial transfer data to the scan drive and sustain drive shift registers (71, 81). The second and subsequent driver ICs are sequentially connected so that Dout from IC # 1 is input as Din to IC # 2. As a result, the data is continuously transferred to the shift registers (71, 81) in all the driver ICs.

For the data signal Din, the method of selecting the line to be applied, the application timing, and the application for all the scanning voltages −Vd and the sustain voltage Vs depending on how to supply the data H (high) and L (low). The number and the like are controlled (details will be described later).

<2-4: Drive waveform>
Next, in FIG. 16 and FIG. 17, the details of the drive waveform for each line for the two SF examples of SF1 and SF2 are shown (expression is the same as in FIG. 8). The circled numbers indicate the scanning order in the group, and the numbers surrounded by a frame indicate the SN in the line. Va, -Vd, Vs, etc. are the same as described above.

Since one field (16.667 ms) is composed of 11 SF, the driving time of each SF is 1.515 ms. This SF is further divided into a reset driving period Tr of about 0.1 ms and an address / sustain driving period Tas of about 1.415 ms. Each timing T (T1 to T1123) of Tas is about 1.26 μs.

In FIG. 16, SF1, first, driving is started from the reset driving period Tr, and reset voltage waveforms (Vwy, Vwx) that rise alternately in a rising ramp shape are applied to all Y electrodes and X electrodes in common. The As a result, the wall charges accumulated in all the cells are reset to the initial state.

Next, an address / sustain drive period Tas is started, and in SF1, which is the first SF, address drive is started from the group G1 as described above. Therefore, at the first timing T1, Y of the line L1 to be scanned is A scanning voltage −Vd is applied to the electrode Y1.

At the next timing T2, the scan moves to the line L12 that has been skipped in units of 11 lines, but the scan voltage is applied to the X electrode (X12) different from the Y electrode (Y1) to which the scan voltage −Vd was applied immediately before (T1). -Vd is applied. At the same time, the sustain voltage Vs is applied to the Y electrode (Y1) corresponding to the line (L1) to which the scanning voltage −Vd has been previously applied and the address drive has been completed.

At the next timing T3, similarly, the scanning shifts to the line L23 which is skipped in units of 11 lines, and the scanning voltage is applied to the Y electrode (Y23) different from the X electrode (X12) to which the scanning voltage −Vd is applied immediately before (T2). -Vd is applied. At the same time, the sustain voltage Vs is applied to the X electrodes (X1, X12) corresponding to the lines (L1, L12) that have been previously applied with the scanning voltage -Vd and address driven.

Thereafter, the interlace scanning is similarly performed at each subsequent timing T, and one display electrode to which the scan voltage −Vd is applied and a plurality of display electrodes to which the sustain voltage Vs is applied are the Y electrode and the X electrode. The drive proceeds while maintaining the relationship of being alternately reversed. Then, at timing T99, the scan voltage −Vd is applied to the Y electrode Y1079 of the last line L1079 of the drive group G1, and the address drive of G1 is completed.

In summary, the scanning order (circled numbers) is as follows: first scanning (T1): L1 (Y1), second scanning (T2): L12 (X12), third scanning (T3): L23 (Y23),. ..., 98th scan (T98): L1068 (X1068), 99th scan (T99): L1079 (Y1079).

At the next timing T100, address drive for the next drive group G2 is started, and the first scan line becomes L2. Even when the drive groups are switched in this way, the relationship between the type of voltage application at the previous timing and the electrodes is reversed as described above. That is, the scanning voltage −Vd is applied to the X electrode side (X2) different from the Y electrode side (Y1079) immediately before (T99), and at the same time, the Y electrode side (Y1, Y12, Y23,. ..., Y1079) is applied with the sustain voltage Vs. Thereafter, this relationship is followed and the driving proceeds.

Here, as described above, the sustain drive number SN applied to each group is 1024, which is the largest in the group G1 where address drive is first started. In order to apply this, it is necessary to secure time (timing T) until the sustain drive of 1024 units is completed for the line L1079 where address drive (scan) is performed last in the group G1. . The scanning timing to the line L1079 is T99, and the application timing of the first sustain voltage pulse Vs is T100. Thereby, the number of timings (1024) for applying the sustain voltage pulse Vs of SN = 1024 thereafter is simply added. Therefore, 1123T from T1 to T1123 is required as the timing (time) required for completing all Tas address and sustain driving for G1 (99 + 1024 = 1123).

Therefore, in this example, T1 to T1123 are provided as the number of timings required for Tas of all SFs in the field including this SF1. However, it is not limited to the number of timings described here, and it is needless to say that the number of timings can be appropriately increased according to other driving needs.

The sustain drive number SN for the group G2 after T100 is 512 as described above. When the maximum sustain drive number SN that can be taken by the group G2 is calculated in the same manner, it becomes 925 (= 1123−99 × 2), which is smaller than 925. Therefore, the sustain drive can be completed within the timing T1123.

The driving is performed in the same manner from the group G3 onward, and the sustain drive number SN is selected to be 256, 128,.

The line on which address driving is performed at the end of SF1 is for L1078 of group G11, and the timing of address driving at this time is T1080 which is a value equal to 1080 which is the total number of lines.

For the lines (L1079 and L1080) belonging to the 99th area (B99), L1079 is treated as belonging to group G1, and L1080 is regarded as belonging to group G2. As a result, normal driving can be performed as well as the lines in the other regions B without missing.

Looking at the phase of the sustain voltage pulse Vs applied between the electrodes of two adjacent lines in the drive waveform described above, the same type of electrodes in Y and X (for example, T101, X1, X2) It can be seen that the phase is the same, but different types of electrodes have different phases. Since the display is not performed between the electrodes (non-display portion) between the adjacent lines (for example, between X1 and X2 in FIG. 12), it is not necessary to reverse the phase of the sustain voltage pulse Vs. The charge / discharge power to the capacity component is wasted. Therefore, in this configuration, in order to avoid this, the above-described PDP device configuration in FIG. 12 is applied, and the electrodes adjacent to each other as the electrode arrangement configuration in the PDP 10 are the same type of electrodes.

In FIG. 17, the driving waveform of SF2 is composed of Tr and Tas as in the previous SF1 (FIG. 16), and their time relationships are set similarly. As described above, SF2 is different from SF1 in that the order of the group G from which address driving is started is changed. First, address driving is started from a group G2 different from the group G1. Therefore, the scanning voltage −Vd is applied from the Y electrode Y2 of the line L2 at the timing T1. Others are the same as SF1.

<2-5: Control timing>
Next, in FIG. 18 to FIG. 20, the control timing related to the drive waveform described above is shown, and details of signals for controlling the Y and X electrode driver ICs (Dy110, Dx120) will be described. FIG. 18 shows the control timing of 1SUS (SN = 1, SF1, G11) when the sustain voltage pulse Vs is applied once at G11 of SF1, and similarly, 2SUS (SN = 2, SF1) is shown in FIG. , G10) and FIG. 20 show the control timing of 1024SUS (SN = 1024, SF1, G1). SUS indicates the sustain voltage pulse Vs in the sustain drive of the display line by the sustain drive number SN, for example, SUS1 indicates the first pulse immediately after the address drive (application of the scan voltage pulse −Vd), and SUS2 indicates the second pulse. .

As described above (FIG. 14), in the circuit configuration of the driver IC 301, the shift register / latch circuit (61, 62) for scan driving and sustain driving and the control circuit incorporated in the output stage buffer circuit 202 are used. A gate circuit 63 is provided, and as described above (FIG. 15), such a driver IC 301 is used and connected. As these control signals, a clock signal CLK, a data signal Din, a latch signal LAT, a strobe signal STB, and the like are input, respectively. In the lower part of FIG. 18, examples of these control signals are shown. For example, Yscan-CLK is a clock signal (scan-CLK) for scanning driving on the Dy110 side.

In FIG. 18, the clock signals CLK (Yscan-CLK, Ysus-CLK, Xscan-CLK, Xsus-CLK) for each of the scan drive and sustain drive shift register / latch circuits (61, 62) 11 clocks (clk) are input. This is because the number of the clocks (clk) is selected to be equal to 11 which is the number of sustain drive groups.

The latch signal LAT (Yscan-LAT, Ysus-LAT, Xscan-LAT, Xsus-LAT) is input during the timing T, and the data transferred at 11 clk is sent to the latch circuit (72, 82) every time the timing T is switched. It is captured.

First, for the shift register / latch circuit (61 (71, 72) for scanning drive), as the data signal Din (Yscan-Din), one data (Din (H)) synchronized with the first clk at the timing T0. ) Only, and transfer the 1 data for 11 clk. As a result, it is possible to apply the scanning voltage −Vd by interlaced scanning corresponding to the group G11 as described above, such as the lines L11 → L22 → L33 →.

Here, the strobe signal STB is input to the Y electrode side (Yscan-STB) so as to become active at odd-numbered timings T1, T3,..., And the even-numbered signal is supplied to the X electrode side (Xscan-STB). It is input so as to become active at timings T2, T4,. Thereby, the scanning voltage pulse −Vd can be alternately applied to the Y electrode and the X electrode corresponding to the group G11 in accordance with the respective timings.

Next, the sustain drive shift register / latch circuit (62 (81, 82)) is substantially the same as that for the scan drive, but the data signal Din is at the first clk at the timing T1. By inputting only one synchronized data (Din (H)), the strobe signal STB is alternately input to the Y electrode and the X electrode after the timing T2. Thereby, one sustain voltage Vs can be alternately applied to the Y electrode or the X electrode corresponding to the group G11.

Next, in FIG. 19, the control timing of 2SUS (SUS1, SUS2) is as follows. In this case, since control is performed for the group G10, the data signal Din is input to both the shift registers (71, 81) in synchronization with the second clk among 11 clks at each timing T.

On the scanning drive side, by inputting only one data (Din (H)) at T0, the scanning voltage pulse -Vd can be alternately applied to the Y and X electrodes corresponding to the group G10.

On the sustain drive side, by inputting two data (Din (H)) at T1 and T2, one sustain voltage pulse Vs is applied to the Y and X electrodes corresponding to the group G10, for a total of 2SUS ( SUS1, SUS2) can be applied.

Finally, in FIG. 20, the control timing of 1024SUS (SUS1 to SUS1024) is as follows. In this case, since control is performed for the group G1, the data signal Din is input to both the shift registers (71, 81) in synchronization with the last eleventh clk of 11clk at each timing T.

Similarly, on the scanning drive side, by inputting only one data (Din (H)) at T0, it is possible to alternately apply the scanning voltage pulse -Vd to the Y and X electrodes corresponding to G1.

On the sustain drive side, by inputting 1024 data (number of Din (H) is 1024) from T1 to T1024, 512 sustain voltage pulses Vs are alternately applied to the Y and X electrodes corresponding to G1, respectively. A total of 1024 SUS (SUS1 to SUS1024) can be applied.

The control method in the three examples regarding the SUS number (SN) to be applied has been described above, but the same applies to the control of other SUS numbers.

(Embodiment 3)
Next, the PDP device according to Embodiment 3 (Configuration B) of the present invention, its drive circuit, drive system, and the like will be described with reference to FIGS. In the third embodiment, as shown in FIG. 21, the number of lines on the screen is 1080, which is the same as in the first embodiment. However, the number of divided groups G is set to 12, which is one more, and correspondingly, 1F includes 12 SFs. The configuration consisting of (SF1 to SF12) is applied. This is an example in which 1865 gradation display (including black display) is realized in consideration of stabilization of operation. In the third embodiment, 12 types of sustain drive numbers (SN: 1, 2, 4,..., 256, 406, 451, 496) are assigned to 12 of the group G number. These 12 types of sustain drive numbers SN are equally allocated to each group G by driving the 12 SF1 to SF12. This realizes 1864 gradation display (excluding black display). In this case, if the 1080 lines are divided into 12 groups, unlike the second embodiment, the lines are divided into 90 regions B (B1 to B90) without excess or deficiency. Therefore, the driving method of the first basic configuration (FIGS. 2 and 3) is applied. Also, unlike Embodiments 1 and 2, a value (406, 451, 496) other than the power of a natural number for 2 is used as part of SN (the reason will be described later).

Therefore, the group number 12 in this case is the minimum N (1086 <2 to the 11th power) when the natural power N is larger than the Nth power of 2 in comparison with the above-mentioned maximum number of gradations (K). Does not match and is a value larger by one.

<3-1: Drive system>
22A to 22D show application timings of reset drive (R), address drive (A), and sustain drive (S) for each SF (the expression is the same as described above). In FIG. 22A, in the first SF1 (1.389 ms), after the common reset driving (R1), address / sustain driving is started, and address driving is performed in the order of groups G1, G2,..., G11, G12. Is done. Each address drive is performed by interlaced scanning in units of 12 lines. Immediately after the address drive, the sustain drive by the SN set for each group G is performed. The sustain drive number SN (SUS number) for each group G is set so that more SNs are applied from the group G where address drive starts earlier. For the order of G1, G2,..., G6,..., G10, G11, G12 in the case of SF1, SN: 496, 451, 406,. Each value is applied. The details after the next SF2 are as shown in the figure, and the basic contents are the same as those in the first embodiment.

<3-2: PDP device>
As a PDP device realizing the third embodiment, the configuration of the second embodiment (FIG. 12) can be similarly applied.

<3-3: Driver IC>
FIG. 23 shows the arrangement and connection configuration of the Y and X electrode driver ICs (Dy110, Dx120). Here, a case is shown in which a driver IC 302 having a 90-bit output is used and 12 of the driver ICs 302 (# 1 to # 12) are used for the Y and X electrodes (90 × 12 = 1080). As the circuit configuration of the driver IC 302, the configuration shown in FIG. 14 and the like can be similarly applied (the number of outputs is different). Further, as the connection circuit configuration between the twelve driver ICs 302 and the control logic circuit, the configuration shown in FIG. 15 can be similarly applied (the number of ICs is different).

<3-4: Drive waveform>
FIG. 24 shows details of the drive waveform for each line for the example of SF1. In SF1, the scanning order is G1 (L1, L13, ..., L1069), G2 (L2, L14, ..., L1070), ..., G12 (L12, L24, ..., L1080). For example, in SF2, G2 (L2, L14,..., L1070),..., G1 (L1, L13,..., L1069).

Since one field (16.667 ms) is composed of 12 SFs, the driving time of each SF is 1.389 ms, which further includes a reset driving period (Tr) of about 0.1 ms and an address / maintenance of about 1.289 ms. It is divided into a driving period (Tas). Tas has T1 to T1082. T is about 1.19 μs.

At SF1, driving is first started from Tr having the same contents as described above. Next, Tas is started. In the second embodiment, the above-described second driving waveform of FIG. 9 (one sustain voltage pulse Vs at 2T) is applied in order to give more importance to driving stability. .

Furthermore, from the viewpoint of emphasizing driving stability, the number of timings T in one address / sustain driving period Tas is limited to the minimum necessary so that the time width of one timing T can be secured as much as possible. For this reason, 1082 timings (T1 to T1082) obtained by adding only the driving time (2T) for one SUS to all scanning times (1080T) for the number of display lines (1080) are set as the basic timing numbers. Yes.

In SF1 Tas, at the first T1, the scanning voltage −Vd is applied to the Y electrode Y1 of the L1 of G1. In the next T2, the scanning shifts to the line L13 that is skipped in units of 12 lines. In the third embodiment, the scanning voltage − is applied to the Y electrode Y13 that is the same as the Y electrode (Y1) side to which the scanning voltage −Vd is applied immediately before. Vd is applied.

Then, at the next T3, similarly, the scanning shifts to the line L25 which is skipped in units of 12 lines, but this time, the scanning is performed to the X electrode X25 which is different from the Y electrode (Y13) side to which the scanning voltage −Vd was applied immediately before. A voltage −Vd is applied. At the same time, the sustain voltage Vs is applied to the Y electrodes (Y1, Y13) corresponding to the address-driven lines previously applied with the scan voltage -Vd.

Further, at the next T4, similarly, the scanning shifts to the line L37 jumped by the unit of 12 lines, but this time, the scanning voltage is applied to the same X electrode X37 as the X electrode (X25) side to which the scanning voltage −Vd was applied immediately before. -Vd is applied. As for the application of the sustain voltage Vs at T4, since the sustain voltage is not applied to the Y electrode Y25 in the immediately preceding T3, although the address drive is completed, the sustain voltage is not applied to Y25, and similarly to T3, The sustain voltage Vs is applied to the Y electrodes (Y1, Y13).

Thereafter, interlaced scanning is similarly performed at each subsequent timing, and one electrode (Y or X) to which the scanning voltage −Vd is applied and a plurality of electrodes (Y or X) to which the sustain voltage Vs is applied. The Y and X electrodes are controlled so that the drive proceeds while maintaining the relationship of being alternately reversed every two timings (2T).

By the above operation, as shown in the figure, the time width (pulse width) of the sustain voltage pulse Vs (SUS) applied to the Y and X electrodes is widened to 2T. This has the effect of stabilizing the drive.

Here, when the timing for completing the address drive in each group G is viewed, the number of lines in each group G is 90. Therefore, T1 in G1, T180 in G2, T270 in G3, T360 in G4, It becomes each timing. In addition to this, since the number of 1SF Tas timings described above is limited to a maximum of 1082, the sustain drive number SN that can be set for each group G is naturally determined, and the details are as follows.

The sustain drive number SN (maximum settable number) that can be set for each group G is 992T from the next timing T91 to the last timing T1082 at the end of address drive in G1. In the third embodiment, 2T corresponds to one unit of the sustain drive number SN (one sustain voltage pulse Vs (SUS) having a width of 2T), and in 992T, the sustain drive number SN is 496 (496SUS). Similar calculation shows that SN (SUS) (maximum settable number) can be set to 451 for G2, 406 for G3, and 361 for G4.

However, when setting the actual SN (SUS) of each group G, it is necessary to be able to perform continuous setting in units of 1 SUS from the minimum 1 SUS to the maximum SUS number. For this reason, it is necessary to comprehensively select the setting by taking in powers of zero and natural numbers to 2 that can be set continuously in units of 1 SUS.

Specifically, first, address driving is completed in the order from the slowest group, that is, G12, G11,..., G4, G3, G2, and G1. The values 1, 2,..., 256, 512, 1024, and 2048, which are power values, are associated with each other. As described above, when the value of 512 or more cannot be selected, the maximum number that can be set is selected for SN after G3, that is, 406 for G3, 451 for G2, and 496 for G1. It is. The sustain drive number SN for each group G of each SF finally determined as described above is as shown in FIG. As a result, a maximum of 1864 SUS gradation driving is possible. However, the above setting is a case where the number of timings of one Tas is 1082, which can of course be arbitrarily increased according to the necessity of the number of gradations.

Further, due to the necessity of different gradation control, etc., the sustain drive numbers SN of G3, G2, and G1 are not changed as described above, but for at least two groups or all three groups. It is also possible to select the same SN.

In the above, the phase of the sustain voltage pulse Vs applied between the electrodes of the adjacent lines is the same, which is the same as in the second embodiment.

Regarding the driving waveform of the next SF2, the difference from the SF1 is that the order of the group G in which the address driving is started is changed. First, the driving waveform starts from G2 different from G1. Therefore, the scanning voltage −Vd is applied from the Y electrode Y2 of L2 at T1. About others, it is the same as that of SF1. The same applies to the subsequent SFs.

<3-5: Control timing>
In FIG. 25, details of signals for controlling the Y and X electrode driver ICs (Dy110, Dx120) will be described. Basically, it is the same as that of the second embodiment, and only the differences will be described.

At the control timing of 1SUS (G12, SN = 1) in SF1, 12clk is input at every timing T as the clock signal CLK of all the shift registers (71, 81). 12clk is chosen to be equal to 12 in the group G number. The corresponding strobe signal STB is output continuously every two timings (2T) to the Y electrode side and the X electrode side in both scanning drive and sustain drive so that H and L are alternately repeated every 2T. Set to

Also, for the sustain drive data signal Din, two data (Din (H)) synchronized with the first clk of T1 and T2 (corresponding to G12) are input in order to continuously output over 2T.

With respect to the control timing of 2SUS in SF1, 4 data synchronized with the second clk of T1 to T4 (corresponding to G11) for the data signal Din for sustain driving on both the Y and X electrodes side for the control of 2SUS. input. Others are the same as described above.

Regarding the control timing of 496SUS in SF1, for the control of 496SUS, 992 data synchronized with the 12th clk of T1 to T992 (corresponding to G1) is used for the data signal Din for the sustain drive on both the Y and X electrodes. input. Others are the same as described above.

Although the method of controlling the three examples of the SUS number to be applied has been described above, the same applies to the control of the other SUS numbers.

(Embodiment 4)
Next, FIG. 26 to FIG. 30 and the like show a PDP device and the like according to Embodiment 4 (Configuration C) of the present invention. In the fourth embodiment, application specifications, group, SF, SN assignment, reset for each SF, address, sustain drive timing, and the like are the same as those in the third embodiment. In the fourth embodiment, the same configurations as those of the second embodiment can be applied to the configurations of the PDP device and the driver IC. In the fourth embodiment, the number of output bits of the driver IC is 72 bits (FIG. 14, driver IC 301), which is the same as in the second embodiment. As a result, the number of ICs required for each of the Y and X electrodes of the PDP 10 is 15 (similar to FIG. 13).

<4-1: Driver IC>
FIG. 26 shows a circuit configuration of the driver IC 303 (Dy110, Dx120) according to the fourth embodiment. FIG. 27 shows the connection between the driver IC 303 and the control logic circuit and the signal input configuration.

As a feature of the fourth embodiment, the difference from the first embodiment is that, as shown in FIG. 26, both the scan drive and sustain drive shift registers (71, 81) have different numbers of input / outputs of the data signal Din. It is set to 12 which is the same as the number G of sustain driving groups (scan-Din1 to Din12, etc.).

In the second and third embodiments, as described above (FIG. 14 and the like), the shift register (71, 81) is constituted by one serial transfer type, so that the number of input / output of the data signal Din is one. One. By controlling the number of clocks (clk) applied during one timing T and the position of the data signal Din inputted in synchronization with the number of clocks (clk) (FIG. 18 etc.), the number of groups G for sustain drive and various controls corresponding to this It is carried out.

On the other hand, in the fourth embodiment, the driver IC 303 is provided in advance with the same number of shift register / latch circuits (the plurality of circuits 63 of 61 and 62) as the number of sustain drive groups G (12). Keep it. Thus, the configuration is changed so that each of the circuits (63) can be controlled independently. The control data of each group G is stored in a dedicated shift register / latch circuit (63). The output of each latch circuit of the dedicated shift register / latch circuit (63) is connected to the Y or X electrode corresponding to each group G via the output stage buffer circuit 202. In the output circuit 202, OG1 to OG6 are output groups. For example, the first output group OG1 corresponds to OUT1 to OUT12.

By using the driver IC 303 as described above, as shown in FIG. 27, between the ICs (control logic circuit IC-driver IC 303), both the scan drive and sustain drive shift registers (71, 81) input 12-bit data. A signal Din (scan-Din1 to Din12 etc.) is sequentially connected between the input and output in parallel.

Here, for the input part from the external control logic circuit, the photocoupler 501 for potential level conversion for the signal Din is required for the number of parallel inputs. As a device for reducing this, FIG. The structure is as follows. That is, for both scanning drive and sustain drive, the signal Din is received serially (DATA-CLK, DATA-in, DATA-LAT), and a dedicated shift register / latch circuit (91 for converting this from serial to parallel) , 92). With this configuration, the number of photocouplers 501 related to the signal Din is reduced to three.

<4-2: Control timing>
The drive timing control timing of the fourth embodiment will be described with reference to FIGS. The drive waveform of the fourth embodiment is the same as that of the third embodiment. Since the control timing is basically the same as that of the third embodiment, only the differences will be described.

As described above (FIG. 26), the shift registers (71, 81) are divided into 12 groups G. Therefore, data Din1 to Din12 corresponding to each group G is input at each timing T as one clock (CLK) input per timing T. Other latch signals LAT, strobe signals STB, and the like are the same as in the third embodiment.

FIG. 28, the control timing of 1SUS in SF1 is the control of the waveform output of 1SUS to the group G12. Therefore, data is input only to Din12 of the shift register / latch circuit (61, 62) for the scan drive and sustain drive of the Y and X electrodes.

The control timing written in FIG. 28 is not the signal of the input part from the control logic part in FIG. 27 but the signal seen at the input terminal part of IC # 1.

For scan drive, 1 data (Din (H)) is input to T0, and for sustain drive, 2 data (Din (H)) of T1 and T2 are input. As a result, the scan drive and the sustain drive are interchanged between the Y and X electrodes every 2T as in the third embodiment, and only 1SUS is output.

Since the control timing of FIG. 29 and 2SUS is the control of the 2SUS waveform output to G11, it corresponds to Din11 of the shift register and latch circuit (61, 62) for the scan drive and sustain drive of the Y and X electrodes. Only data is input. For scan driving, 1 data (Din (H)) is input to T0, and for sustain driving, 4 data (Din (H)) T1 to T4 are input. The time of data H is 4CLK width (for 4T). As a result, the scanning drive and the sustain drive are interchanged between the Y and X electrodes every 2T as in the third embodiment, and the drive for outputting a total of 2SUS by 1SUS is performed.

Since the control timing of FIGS. 30 and 496 SUS is the control of the 496 SUS waveform output for G 1, it corresponds to Din 1 of the shift register and latch circuit (61, 62) for the scan drive and sustain drive of the Y and X electrodes. Only data is input. For scan driving, 1 data (Din (H)) is input to T0, and for sustain driving, 992 data (Din (H)) from T1 to T992 is input. As a result, the scan drive and the sustain drive are interchanged between the Y and X electrodes every 2T as in the third embodiment, and a drive for outputting a total of 496 SUS in units of 248 SUS is performed.

Although the method of controlling the three examples of the SUS number to be applied has been described above, the same applies to the control of the other SUS numbers.

According to the circuit configuration of the fourth embodiment described above, the number of clock signals input to each driver IC for each timing may be one, and the operation is performed at a low frequency. The frequency characteristics required for the logic circuit of each driver IC may be lower than that of the driver IC, so that the cost of the driver IC can be reduced, and the operation is less susceptible to adverse effects such as malfunction caused by high frequency noise. There are advantages that are possible.

As described above, according to each embodiment, improvement in gradation display performance and panel drive characteristics by a new drive method is realized.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

The present invention can be used for a PDP device or the like.

Claims (17)

1. A plurality of first electrodes and second electrodes extending in a first direction; and a plurality of third electrodes extending in a second direction intersecting the first direction, wherein the plurality of first electrodes and second electrodes are adjacent to each other. A display line is configured by a pair of the first electrode and the second electrode, respectively, and a plasma display panel in which a display cell is configured in each intersection region of the plurality of display lines and the plurality of third electrodes;
   A first drive circuit for driving the plurality of first electrodes;
   A second drive circuit for driving the plurality of second electrodes;
   A third drive circuit for driving the plurality of third electrodes;
   A control circuit for controlling the first, second and third drive circuits,
   The control circuit includes:
   In order to select the display cell and start discharging, the first electrode or the second electrode of the display line to be selected, together with the operation of applying a third voltage to the third electrode to be selected at every predetermined time unit While performing an address driving operation for performing a scanning operation of applying a first voltage to
   In order to maintain the discharge of the display cell, a pair of the first electrode and the second electrode adjacent to one or more display lines that have undergone the address driving operation among display lines that are not selected during the address driving operation. By executing the sustain driving operation of applying the second voltage to
   Controlling each of the driving circuits so as to execute the address driving operation and the sustain driving operation simultaneously in parallel;
   The scanning operation in the address driving operation is performed by interlaced scanning in units of a predetermined number of display lines with respect to an arrangement of a plurality of display lines on the screen of the panel.
   Controlling each of the drive circuits so that the number of times of applying the pulse of the second voltage in the sustain drive operation can be different between all adjacent display lines in the plurality of display lines. A characteristic plasma display device.
2. The plasma display device according to claim 1, wherein
   A plurality of groups of groups of distant display lines so that the plurality of display lines of the screen can vary the number of times of application of the second voltage pulse in the sustain driving operation to a plurality of types. Divided into
   The number of display lines in the interlaced scanning unit in the address driving operation is equal to the number of the plurality of groups.
3. The plasma display device according to claim 2, wherein
   The number of the plurality of groups is 2 N to the natural number N with respect to the maximum number of gradations in relation to the maximum number of gradations determined by adding the number of pulses of the sustain driving operation within a fixed drive period. A plasma display device characterized by being equal to N when the direction becomes larger.
4. The plasma display device according to claim 1, wherein
   Display lines that are sequentially selected for the address driving operation are switched by the interlaced scanning at each timing, and an electrode to which the first voltage is applied by the scanning operation at each switching is the first electrode. And alternately for the second electrode,
   An electrode to which the second voltage is applied in the sustain driving operation for each of the plurality of display lines that have undergone the address driving operation among the non-selected display lines during the address driving operation is switched at each timing switching. The plasma display device is controlled so as to be alternately switched with respect to the second electrode and the first electrode.
5. The plasma display device according to claim 1, wherein
   The display lines that are sequentially selected for the address driving operation are switched at each timing, and the scanning operation is performed at each timing for the continuous time, with a predetermined number of times of the predetermined time unit as a unit. The electrodes to which the first voltage is applied are alternately switched with respect to the first electrode and the second electrode,
   For the plurality of non-selected display lines during the address driving operation, an electrode to which the second voltage is applied in the sustain driving operation is applied to the second electrode and the first electrode at every successive timing. Can be switched alternately,
   The second voltage is controlled to be continuously applied to either the second electrode or the first electrode in the sustain driving operation during the continuous timing. Plasma display device.
6. The plasma display device according to claim 1, wherein
   The first driving circuit selectively applies a negative voltage (−Vd) as the first voltage to the plurality of first electrodes, and a positive voltage (Vs) as the second voltage. Selectively applied to one electrode,
   The second drive circuit selectively applies a negative voltage (−Vd) as the first voltage to the plurality of second electrodes, and a positive voltage (Vs) as the second voltage. Selectively applied to two electrodes,
   The plasma display apparatus, wherein the third driving circuit selectively applies a positive voltage (Va) as the third voltage to the plurality of third electrodes.
7. The plasma display device according to claim 1, wherein
   In each of the first and second drive circuits,
   A high-side switch element connected between a corresponding electrode of the first or second electrode and a high-potential side power supply terminal, and between a corresponding electrode of the first or second electrode and a low-potential side power supply terminal A plurality of circuits including a low-side switch element connected to
   A drive voltage supply circuit for supplying a predetermined drive voltage corresponding to the first and second voltages is connected to each of the high potential side power supply terminal and the low potential side power supply terminal. Plasma display device.
8. The plasma display device according to claim 7, wherein
   The plurality of circuits in the first and second drive circuits are composed of a plurality of ICs that are integrated into ICs for each predetermined number of outputs.
9. The plasma display device according to claim 8, wherein
   A first shift register for scanning drive control for applying the first voltage to a corresponding electrode of the first or second electrode in the plurality of ICs in the first and second drive circuits; And a second shift register for sustain drive control for applying the second voltage to the corresponding electrode of the first or second electrode.
10. The plasma display device according to claim 9, wherein
    In the plurality of ICs in the first and second drive circuits,
    The number of times the first voltage and the second voltage are applied to the corresponding electrode of the first or second electrode is controlled by the number of data input in synchronization with the clocks of the first and second shift registers. A plasma display device.
11. The plasma display device according to claim 10, wherein
    A circuit that serially inputs a data signal from the control circuit side and converts the data signal into parallel; a plurality of the data signals converted into parallel form the first and second shift registers of the plurality of ICs; A plasma display device, wherein the circuit unit inputs and processes in parallel.
12. A plurality of first electrodes and second electrodes extending in a first direction; and a plurality of third electrodes extending in a second direction intersecting the first direction, wherein the plurality of first electrodes and second electrodes are adjacent to each other. A display line is configured by the pair of the first electrode and the second electrode, respectively, and a plasma display panel in which a display cell is configured in each intersection region of the plurality of display lines and the plurality of third electrodes;
    A first drive circuit for driving the plurality of first electrodes;
    A second drive circuit for driving the plurality of second electrodes;
    A third drive circuit for driving the plurality of third electrodes;
    A control circuit for controlling the first, second and third driver circuits,
    The control circuit includes:
    In order to select the display cell and start discharging, the first electrode or the second electrode of the display line to be selected, together with the operation of applying a third voltage to the third electrode to be selected at every predetermined time unit While performing an address driving operation for performing a scanning operation of applying a first voltage to
    In order to maintain the discharge of the display cell, a pair of the first electrode and the second electrode adjacent to each other in the one or more display lines that have been address driven among the non-selected display lines during the address driving operation. By performing the sustain drive operation to apply the second voltage,
    Controlling each of the driving circuits so as to execute the address driving operation and the sustain driving operation simultaneously in parallel;
    The display lines that are sequentially selected for the address driving operation are switched at each timing, and the scanning operation is performed at each timing for the continuous time, with a predetermined number of times of the predetermined time unit as a unit. The electrodes to which the first voltage is applied are alternately switched with respect to the first electrode and the second electrode,
    For the plurality of non-selected display lines during the address driving operation, an electrode to which the second voltage is applied in the sustain driving operation is applied to the second electrode and the first electrode at every successive timing. Can be switched alternately,
    The second voltage is controlled to be continuously applied to either the second electrode or the first electrode in the sustain driving operation during the continuous timing. Plasma display device.
13. The plasma display device according to claim 12, wherein
    The first driving circuit selectively applies a negative voltage (−Vd) as the first voltage to the plurality of first electrodes, and a positive voltage (Vs) as the second voltage. Selectively applied to one electrode,
    The second drive circuit selectively applies a negative voltage (−Vd) as the first voltage to the plurality of second electrodes, and a positive voltage (Vs) as the second voltage. Selectively applied to two electrodes,
    The plasma display apparatus, wherein the third driving circuit selectively applies a positive voltage (Va) as the third voltage to the plurality of third electrodes.
14. The plasma display device according to claim 12, wherein
    In each of the first and second drive circuits,
    A high-side switch element connected between a corresponding electrode of the first or second electrode and a high-potential side power supply terminal, and between a corresponding electrode of the first or second electrode and a low-potential side power supply terminal A plurality of circuits including a low-side switch element connected to
    A drive voltage supply circuit for supplying a predetermined drive voltage corresponding to the first and second voltages is connected to each of the high potential side power supply terminal and the low potential side power supply terminal. Plasma display device.
15. The plasma display device according to claim 14, wherein
    The plurality of circuits in the first and second drive circuits are composed of a plurality of ICs that are integrated into ICs for each predetermined number of outputs.
16. The plasma display device according to claim 15, wherein
    A first shift register for scanning drive control for applying the first voltage to a corresponding electrode of the first or second electrode in the plurality of ICs in the first and second drive circuits; And a second shift register for sustain drive control for applying the second voltage to the corresponding electrode of the first or second electrode.
17. The plasma display device according to claim 16, wherein
    In the plurality of ICs in the first and second drive circuits,
    The number of times the first voltage and the second voltage are applied to the corresponding electrode of the first or second electrode is controlled by the number of data input in synchronization with the clocks of the first and second shift registers. A plasma display device.

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