WO2010016958A1 - Structure d'interconnexion avec chapeau métallique auto-alignée avec une surface d'un matériau conducteur incorporé - Google Patents

Structure d'interconnexion avec chapeau métallique auto-alignée avec une surface d'un matériau conducteur incorporé Download PDF

Info

Publication number
WO2010016958A1
WO2010016958A1 PCT/US2009/042065 US2009042065W WO2010016958A1 WO 2010016958 A1 WO2010016958 A1 WO 2010016958A1 US 2009042065 W US2009042065 W US 2009042065W WO 2010016958 A1 WO2010016958 A1 WO 2010016958A1
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric material
interconnect structure
dielectric
noble metal
conductive material
Prior art date
Application number
PCT/US2009/042065
Other languages
English (en)
Inventor
Conal E. Murray
Chih-Chao Yang
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Publication of WO2010016958A1 publication Critical patent/WO2010016958A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor interconnect structure and a method of fabricating the same. More particularly, the present invention relates to a semiconductor interconnect structure having enhanced electromigration (EM) reliability in which a noble metal cap is located directly on a surface of a conductive material that is embedded within an interconnect dielectric material. A method of forming such an interconnect structure is also provided.
  • EM electromigration
  • semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate.
  • IC integrated circuit
  • a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures.
  • the wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
  • metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as "crosstalk") are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
  • Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size decreases, the practical significance of EM increases.
  • EM is one of the worst reliability concerns for very large scale integrated (VLSI) circuits and manufacturing since the 1960's.
  • VLSI very large scale integrated
  • the problem not only needs to be overcome during the process development period in order to qualify the process, but it also persists through the lifetime of the chip.
  • Voids are created inside the metal conductors of an interconnect structure due to metal ion movement caused by the high density of current flow.
  • metal atoms such as Cu atoms
  • the EM initial voids first nucleate at the metal/dielectric cap interface and then grow in the direction to the bottom of the interconnect, which eventually results in a circuit dead opening.
  • FIGS. 1 A-ID are pictorial representations of a prior art interconnect structure at various stages of an EM failure.
  • reference numeral 12 denotes the dielectric cap
  • reference numeral 10 denotes the metal interconnect feature; all other components of the prior art interconnect structure are not labeled to avoid obscuring the EM problem.
  • FIG. IA is at an initial stress stage.
  • FIG. IB is at a time when void 14 nucleation initiates at the metal interconnect feature 10/dielectric cap 12 interface.
  • FIG. 1C is at a time when the void 14 grows towards the bottom of the conductive feature 10
  • FIG. ID is at a time in which the void 14 growth crosses the metal interconnect feature 10 causing a circuit dead opening.
  • Prior art metal caps are typically comprised of a Co-containing alloy such as, for example, CoWP, which is selectively deposited atop of the Cu conductor region of the interconnect structure.
  • CoWP Co-containing alloy
  • One problem with utilizing such selective deposited metal caps is that some of the metal cap extends onto the adjoining surface of the interconnect dielectric material and, as such, electrical shorts between adjacent interconnects may arise. This is seen, for example, in FIG.
  • reference numeral 20 denotes a dielectric material
  • reference numeral 22 denotes a conductive material embedded within the dielectric material
  • reference numeral 24 denotes a Co-containing alloy metal cap
  • reference numeral 25 denotes metal residues from the Co-containing alloy cap process.
  • the present invention provides a semiconductor interconnect structure that has improved EM reliability.
  • the present invention also provides a semiconductor interconnect structure in which electrical shorts between adjacent interconnect structures is avoided.
  • the present invention also provides an interconnect structure that has better reliability and technology extendibility for the semiconductor industry.
  • the present invention provides an interconnect structure in which a noble metal-containing cap layer is present only on an exposed upper surface of a non-recessed conductive material which is embedded within a low k dielectric material. That is, the noble metal-containing cap layer is self-aligned to the exposed upper surface of the non-recessed low k dielectric material. Moreover, in the inventive structure no metal-containing cap layer extends onto the diffusion barrier that separates the conductive material from the low k dielectric material
  • low k is used throughout this application to denote an interconnect dielectric material having a dielectric constant of about 3.0 or less.
  • non-recessed conductive material is used herein to denote a conductive material having an upper surface that is co-planar with an upper surface of the low k dielectric material. Applicants have determined that by providing a metal-containing cap layer that is self-aligned to the upper surface of the non- recessed conductive material, a structure having better leakage control compared with prior art structures such as those described in the co-pending applications mentioned in the Related Applications section of this application is provided.
  • the interconnect structure of the present invention includes:
  • dielectric material having a dielectric constant of about 3.0 or less, said dielectric material having at least one conductive material embedded within said dielectric material, said at least one conductive material having an upper surface that is co-planar with an upper surface of said dielectric material;
  • a noble metal cap located directly on said upper surface of said at least one conductive material, said noble metal cap does not extend onto an upper surface of a diffusion barrier that separates the at least one conductive material from said dielectric material.
  • the dielectric material which is present in the inventive interconnect structure may be any interconnect dielectric material having a dielectric constant of about 3.0 or less.
  • the dielectric material employed in the present invention comprises a silsesquioxane, a C doped oxide (i.e., an organosilicate) that includes at least atoms of Si, C, O and H, a thermo setting polyarylene ether, or multilayers thereof.
  • the dielectric material may be porous, non-porous or contain regions and/or surfaces that are porous and other regions and/or surfaces that are non-porous.
  • the conductive material which forms an embedded conductive region within the interconnect structure includes any material that has the ability to transfer electricity.
  • Examples of conductive material that can be present in the conductive region include, for example, polySi, a conductive metal, a conductive metal alloy, a conductive metal suicide or combinations and multilayers thereof.
  • the conductive material includes a conductive metal such as, for example, Cu, W, and/or Al.
  • the conductive material includes a Cu-containing conductive material such as, for example, Cu, or a Cu alloy (such as AlCu).
  • the conductive material is separated from the dielectric material by a diffusion barrier.
  • the diffusion barrier prevents diffusion of the conductive material into the dielectric material.
  • diffusion barriers that can be present within the conductive region include, for example, Ta, TaN, Ti, TiN, Ru 5 RuN, RuTa, RuTaN, IrTa, IrTaN, W, WN or combinations and multilayers thereof.
  • the conductive material may be present within a via opening, a line opening, a combined via and line opening or any combination thereof.
  • the term "noble metal" when referring to the cap located directly atop the at least one conductive material includes any metal that is resistant to corrosion or oxidation.
  • the preferred noble metals that can be used in the present invention are selected from the group consisting of Ru, Ir, Rh, Pt, Co and alloys thereof. More preferably, the noble metal employed as the noble metal cap comprises Ru or a Ru alloy.
  • the present invention also provides a method of fabricating the same.
  • the inventive method includes:
  • dielectric material having a dielectric constant of about 3.0 or less, said dielectric material having at least one conductive material embedded within said dielectric material, and said at least one conductive material has an upper surface that is co-planar with an upper surface of said dielectric material;
  • a noble metal cap directly on said upper surface of said at least one conductive material, said noble metal cap does not extend onto an upper surface of a diffusion barrier that separates the at least one conductive material from said dielectric material, said noble metal cap forming does not result in noble metal residues on the upper surface of said dielectric material, and said forming includes a chemical deposition process that is performed at a temperature of about 200 0 C or less.
  • FIGS. IA-I D are pictorial representations (through cross sectional views) illustrating the formation of a circuit dead opening in a prior art interconnect structure which is caused by EM failure.
  • FIG. 2 is a prior art interconnect structure (through a cross sectional view) including a Co-containing alloy metal cap located atop a conductive material that is embedded with a dielectric material, and metal residues from the Co-containing alloy cap process are present on the dielectric surface.
  • FIG. 3 is a prior interconnect structure (through a cross sectional view) including a recessed conductive material embedded within a dielectric material, said recessed conductive material having a metal capping layer located thereon.
  • FIGS. 4A-4E are pictorial representations (through cross sectional views) illustrating an interconnect structure through various processing steps of the present invention.
  • the present invention provides an interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less.
  • This low k dielectric material has at least one conductive material having an upper surface embedded therein.
  • a noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the low k dielectric material and the low temperature deposition employed in forming the noble metal cap, the noble metal cap does not substantially extend onto an upper surface of a diffusion barrier that separates the at least one conductive material from the dielectric and no metal residues from the noble metal cap deposition form on the dielectric material surface.
  • FIGS. 4A-4E are pictorial representations (through cross sectional views) illustrating an exemplary interconnect structure of the present invention through various processing steps.
  • FIG. 4A illustrates an initial structure 50 that can be employed in the present invention in fabricating the inventive interconnect structure.
  • the initial structure 50 includes a dielectric material 52 having a pad stack 54 located on an upper surface thereof.
  • the initial structure 50 is typically located upon a substrate (not shown in the drawings of the present application).
  • the substrate may comprise a semiconducting material, an insulating material, a conductive material or any combination including multilayers thereof.
  • any semiconductor such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs 5 InAs, InP and other III/V or II/VI compound semiconductors may be used.
  • the present invention also contemplates cases in which the semiconductor substrate is a layered semiconductor such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs).
  • the semiconductor substrate is a layered semiconductor such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs).
  • the insulating material can be an organic insulator, an inorganic insulator or a combination thereof including multilayers.
  • the substrate may include, for example, polySi, an elemental metal, alloys of elemental metals, a metal suicide, a metal nitride or combinations thereof including multilayers.
  • the substrate comprises a semiconducting material, one or more semiconductor devices such as, for example, complementary metal oxide semiconductor (CMOS) devices can be fabricated thereon.
  • CMOS complementary metal oxide semiconductor
  • the substrate may represent a first interconnect level of a multilayered interconnect structure.
  • the dielectric material 52 of the initial structure 50 comprises any interlevel or intralevel dielectric including inorganic dielectrics or organic dielectrics.
  • the dielectric material 52 may be porous, non-porous or contain regions and/or surfaces that are porous and other regions and/or surfaces that may be non-porous.
  • dielectric material 52 examples include, but are not limited to silsesquioxanes, C doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, thermosetting polyarylene ethers, or multilayers thereof.
  • polyarylene is used in this application to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like.
  • the dielectric material 52 typically has a dielectric constant that is about 3.0 or less, with a dielectric constant of about 2.8 or less being even more typical. All dielectric constants mentioned herein are relative to a vacuum, unless otherwise noted. These dielectrics generally have a lower parasitic cross talk as compared with dielectric materials that have a higher dielectric constant than 4.0.
  • the thickness of the dielectric material 52 may vary depending upon the dielectric material used as well as the exact number of dielectric layers within the dielectric material 52. Typically, and for normal interconnect structures, the dielectric material 52 has a thickness from about 50 to about 1000 ran.
  • the dielectric material 52 is formed utilizing any conventional deposition process including, but not limited to chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation, chemical solution deposition and spin-on coating.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • evaporation chemical solution deposition
  • chemical solution deposition chemical solution deposition and spin-on coating.
  • pad stack 54 is formed on an exposed upper surface of dielectric material 52.
  • the pad stack 54 comprises an oxide, nitride, oxynitride or multilayers thereof (e.g., a pad stack comprising a pad oxide and a pad nitride).
  • the pad stack 54 typically comprises a semiconductor oxide, semiconductor nitride and/or a semiconductor oxynitride.
  • the pad stack 54 comprises an oxide of silicon and/or a nitride of silicon.
  • the pad stack 54 may be formed utilizing any conventional deposition process including, for example, CVD, PECVD, evaporation, chemical solution deposition, physical vapor deposition (PVD) and atomic layer deposition.
  • the pad stack 54 is formed by a thermal process such as, for example, a thermal oxidation, a thermal nitridation and/or a thermal oxynitridation process.
  • the pad stack 54 is formed utilizing a combination of deposition and thermal processes.
  • the thickness of the pad stack 54 may vary depending on the number of materials within the pad stack itself as well as the technique that was used in forming the same. Typically, the pad stack 54 has a thickness from about 10 to about 80 nm.
  • At least one opening 56 is formed into the dielectric material 52 utilizing the pad stack 54 as a pattern mask.
  • the resultant structure including the at least one opening 56 is shown, for example, in FIG. 4B.
  • the at least one opening 56 may include a via opening, a line opening, a combined via and line opening, or any combinations thereof. In the drawings, three via openings are shown by way of a non-limiting example.
  • the at least one opening 56 is formed utilizing conventional lithography and etching.
  • the lithographic step includes forming a photoresist (organic, inorganic or hybrid) atop the pad stack 54 utilizing a conventional deposition process such as, for example, CVD, PECVD and spin-on coating. Following formation of the photoresist, the photoresist is exposed to a desired pattern of radiation. Next, the exposed photoresist is developed utilizing a conventional resist development process.
  • an etching step is performed to transfer the pattern from the patterned photoresist into first the pad stack 54 and then the dielectric material 52.
  • the patterned photoresist is typically removed from the surface of the structure after transferring the pattern into the pad stack 54 utilizing a conventional resist stripping process such as, for example, ashing.
  • the etching step used in forming the at least one opening 56 comprises a dry etching process (including reactive ion etching, ion beam etching, plasma etching or laser ablation), a wet chemical etching process or any combination thereof. Typically, reactive ion etching is used to form the at least one opening 56.
  • a diffusion barrier 58 and a conductive material 60 are formed into each of the at least one openings 56.
  • the diffusion barrier 58 comprises Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, IrTa 5 IrTaN, W, WN or any other material that can serve as a barrier to prevent conductive material from diffusing there through.
  • the thickness of the diffusion barrier 58 may vary depending on the deposition process used as well as the material employed. Typically, the diffusion barrier 58 has a thickness from about 4 to about 40 nm, with a thickness from about 7 to about 20 nm being more typical.
  • the diffusion barrier 58 which is located between the conductive material 60 and the dielectric material 52 is formed by any conventional deposition process including, for example, CVD, PECVD, PVD 5 sputtering and plating.
  • the conductive material 60 used in forming the conductive region of the interconnect structure includes, for example, polySi, a conductive metal, an alloy comprising at least one conductive metal, a conductive metal suicide or combinations thereof.
  • the conductive material 60 that is used in forming the conductive region is a conductive metal such as Cu, W or Al, with Cu or a Cu alloy (such as AlCu) being highly preferred in the present invention.
  • the conductive material 60 is formed into each of the openings 56 that are lined with the diffusion barrier 58 utilizing any conventional deposition process including, for example, CVD, PECVD, PVD, sputtering, plating, chemical solution deposition and electroless plating.
  • a planarization process such as, for example, chemical mechanical polishing (CMP) and/or grinding.
  • CMP chemical mechanical polishing
  • the planarization process provides a planar structure such as is shown in FIG. 3 C in which the upper surfaces of the dielectric material 52, the diffusion barrier 58 (which is now U-shaped) and the conductive material 60 are substantially coplanar with each other. It is noted that during the planarization process, the remaining pad stack 54 is removed from the structure.
  • a noble metal cap 62 is selectively formed atop the conductive material 60. As shown and discussed above, no noble metal cap 62 extends onto the surface of the diffusion barrier 58. Moreover, none of the noble metal cap 62 (or residues thereof) are deposited (or form) on the dielectric material 52 surface.
  • the term "noble metal” when referring to the cap 62 located directly atop the at least one conductive region (i.e., conductive material 60) includes any metal that is resistant to corrosion or oxidation.
  • the preferred noble metals that can be used in the present invention are selected from the group consisting of Ru, Ir, Rh, Pt, Co and alloys thereof. More preferably, the noble metal employed as the noble metal cap comprises Ru or a Ru alloy. In some embodiments, the noble metal cap 62 is comprised of a multilayered nobie metal or noble metal alloy stack.
  • the thickness of the noble metal cap 62 may vary depending on the type of noble metal present in the cap, the deposition technique and conditions used as well as the number of noble metals within the cap. Typically, the noble metal cap 62 has a thickness from about 1 to about 100 A, with a thickness from about 5 to about 50 A being more highly preferred.
  • the noble metal cap 62 is formed utilizing a low temperature chemical deposition process including, for example, CVD, PECVD, low pressure CVD and ALD.
  • low temperature it is meant a deposition temperature of about 200 0 C or less, with a deposition temperature of less than about 15O 0 C being even more preferred.
  • the deposition conditions are selected to provide a deposition rate of the noble metal cap 62 onto the conductive material 60 that is from about 0.2 to about 0.8 A/sec.
  • the selective deposition of the noble metal cap only to the conductive material 60 is enhanced by utilizing a low k dielectric material 52, with k about 3.0 or less, as well as a low temperature chemical deposition process. These two factors are critical in the present invention to avoid forming the noble metal cap onto the diffusion barrier material.
  • a dielectric capping layer 64 is formed across the entire structure providing the structure shown in FIG. 4D.
  • the resultant structure including the dielectric capping layer 64 is shown, for example, in FIG. 4E.
  • the dielectric capping layer 64 comprises any suitable dielectric capping material such as, for example, SiC, Si 4 NH 3 , SiO 2 , a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N 5 H) or multilayers thereof.
  • the thickness of the dielectric capping layer 64 may vary depending on the technique used to form the same as well as the material make-up of the layer. Typically, the dielectric capping layer 64 has a thickness from about 15 to about 100 ntn, with a thickness from about 25 to about 45 nm being more typical.
  • the dielectric capping layer 64 is formed utilizing any conventional deposition process including, for example, CVD, PECVD, evaporation, spin-on coating, chemical solution deposition and PVD.
  • FIG. 4E illustrates an interconnect structure in accordance with an embodiment of the present invention.
  • the inventive interconnect structure includes a dielectric material 52 having a dielectric constant of about 3.0 or less.
  • the dielectric material 52 has at least one conductive region (represented by conductive material 60) embedded within the dielectric material 52, said at least one conductive region having an upper surface.
  • a noble metal cap 62 is located directly on the upper surface of the at least one conductive region (i.e., conductive material 60). Because of the presence of the low k dielectric material and the low temperature chemical deposition process used in forming the noble metal cap, the noble metal cap 62 does not extend onto an upper surface of the diffusion barrier 58. Also, the noble metal cap 62 does not deposit on the dielectric material 52 surface and no residues of the noble metal form of the surface of the dielectric material 52.
  • reference numeral 6OA represents the upper surface of the conductive material 60.
  • inventive interconnect structure shown in FIG. 4E has better leakage control than prior art interconnect structures in which the metal cap extends onto the diffusion barrier that separates the embedded conductive material from the dielectric material.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention porte sur une structure d'interconnexion qui a une fiabilité d'électromigration améliorée sans dégradation de rendement de court-circuit, et une extensibilité de technologie améliorée. La structure d'interconnexion de l'invention comprend un matériau diélectrique ayant une constante diélectrique d'environ 3,0 ou moins. Le matériau diélectrique a au moins un matériau conducteur incorporé dans celui-ci. Un chapeau en métal noble est située directement sur une surface supérieure de la au moins une région conductrice. Le chapeau en métal noble ne s'étend pas sur une surface supérieure d'une barrière de diffusion qui sépare le au moins un matériau conducteur du matériau diélectrique, et le matériau de chapeau noble ne se dépose pas sur la surface diélectrique. L'invention porte également sur un procédé de fabrication d'une telle structure d'interconnexion à l'aide d'un procédé de dépôt chimique à basse température (environ 200°C ou moins).
PCT/US2009/042065 2008-08-07 2009-04-29 Structure d'interconnexion avec chapeau métallique auto-alignée avec une surface d'un matériau conducteur incorporé WO2010016958A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18786408A 2008-08-07 2008-08-07
US12/187,864 2008-08-07

Publications (1)

Publication Number Publication Date
WO2010016958A1 true WO2010016958A1 (fr) 2010-02-11

Family

ID=41663924

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/042065 WO2010016958A1 (fr) 2008-08-07 2009-04-29 Structure d'interconnexion avec chapeau métallique auto-alignée avec une surface d'un matériau conducteur incorporé

Country Status (1)

Country Link
WO (1) WO2010016958A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6261950B1 (en) * 1999-10-18 2001-07-17 Infineon Technologies Ag Self-aligned metal caps for interlevel metal connections
US20060264036A1 (en) * 2003-12-08 2006-11-23 International Business Machines Corporation Line level air gaps
US20070273044A1 (en) * 2006-05-25 2007-11-29 Chih-Chao Yang Adhesion enhancement for metal/dielectric interface
US20080108220A1 (en) * 2006-03-13 2008-05-08 International Business Machines Corporation Interconnect structure with a barrier-redundancy feature

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6261950B1 (en) * 1999-10-18 2001-07-17 Infineon Technologies Ag Self-aligned metal caps for interlevel metal connections
US20060264036A1 (en) * 2003-12-08 2006-11-23 International Business Machines Corporation Line level air gaps
US20080108220A1 (en) * 2006-03-13 2008-05-08 International Business Machines Corporation Interconnect structure with a barrier-redundancy feature
US20070273044A1 (en) * 2006-05-25 2007-11-29 Chih-Chao Yang Adhesion enhancement for metal/dielectric interface

Similar Documents

Publication Publication Date Title
US8013446B2 (en) Nitrogen-containing metal cap for interconnect structures
US8138604B2 (en) Metal cap with ultra-low k dielectric material for circuit interconnect applications
US8497580B2 (en) Noble metal cap for interconnect structures
EP2139037B1 (fr) Méthode de fabrication d'une structure d'interconnexion pour amélioration de l'électromigration
US8796853B2 (en) Metallic capped interconnect structure with high electromigration resistance and low resistivity
US8288276B2 (en) Method of forming an interconnect structure including a metallic interfacial layer located at a bottom via portion
US7834457B2 (en) Bilayer metal capping layer for interconnect applications
US8133767B2 (en) Efficient interconnect structure for electrical fuse applications
US8889546B2 (en) Discontinuous/non-uniform metal cap structure and process for interconnect integration
US8802563B2 (en) Surface repair structure and process for interconnect applications
WO2011084667A2 (fr) Structure d'interconnexion avec une couche de couverture en oxyde en forme de champignon et son procédé de fabrication
WO2010016958A1 (fr) Structure d'interconnexion avec chapeau métallique auto-alignée avec une surface d'un matériau conducteur incorporé

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09805306

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09805306

Country of ref document: EP

Kind code of ref document: A1