WO2010012207A1

WO2010012207A1 - Processor and processing method for fft/ifft

Info

Publication number: WO2010012207A1
Application number: PCT/CN2009/072877
Authority: WO
Inventors: 周圆
Original assignee: 中兴通讯股份有限公司
Priority date: 2008-07-28
Filing date: 2009-07-22
Publication date: 2010-02-04
Also published as: CN101330489A

Abstract

A processor and processing method for FFT/IFFT are provided. The processor includes: a control signal and address signal generator (102), which is configured to generate the control signal and the address signal; a random access memory module (104), which is configured to store input data and intermediate calculating results; a read-only memory module (106), which is configured to store twiddle factors; a data processing module (108), which is configured to implement butterfly operations on the input data according to the control signal and the twiddle factor, and then to transmit the intermediate calculating result back to the random access memory module to store. The invention can realize IFFT/FFT transforms compatible with any even point whose length is longer than or equal to four.

Description

Fast Fourier Transform / Fast Fourier Transform Processor

And its treatment method

TECHNICAL FIELD The present invention relates to communication or, in particular, to an FFT/IFFT (Fast Fourier Transform/Inverse Fast Fourier Transform) processor and a processing method thereof. BACKGROUND In current digital multimedia, a communication system needs to use FFT/IFFT of any even-length and multiple modes. For example, LTE (Long-Term Evolution) system requires 12 modulation, demodulation, and channel estimation. FFT/IFFT with 34 lengths of -1200 points, how to implement multi-mode compatible FFT/IFFT in FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) It is one of the keys to the realization of the whole system. At present, there are the following difficulties in implementing this function: (1) There is no FFT IP (Intellectual Property) core available, existing

The IP core only supports FFT/IFFT with a length of 2 to the power of N, such as: 512, 1024, and 2048 points of FFT/IFFT;

(2) There are many compatibility modes, the control structure is complex, and the design is difficult;

(3) The speed requirement is very high, for example: LTE system needs to complete FFT/IFFT with a total length of 1200 points in 41.66 microseconds;

(4) In practical applications, FFT/IFFT is required to be implemented on different FPGAs, so the FFT/IFFT processor architecture must have high portability. Based on the above difficulties, the prior art has not been able to provide an FFT/IFFT processor of any even length and multiple modes. SUMMARY OF THE INVENTION The present invention has been made in view of the problem that the prior art has not been able to provide an FFT/IFFT processor of any even length and multiple modes. To this end, the present invention aims to provide an FFT/IFFT processor and a processing method thereof. To solve at least one of the above problems. According to one aspect of the invention, a fast Fourier transform/inverse fast Fourier transform processor is provided. A fast Fourier transform/inverse fast Fourier transform processor according to the present invention includes: a control signal and address signal generator for generating a control signal and an address signal; a random access memory module for storing input data and an intermediate operation result; a module, configured to store a twiddle factor; a data processing module, configured to perform a butterfly operation on the input data according to the control signal and the twiddle factor, and send the intermediate operation result back to the random memory module for storage. Preferably, the address signal comprises a random memory address signal and a read only memory address signal, the control signal comprising a random access memory control signal, a read only memory control signal, a data processing module control signal. Preferably, the random access memory module transmits input data to the data processing module based on the random access memory address signal and the random access memory control signal. Preferably, the read only memory module reads the twiddle factor sent to the data processing module based on the read only memory address signal and the read only memory control signal. Preferably, the random access memory module comprises two four port random access memories. Preferably, the four port random access memory comprises: a two port random access memory, a register and a multiplexer operating at a frequency twice the processor system clock frequency. Preferably, the control signal and address signal generator are further configured to perform a transform length setting, and the two four-port random access memories respectively write the input data according to the transform length setting. Preferably, the data processing module includes two butterfly operators and multiplexers. According to another aspect of the present invention, a processing method of a fast Fourier transform/inverse fast Fourier transform processor is provided. Processing method package for fast Fourier transform/fast Fourier transform inverse transform processor according to the present invention The random access memory module loads the input data under the control of the control signal and the address signal generator, and sends the input data to the data processing module; the data processing module 4 controls the control signal and the read-only signal according to the control signal and the address signal generator. The rotation factor sent by the memory module performs a butterfly operation on the input data, and sends the intermediate operation result back to the random memory module for storage; the random access memory module unloads the data under the control of the control signal and the address signal generator. Preferably, the address signal comprises a random memory address signal and a read only memory address signal, the control signal comprising a random access memory control signal, a read only memory control signal, a data processing module control signal. Preferably, the random access memory module transmits input data to the data processing module based on the random access memory address signal and the random access memory control signal. Preferably, the read only memory module reads the twiddle factor sent to the data processing module based on the read only memory address signal and the read only memory control signal. Preferably, before performing the butterfly operation, the method further includes: controlling a signal and an address signal generator to perform a transform length setting; and dividing the input data into the first group of data and the second group of data having the same length according to the transform length setting, The first set of data is sequentially written to the first four port random access memory, and the second set of data is sequentially written to the second four port random access memory. Preferably, the method further includes: Step 1: The random access memory module reads the first data and the second data of the first group of data from the first four-port random access memory, and reads the first data from the second four-port random access memory. First data and second data of the two sets of data, wherein the first data and the second data of the first set of data are the same as the addresses of the first data and the second data of the second set of data; Step 2, the random access memory module The first data of the first set of data and the first data of the second set of data are sent to the first butterfly operator of the data processing module for butterfly operation, and the second data of the first set of data and the second set of data are The second data is sent to the second butterfly operator of the data processing module for butterfly operation; steps 1 and 2 are repeated until all data in the first set of data and the second set of data are read. Preferably, after reading all the data in the first set of data and the second set of data, the method further includes: Step 3: The random access memory module reads two of the first set of data from the first four-port random access memory. Data, and send the two data of the first set of data to the first butterfly operator of the data processing module for butterfly operation; Step 4, the random access memory module reads the second from the second four-port random access memory Two data of the group data, and two data of the second group of data are sent to the second butterfly operator of the data processing module for butterfly operation, wherein the two data of the second group of data are The addresses of the two data of the first set of data are the same; steps 3 and 4 are repeated until all data to be processed in the first set of data and the second set of data are read. Preferably, after the data processing module sends the operation result back to the random memory module for storage, the method further includes: the random memory module stores and outputs the operation result according to the read address and the storage address, wherein the read address is obtained. The address of the input data used in the operation result in the random access memory module. Through the present invention, the problem that the prior art has not been able to provide an FFT/IFFT processor of any even-length and multiple modes is solved, and an IFFT/FFT transform compatible with any even-numbered length of four or more can be realized. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In the drawings: FIG. 1 is a schematic diagram showing the structure of an FFT/IFFT processor according to an embodiment of the present invention; FIG. 2 is a flowchart of a processing method of an FFT/IFFT processor according to an embodiment of the present invention; 3 is a schematic diagram of a data path structure of an FFT/IFFT processor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT According to an embodiment of the present invention, an FFT/IFFT processor and a processing method thereof are provided, which can be applied to a communication system, a communication method, and a processing product in digital multimedia, and are applicable to a communication system. Processing of FFT/IFFT with even length and variable length. In the present invention, a four-port memory module, a butterfly operator (BF), etc. are introduced, which can realize continuous uninterrupted processing of data by using dual channels under a non-pulsating array structure, and reduce processor-to-chip area requirements. At the same time, the required FFT/IFFT operation can be done using a lower clock frequency. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. Apparatus Embodiments According to an embodiment of the present invention, an FFT/IFFT processor is provided. 1 is a schematic diagram of a structure of an FFT/IFFT processor according to an embodiment of the present invention. As shown in FIG. 1, the processor includes a control signal and address signal generator 102, a RAM (Random Access Memory) module 104, The ROM (Read Only Memory) module 106, the data processing module 108, the following is a detailed description of the structure of the processor: a control signal and address signal generator 102 for generating a control signal and an address signal, wherein The address signal includes a RAM address signal and a ROM address signal, and the control signal includes a RAM control signal, a ROM control signal, and a data processing module control signal; the control signal and address signal generator 102 is further configured to perform a transform length setting (selection), that is, The length of the input data is divided into two parts of equal length.

The RAM module 104 is connected to the control signal and address signal generator 102 for storing input data; the RAM module may include two four-port RAMs, wherein each of the four-port RAMs includes an operating frequency twice the clock frequency of the processor system Two-port RAM, attached p register, and multiplexer; the two four-port RAM respectively write input data according to the conversion length setting of the control signal and address signal generator 102, and according to the control signal and The RAM address signal and the RAM control signal generated by the address signal generator 102 transmit input data to the data processing module. Specifically, the data of the previous portion of the conversion length setting is written to the first four-port RAM, and the latter portion of the data is written to the second four-port RAM. ROM module 106, connected to control signal and address signal generator 102, data processing module

108. For storing a twiddle factor, reading a rotation factor sent to the data processing module according to the ROM address signal generated by the control signal and the address signal generator 102 and the ROM control signal. The data processing module 108 is connected to the control signal and address signal generator 102, the RAM module 104, and the ROM module 106. The data processing module 108 includes two BFs and a multiplexer for generating the data according to the control signal and the address signal. The control signal generated by the device 102 and the twiddle factor sent from the ROM module 106 perform a butterfly operation on the input data sent from the RAM module 104, and the operation result is sent back to the RAM module 104 for storage. The processor provided by this embodiment includes two identical four-port RAMs and two identical BFs, and the control thereof is almost identical. This structure can simplify the design of the design; the processor can be compatible with a length of four or more. IFFT/FFT conversion of any number of points, using four-port RAM to implement four The continuous reading and writing of data not only improves the processing speed, but also provides the basis for the design of the more centralized control unit. Method Embodiments According to an embodiment of the present invention, a processing method of an FFT/IFFT processor is provided. 2 is a flowchart of a processing method of an FFT/IFFT processor according to an embodiment of the present invention. As shown in FIG. 2, the method includes the following steps S202 to S206: Step S202, the RAM module is in a control signal and The input signal is loaded under the control of the address signal generator, and the input data is sent to the data processing module; in step S204, the data processing module detects the control signal generated by the control signal and the address signal generator, and the twiddle factor sent by the ROM module. Performing a butterfly operation on the input data, and returning the intermediate operation result to the RAM module for storage. Thereafter, the RAM module stores and outputs the operation result according to the read address and the storage address, wherein the read address means obtaining the The address of the input data used in the operation result is in the RAM module; in step S206, the RAM module unloads the data under the control of the control signal and the address signal generator. Before the step S204, the method further includes the following steps (42) to (46):

(42) the control signal and the address signal generator perform a transform length setting;

(44) The RAM module transmits the input data to the data processing module according to the RAM address signal and the RAM control signal; (46) the ROM module reads the twiddle factor sent to the data processing module according to the ROM address signal and the ROM control signal. Specifically, the processing (44) may specifically include the following operations (202) to (214):

(202) According to the transform length setting, the input data is divided into the first group data and the second group data of equal length, and the first group data is sequentially written into the first four port RAM (the cylinder is called 4-Port RAMI). , the second set of data is sequentially written into the second four-port RAM (the cartridge is called 4-Port RAM2);

(204) The RAM module reads the first data and the first data of the first group of data from the 4-Port RAMI Two data, reading the first data and the second data of the second group of data from the second four-port RAM, wherein the addresses of the first data and the second data of the first group of data and the first of the second group of data The data and the address of the second data are the same;

(206) the RAM module sends the first data of the first set of data and the first data of the second set of data to the first butterfly operator of the data processing module (referred to as BF1) for butterfly operation, and will be first The second data of the group data and the second data of the second group of data are sent to a second butterfly operator of the data processing module (called BF2) for butterfly operation;

(208) repeating steps (204) and (206) until all data in the first set of data and the second set of data are read; (210) the RAM module reads the first set of data from the 4-Port RAMI Two data, and two data of the first group of data are sent to the BF1 of the data processing module for butterfly operation;

(212) The RAM module reads two data of the second group of data from the 4-Port RAM2, and sends two data of the second group of data to the BF2 of the data processing module for butterfly operation, wherein the second group of data The addresses of the two data are the same as the addresses of the two data of the first group of data; (214) repeating steps (210) and (212) until the first set of data and the second set of data are read All data. The technical solution in this embodiment compares the control of the operation process, and for the calculation of any cardinality, the corresponding operation result returns to the position of the read data, and no replacement process is required in the middle, which can save 4 cycles. The specific implementation process of the embodiment of the present invention will be described below with reference to FIG. 3 by taking a 12-point FFT operation as an example. 3 is a schematic diagram of a data path structure of an FFT/IFFT processor in accordance with an embodiment of the present invention. In Figure 3, the 4-Port RAM includes 4-Port RAMI and 4-Port RAM2. In 4-Port RAMI and 4-Port RAM2, PortA and PortB are included, respectively, where PortA includes Addr (connected to Addra). Out and Addrb_out or Addrc_out and Addrd_out, address signals for reading data output from the 4-Port RAMI or 4-Port RAM2 to the data processing unit) and Dout (connected to A douta and B doutb or C doutc and D doutd, used to feed data to the data processing module), PortB includes Din (connected to input A and B or input C and D) and Addr (connected to Addra-in and Addrb-in or Addrc-in and Addrd—in, for reading The address signal of the data input to 4-Port RAMI or 4-Port RAM2); the data processing unit includes BF 1 and BF2; and the ROM is used to provide a twiddle factor to the data processing module. As shown in FIG. 3, the processing of the following steps (301) to (310) is included:

(301) The processor loads the data, and writes the data [xO, xl, x2, x3, x4, x5] from Din to 4-Port RAMI;

(302) Write data [x6, x7, x8, x9, xlO, xll] from Din to 4-Port RAM2;

(303) Read data xO and xl of address 0, 1 in 4-Port RAMI from A douta and B doutb, respectively, and read data x6 of address 0, 1 in 4-Port RAM2 from C doutc and D doutd, respectively. And x7; send xO and x6 to BF1 for butterfly operation, send xl and x7 to BF2 for butterfly operation; write xO and x6 operation results from A and C to 4-Port RAMI and 4-Port RAM2 Address 0, ^) win xl and x7 operation results from B and D write 4-port RAMI and 4-port RAM2 address 1;

(304) Transform the address, complete the butterfly operations of x2 and x8, x3 and x9, and x4 and xlO, x5 and xll according to the method of step 3; (305) read from A douta and B doutb respectively in 4-Port RAMI The data of address 0, 3 is sent to BF 1 for butterfly operation, and the operation result is written back to address 0, 3 from A and B; meanwhile, it is read from C doutc and D doutd at address 4-port RAM2 0, 3 Data, sent to BF2 for butterfly operation, and write the operation result from C and D back to address 0, 3;

(306) Convert the address, and perform the butterfly operations on the addresses 1 and 4 and the addresses 2 and 5 respectively for 4-Port RAMI and 4-Port RAM2 according to the method in step 5;

(307) Convert the address and perform the butterfly operations on the addresses 1 and 2 and the addresses 4 and 5 respectively for 4-Port RAMI and 4-Port RAM2 according to the method in step 5;

(308) Convert the address, according to the method in step 5, perform the butterfly operations of the addresses 0 and 1 and the data in the addresses 3 and 4 for the 4-Port RAMI and the 4-Port RAM2 respectively; (309) change the address, according to the steps The method in 5, the 4-port RAMI and the 4-Port RAM2 respectively perform the butterfly operations of the addresses 1 and 2, and the data in the addresses 4 and 5;

(310) Unload data (output from Output), unload address order is [0639174102 8 5 11 ] , where address 0-5 corresponds to 4-port RAM 1 address 0-5, and address 6-11 corresponds to 4-port RAM2 address 0-5. According to an embodiment of the present invention, there is also provided a computer readable medium having stored thereon computer executable instructions for causing a computer or processor to perform, for example, when executed by a computer or processor The processing of steps S202 to S204 shown in Fig. 2, preferably, the above-described method embodiments can be performed. The processor provided by the embodiment of the invention has a fast operation speed and a relatively simple processing process. It takes 6600 clock cycles to process 1200 points of FFT/IFFT, and takes 41.27 4 start seconds at a frequency of 160 MHz, and consumes at a frequency of 246 MHz. 26.83 seconds; this architecture is suitable for implementations based on different vendors, different types of FPGAs or ASICs; this architecture is suitable for FFT/IFFT of any even point with a length greater than or equal to four, since jt匕 can be used not only for LTE systems, but also for other OFDM applications. (Orthogonal Frequency Division Multiplexing, Orthogonal Frequency Division Multiplexing) technology system. In addition, the implementation of the present invention does not modify the system architecture and the current processing flow, is easy to implement, facilitates promotion in the technical field, and has strong industrial applicability. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be separately fabricated into individual integrated circuit modules, or they may be Multiple modules or steps are made into a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim

A fast Fourier transform/inverse fast Fourier transform processor, comprising: a control signal and an address signal generator for generating a control signal and an address signal; a random access memory module for storing input data and an intermediate operation Result; a read only memory module for storing a twiddle factor;

And a data processing module, configured to perform a butterfly operation on the input data according to the control signal and the twiddle factor, and send the intermediate operation result back to the random access memory module for storage.

2. The processor of claim 1 wherein:

The address signals include random memory address signals and read only memory address signals, the control signals including random access memory control signals, read only memory control signals, data processing module control signals.

3. The processor of claim 2, wherein

The random access memory module transmits the input data to the data processing module based on the random memory address signal and the random memory control signal.

4. The processor of claim 2, wherein:

The read only memory module reads the twiddle factor sent to the data processing module based on the read only memory address signal and the read only memory control signal.

The processor according to claim 1, wherein the random access memory module comprises two four-port random access memories.

The processor according to claim 5, wherein the four-port random access memory comprises: a two-port random access memory, a register and a multiplexer whose operating frequency is twice the clock frequency of the processor system.

The processor according to claim 5, wherein the control signal and the address signal generator are further configured to perform a transform length setting, and the two four-port random access memories are respectively set according to the transform length To write the input data.

8. The processor of claim 1 wherein said data processing module comprises two butterfly operators and multiplexers.

9. A method of processing a fast Fourier transform/inverse fast Fourier transform processor, the method comprising:

The random access memory module loads the input data under the control of the control signal and the address signal generator, and sends the input data to the data processing module;

The data processing module performs a butterfly operation on the input data according to the control signal generated by the control signal and the address signal generator and a rotation factor sent by the read-only memory module, and sends the intermediate operation result back to the random The memory module is stored;

The random access memory module unloads data under the control of the control signal and address signal generator.

10. The method of claim 9 wherein:

11. The method of claim 10, wherein

12. The method according to claim 10, characterized in that

The method according to claim 12, wherein before the performing the butterfly operation, the method further comprises:

The control signal and the address signal generator perform a transform length setting; according to the transform length setting, the input data is divided into a first group of data and a second group of data of equal length, and the first group of data is sequentially The first four-port random access memory is written, and the second set of data is sequentially written to the second four-port random access memory.

14. The method of claim 13, further comprising:

Step 1: The random access memory module reads first data and second data of the first group of data from the first four-port random access memory, and reads the second group from the second four-port random access memory. First data and second data of the data, wherein the first data and the second data of the first group of data are the same as the addresses of the first data and the second data of the second group of data;

Step 2, the random access memory module sends the first data of the first set of data and the first data of the second set of data to a first butterfly operator of the data processing module to perform a butterfly operation. And sending the second data of the first set of data and the second data of the second set of data to a second butterfly operator of the data processing module to perform a butterfly operation;

Step 1 and step 2 are repeated until all data in the first set of data and the second set of data are read.

The method according to claim 14, wherein after the reading of all the data in the first set of data and the second set of data, the method further comprises:

Step 3: The random access memory module reads two data of the first group of data from the first four-port random access memory, and sends two data of the first set of data into the data processing module. The first butterfly operator performs a butterfly operation;

Step 4, the random access memory module reads two data of the second set of data from the second four-port random access memory, and sends two data of the second set of data into the data processing module. The second butterfly operator performs a butterfly operation, wherein two data of the second group of data are the same as addresses of two data of the first group of data;

Step 3 and step 4 are repeated until all data to be processed in the first set of data and the second set of data are read.

The method according to claim 9, wherein after the data processing module returns the operation result to the random memory module for storage, the method further comprises: the random memory module according to the reading The operation result is stored and outputted in a manner corresponding to the storage address, wherein the read address is an address of the input data used to obtain the operation result in the random access memory module.