CN107391439B - Processing method capable of configuring fast Fourier transform - Google Patents
Processing method capable of configuring fast Fourier transform Download PDFInfo
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Abstract
The invention discloses a processing method capable of configuring fast Fourier transform, which comprises the following steps: the arithmetic unit receives input data; the twiddle factor generating unit generates twiddle factors required by butterfly operation and sends the twiddle factors to the arithmetic unit; the arithmetic unit receives a mode selection signal for representing and determining a data operation mode of the arithmetic unit, wherein the data operation mode comprises a time extraction mode or a frequency extraction mode; the arithmetic unit carries out butterfly operation on input data under an operation mode corresponding to the mode selection signal according to the twiddle factor to obtain an operation result; the arithmetic unit outputs an arithmetic result. The arithmetic unit receives the mode selection signal for representing and determining the data operation mode of the arithmetic unit and then performs butterfly operation, so that the processing method capable of configuring the fast Fourier transform can process data in different scenes of a time extraction mode or a frequency extraction mode, and the application flexibility of the processing method is improved.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a processing method capable of configuring Fast Fourier Transform (FFT).
Background
Currently, most broadband communication systems employ Orthogonal Frequency Division Modulation (OFDM) technology, wherein an FFT module is a core unit of the OFDM communication system. In order to meet the requirement that the OFDM communication system can operate in different media and different operating frequency bands, the design of the FFT module must support various required data lengths. In order to meet the requirements of different design architectures of the OFDM communication system, the design of the FFT module needs to consider the compatibility problem of a Time extraction mode (differentiation-In-Time, DIT) and a Frequency extraction mode (differentiation-In-Frequency, DIF).
In the prior art, chinese patent publication No. CN101330489A discloses a Fast Fourier transform/Inverse Fast Fourier transform processor (FFT/IFFT) and a processing method thereof, the processor including: a control signal and address signal generator for generating a control signal and an address signal; the random access memory module is used for storing input data and intermediate operation results; the read-only memory module is used for storing the twiddle factors; and the data processing module is used for performing butterfly operation on input data according to the control signal and the twiddle factor, and sending the intermediate operation result back to the memory module for storage, so that the FFT/IFFT conversion of any even number point with the compatible length being more than or equal to four is realized. However, the fft/ifft processor and the processing method thereof support only one of DIT and DIF, and have poor flexibility.
Therefore, how to realize the compatibility of the use of the DIT and DIF modes in the fft/ifft processor becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to solve the technical problem that DIT and DIF modes in a fast Fourier transform/inverse fast Fourier transform processor cannot be compatible.
Therefore, according to a first aspect, an embodiment of the present invention provides a processing method of fast fourier transform, including the following steps: the arithmetic unit receives input data; the twiddle factor generating unit generates twiddle factors required by butterfly operation and sends the twiddle factors to the arithmetic unit; the arithmetic unit receives a mode selection signal for representing and determining a data operation mode of the arithmetic unit, wherein the data operation mode comprises a time extraction mode or a frequency extraction mode; the arithmetic unit carries out butterfly operation on input data under an operation mode corresponding to the mode selection signal according to the twiddle factor to obtain an operation result; the arithmetic unit outputs an arithmetic result.
Optionally, the processing method of the fast fourier transform further includes: the storage address generating unit generates a read address and a write address for representing an intermediate result stored in the memory unit, and sends the read address and the write address to the memory unit, wherein the intermediate result is an operation result in the process of butterfly operation of the arithmetic unit on input data; the arithmetic unit writes the intermediate result into the memory unit according to the write address; the arithmetic unit reads the intermediate result of the read address mapping according to the read address.
Optionally, the operator unit comprises: the input data is 2N channel complex data, wherein N is a positive integer, and when the data operation mode is a time extraction mode, the arithmetic unit performs butterfly operation on the input data in the operation mode corresponding to the mode selection signal according to the twiddle factor to obtain an operation result, wherein the operation result comprises: the exchange unit group converts the input data or the intermediate result into N-channel complex data; the multiplier group multiplies the N-channel complex data by the twiddle factor and then sends the multiplied data into the butterfly unit group; the butterfly unit group performs butterfly operation on the received data to obtain N-channel complex data after the butterfly operation; the exchange unit group converts the N-channel complex data after butterfly operation into 2N-channel complex data, and the 2N-channel complex data is an intermediate result or an operation result.
Optionally, the operator unit comprises: the input data is 2N channel complex data, wherein N is a positive integer, and when the data operation mode is a frequency extraction mode, the arithmetic unit performs butterfly operation on the input data in the operation mode corresponding to the mode selection signal according to the twiddle factor to obtain an operation result, wherein the operation result comprises: the exchange unit group converts the input data or the intermediate result into N-channel complex data and then sends the N-channel complex data into the butterfly unit group; the butterfly unit group performs butterfly operation on the received data to obtain N-channel complex data after the butterfly operation; the multiplier group multiplies the N-channel complex data after butterfly operation by the twiddle factor and then sends the multiplied data to the exchange unit group; the exchange unit group converts the received data into 2N channel complex data, and the 2N channel complex data is an intermediate result or an operation result.
Optionally, before the arithmetic unit performs a butterfly operation on the input data in an operation mode corresponding to the mode selection signal according to the twiddle factor to obtain an operation result, the method further includes: the arithmetic unit receives a transformation mode signal for representing and determining a Fourier transformation mode, wherein the Fourier transformation mode comprises fast Fourier transformation and inverse fast Fourier transformation; judging whether the Fourier transform mode is fast Fourier inverse transform or not; and when the Fourier transform mode is inverse fast Fourier transform, performing conjugation processing on the rotation factor, and performing real-virtual exchange processing on the intermediate result.
Optionally, before the computing unit performs a butterfly operation on the input data in the operation mode corresponding to the mode selection signal according to the twiddle factor to obtain the operation result, the method further includes: the arithmetic unit receives an algorithm selection signal used for representing and determining a Fourier transform algorithm, wherein the Fourier transform algorithm comprises a base-2 algorithm and a base-4 algorithm; judging whether the Fourier transform algorithm is a base-2 algorithm; and when the Fourier transform algorithm is the radix-2 algorithm, performing butterfly operation on a part of butterfly units in the butterfly unit group.
Optionally, the processing method of the fast fourier transform further includes: the iteration control counter unit counts the butterfly operations in the arithmetic unit, wherein: a butterfly calculator in the iteration control counter unit counts butterfly operations in each section to obtain the value of a butterfly counter; and calculating the number of the sections of butterfly operation by a section counter in the iteration control counter unit to obtain the value of the section counter.
Optionally, the twiddle factor generation unit includes: the system comprises an index generation module, an address conversion module and a real-virtual exchange module; the twiddle factor generating unit generates twiddle factors required for performing butterfly operation, and sends the twiddle factors to the arithmetic unit, and the twiddle factors comprise: the twiddle factor generating unit stores the effective twiddle factors into a read-only memory; the index generation module generates an index of the twiddle factor according to the counting value of the iteration control counter unit by adopting the following formula:
where k is the exponent of the twiddle factor of the radix-4 algorithm, k1And k2Is the exponent of the twiddle factor of the radix-2 algorithm, N is the length of the input data, J is the value of the butterfly counter, I is the value of the segment counter; the address conversion module converts the exponent of the twiddle factor of the radix-4 algorithm or the exponent of the twiddle factor of the radix-2 algorithm into a read-only memory address; real and virtual switching module based on read-only memoryThe address reads the effective twiddle factor from the read-only memory and converts it to a twiddle factor.
Optionally, the memory address generation unit generates the memory address using a natural sequential address generation approach.
Optionally, the read address and the write address have the same physical address.
The technical scheme provided by the embodiment of the invention has the following advantages: the arithmetic unit receives the mode selection signal for representing and determining the data operation mode of the arithmetic unit, the data operation mode comprises a time extraction mode or a frequency extraction mode, and then butterfly operation is performed, so that the configurable fast Fourier transform processing method can process data in different scenes of the time extraction mode or the frequency extraction mode, and the application flexibility of the processing method is improved.
As an optional technical solution, the switching unit group in the arithmetic unit converts the input data or the intermediate result of the 2N-path complex data into the N-path complex data, so that the arithmetic unit converts the 2N-path complex data calculated in one cycle into the N-path complex data calculated in one cycle, and the input data or the intermediate result of the 2N-path complex data is calculated in two cycles, thereby reducing the number of multipliers in the butterfly operation and reducing the area of the processor when using the processing method of fast fourier transform.
As an optional technical solution, the arithmetic unit receives a transformation mode signal for characterizing and determining a fourier transform algorithm, so that an algorithm for performing fourier transform by the arithmetic unit is determined to be a radix-2 algorithm or a radix-4 algorithm, rather than only being able to use the radix-2 algorithm or only being able to use the radix-4 algorithm for performing a butterfly operation, and therefore, when the data length of the input data is a power of 4, the arithmetic unit receives the transformation mode signal for characterizing and determining the fourier transform algorithm, so that the algorithm for performing fourier transform by the arithmetic unit is determined to be the radix-4 algorithm rather than continuously using the radix-2 algorithm, thereby improving the processing efficiency of the input data.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a processing method for configurable fast fourier transform disclosed in this embodiment;
fig. 2 is a flow chart of a configurable fft-processed signal disclosed in this embodiment;
FIG. 3 is a flowchart illustrating an operation of the arithmetic unit according to the present embodiment;
FIG. 4 is a flow chart of processing signals of the arithmetic unit disclosed in the present embodiment;
FIG. 5 is another flowchart illustrating the operation of the arithmetic unit disclosed in the present embodiment;
fig. 6 is a flowchart illustrating the operation of the twiddle factor generating unit disclosed in this embodiment.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to achieve the problem of compatible use of time extraction method and frequency extraction method in the fft/ifft processor, this embodiment provides a processing method of configurable fft, please refer to fig. 1, which is a flowchart of the processing method of configurable fft, and the processing method of configurable fft includes the following steps:
in step S100, the operator unit receives input data. Referring to fig. 2, in this embodiment, the arithmetic unit 3 directly receives input data, rather than storing the input data in the memory unit 3 and then reading the input data from the memory unit, so that the requirement of performing fast fourier transform in different data input sequences in the time extraction manner or the frequency extraction manner can be met.
In step S200, the twiddle factor generating unit generates twiddle factors required for performing the butterfly operation, and sends the twiddle factors to the arithmetic unit. Referring to fig. 2, in the present embodiment, the number of twiddle factors generated by the twiddle factor generating unit 4 is determined by the number of input data and the transform algorithm for performing the fft, for example, when the input data is 4-channel complex data, 2 twiddle factors are required if the transform algorithm for the fft is the radix-2 algorithm, and 3 twiddle factors are required if the transform algorithm for the fft is the radix-4 algorithm, as shown in fig. 2
And
as shown. It should be noted that the above specific numerical values are only specific examples for facilitating the understanding of the solution of the present embodiment by those skilled in the art, and the above specific numerical values should not be construed as limiting the technical solution of the present embodiment.
In step S300, the arithmetic unit receives a mode selection signal for characterizing and determining a data operation mode of the arithmetic unit, wherein the data operation mode includes a time extraction mode and a frequency extraction mode. Referring to fig. 2, in the present embodiment, the mode selection signal for characterizing and determining the data operation mode of the arithmetic unit 3 is determined by the current operation scenario of fourier transform according to the requirement on the data input and output sequence, so that the configurable fast fourier transform processing method can meet the requirement on processing data in different scenarios applicable to the time extraction manner or the frequency extraction manner. In a specific embodiment, the mode selection signal for characterizing the data operation mode of the operator unit 3 is received via the I/O device, but may be preset.
In step S400, the arithmetic unit performs a butterfly operation on the input data in the operation mode corresponding to the mode selection signal according to the twiddle factor to obtain an operation result. Referring to fig. 2, in the present embodiment, when the mode selection signal received by the arithmetic unit 3 for characterizing and determining the data operation mode of the arithmetic unit 3 is the time extraction mode, the arithmetic unit 3 is configured to the working mode corresponding to the time extraction mode, and when the mode selection signal received by the arithmetic unit 3 for characterizing and determining the data operation mode of the arithmetic unit 3 is the frequency extraction mode, the arithmetic unit 3 is configured to the operation mode corresponding to the frequency extraction mode.
In step S500, the arithmetic unit outputs an arithmetic result. Referring to fig. 2, in the present embodiment, the arithmetic unit 3 directly outputs the operation result, rather than storing the operation result in the memory unit 2 and then passively reading the operation result, so that different requirements for the data output sequence in the time decimation mode or the frequency decimation mode can be satisfied.
In an optional embodiment, the processing method of the configurable fast fourier transform further includes:
the memory address generating unit 1 generates a read address and a write address for characterizing the storage of the intermediate result in the memory unit 2 and sends the read address and the write address to the memory unit 2. In the present embodiment, the intermediate result is an operation result of the operation unit 3 performing a butterfly operation on the input data. Referring to fig. 2, in the present embodiment, the read address refers to an address at which the intermediate result is stored in the memory unit 2 and the arithmetic unit 3 reads the intermediate result from the memory unit 2, and the write address refers to an address at which the arithmetic unit 3 writes the intermediate result into the memory unit 2. In this embodiment, the number of the read addresses and the write addresses for representing the intermediate results stored in the memory unit 2 is equal to the number of the input data, for example, when the input data is 4 complex data, the memory generating unit generates 4 read addresses corresponding to 4 memory fields for storing the intermediate results and generates 4 write addresses for storing new intermediate results generated after the intermediate results are operated by the operator unit 3. In this embodiment, in order to reduce the cost, the memory unit 2 is a single-port sram, and since the single-port sram requires that the read and write operations cannot occur in the same clock cycle, in a specific embodiment, the read address and the write address may be generated by using a read and write collision-free policy, that is, the read address and the write address have the same physical address.
The operator unit 3 writes the intermediate result to the memory unit 2 in accordance with the write address. Referring to fig. 2, in the present embodiment, the intermediate result is a set of data with the number equal to the number of input data, the arithmetic unit 3 writes the intermediate result into the memory unit 2, and the memory unit 2 stores the intermediate result in the storage area corresponding to the number of write addresses equal to the number of intermediate results.
The arithmetic unit 3 reads the intermediate result of the read address mapping by the read address. Referring to fig. 2, in the present embodiment, the arithmetic unit 3 reads the intermediate result from the memory domain corresponding to the read address generated by the memory address generating unit 1.
In an alternative embodiment, the operator unit 3 comprises: the input data of the switching unit group, the multiplier group and the butterfly unit group is 2N-channel complex data, where N is a positive integer, and when the data operation mode is a time extraction mode, the method includes: the exchange unit group converts the input data or the intermediate result into N-channel complex data; the multiplier group multiplies the N-channel complex data by the twiddle factor and then sends the multiplied data into the butterfly unit group; the butterfly unit group performs butterfly operation on the received data to obtain N-channel complex data after the butterfly operation; the exchange unit group converts the N-channel complex data after butterfly operation into 2N-channel complex data, and the 2N-channel complex data is an intermediate result or an operation result. Specifically, referring to fig. 3, an operation flow chart of the arithmetic unit 3 is shown, wherein the operation process includes:
in step S410, the switch unit group converts the input data or the intermediate result into N-channel complex data. Referring to fig. 4, in the present embodiment, the processing signal flow of the arithmetic unit is a diagram, in the present embodiment, the switching unit group converts the input data or the intermediate result, which is 2N-channel complex data, into two sets of N-channel complex data, the arithmetic unit 3 may perform the operation on the first set of N-channel complex data in a first clock cycle, and perform the operation on the second set of N-channel complex data in a second clock cycle, so that the arithmetic unit 3 converts the 2N-channel complex data calculated in one clock cycle into the N-channel complex data calculated in one clock cycle, and completes the calculation on the input data of the 2N-channel complex data in two clock cycles, thereby reducing the number of multipliers in the butterfly operation. In particular, the overall processing time of the processing method capable of configuring the fast fourier transform can be shortened by increasing the frequency of the clock cycle, and thus, the processing time of the processing method capable of configuring the fast fourier transform does not become longer by dividing the operation in one clock cycle into two clock cycles.
In step S420, the multiplier group multiplies the N-channel complex data by the twiddle factor and sends the multiplied data to the butterfly unit group. Referring to fig. 4, in the present embodiment, the number of complex multipliers in the multiplier group is determined by the value of N, and in the specific embodiment, when the input data is 4-way complex data, the multiplier group is composed of two complex multipliers. In this embodiment, the multiplier bank multiplies the first set of N-path complex data by the twiddle factor in a first clock cycle, and multiplies the second set of N-path complex data by the twiddle factor in a second clock cycle.
In step S430, the butterfly unit performs butterfly operation on the received data to obtain N-channel complex data after butterfly operation. Referring to fig. 4, in the present embodiment, the number of butterfly units in the butterfly unit group is determined by the value of N. In this embodiment, a butterfly unit in the butterfly unit group performs butterfly operation on a group of N-channel complex data in a first clock cycle to obtain N-channel complex data after the first butterfly operation, a butterfly unit in the butterfly unit group performs butterfly operation on a second group of N-channel complex data in a second clock cycle to obtain N-channel complex data after the second butterfly operation, the N-channel complex data after the first butterfly operation and the N-channel complex data after the second butterfly operation enter the switching unit group for switching to form two groups of recombined N-channel complex data, and the recombined N-channel complex data enter the butterfly operation group again for butterfly operation in the first clock cycle and the second clock cycle, respectively. For example, when the input data is 4-channel complex data, which is s, t, u and v, respectively, one butterfly unit in the butterfly unit group performs butterfly operation on the 2-channel complex data u and v in a first clock cycle to obtain u and v after the butterfly operation, one butterfly unit in the butterfly unit group performs butterfly operation on the 2-channel complex data s and t in a second clock cycle to obtain s and t after the butterfly operation, and u and v after the butterfly operation and s and t are exchanged by the exchange unit group to form 2 groups of 2-channel complex data t and v and s and u after recombination, and enter the butterfly operation group again for butterfly operation in the first clock cycle and the second clock cycle, respectively. It should be noted that the above specific numerical values are only specific examples for facilitating the understanding of the solution of the present embodiment by those skilled in the art, and the above specific numerical values should not be construed as limiting the technical solution of the present embodiment.
In step S440, the switching unit group converts the N-channel complex data after the butterfly operation into 2N-channel complex data. In this embodiment, the 2N-path complex data is an intermediate result or an operation result, specifically, when the count of the counter in the middle of the iteration control counter 5 does not reach the maximum value, the 2N-path complex data is an intermediate result, and when the count of the counter in the middle of the iteration control counter 5 reaches the maximum value, the 2N-path complex data is an operation result. Referring to fig. 4, in the embodiment, the switching unit group converts two sets of N-channel complex data in two cycles into an operation result or an intermediate result of a set of 2N-channel complex data, when the 2N-channel complex data is the intermediate result, the arithmetic unit 3 writes the intermediate result into the memory unit 2, and when the 2N-channel complex data is the operation result, the arithmetic unit 3 outputs the operation result.
In an alternative embodiment, the operator unit 3 comprises: the input data of the switching unit group, the multiplier group and the butterfly unit group is 2N-channel complex data, where N is a positive integer, and when the data operation mode is a frequency extraction mode, the method includes: the exchange unit group converts the input data or the intermediate result into N-channel complex data and then sends the N-channel complex data into the butterfly unit group; the butterfly unit group performs butterfly operation on the received data to obtain N-channel complex data after the butterfly operation; the multiplier group multiplies the N-channel complex data after butterfly operation by the twiddle factor and then sends the multiplied data to the exchange unit group; the exchange unit group converts the received data into 2N channel complex data, and the 2N channel complex data is an intermediate result or an operation result. Specifically, please refer to fig. 5, which is another operation flow chart of the operation unit, the operation process includes:
in step S401, the switch unit group converts the input data or the intermediate result into N-channel complex data and sends the N-channel complex data to the butterfly unit group. Referring to fig. 4, in the embodiment, the switching unit group converts the input data or the intermediate result of the 2N channel complex data into two sets of N channel complex data, the arithmetic unit 3 may perform the operation on the first set of N channel complex data in a first clock cycle, and perform the operation on the second set of N channel complex data in a second clock cycle, so that the arithmetic unit converts the 2N channel complex data calculated in one cycle into the N channel complex data calculated in one cycle, and completes the calculation on the input data of the 2N channel complex data in two cycles, thereby reducing the number of multipliers in the butterfly operation. In particular, the overall processing time of the processing method capable of configuring the fast fourier transform can be shortened by increasing the frequency of the clock cycle, and thus, the processing time of the processing method capable of configuring the fast fourier transform does not become longer by dividing the operation in one clock cycle into two clock cycles.
In step S402, the butterfly unit performs butterfly operation on the received data to obtain N-channel complex data after butterfly operation. Referring to fig. 4, in the present embodiment, the number of butterfly units in the butterfly unit group is determined by the value of N. In this embodiment, a butterfly unit in the butterfly unit group performs butterfly operation on a group of N-channel complex data in a first clock cycle to obtain N-channel complex data after the first butterfly operation, a butterfly unit in the butterfly unit group performs butterfly operation on a second group of N-channel complex data in a second clock cycle to obtain N-channel complex data after the second butterfly operation, the N-channel complex data after the first butterfly operation and the N-channel complex data after the second butterfly operation enter the switching unit group for switching to form two groups of recombined N-channel complex data, and the recombined N-channel complex data enter the butterfly operation group again for butterfly operation in the first clock cycle and the second clock cycle, respectively. For example, when the input data is 4-channel complex data, which is s, t, u and v, respectively, one butterfly unit in the butterfly unit group performs butterfly operation on the 2-channel complex data u and v in a first clock cycle to obtain u and v after the butterfly operation, one butterfly unit in the butterfly unit group performs butterfly operation on the 2-channel complex data s and t in a second clock cycle to obtain s and t after the butterfly operation, u and v after the butterfly operation and s and t perform exchange by the exchange unit group to form recombined 2-channel complex data t and v and s and u, and the recombined 2-channel complex data t and v and s and u enter the butterfly operation group again for the butterfly operation in the first clock cycle and the second clock cycle, respectively. It should be noted that the above specific numerical values are only specific examples for facilitating the understanding of the solution of the present embodiment by those skilled in the art, and the above specific numerical values should not be construed as limiting the technical solution of the present embodiment.
In step S403, the multiplier group multiplies the N-channel complex data after the butterfly operation by the twiddle factor, and sends the result to the switch unit group. Referring to fig. 4, in the present embodiment, the number of complex multipliers in the multiplier group is determined by the value of N, and in the specific embodiment, when the input data is 4-way complex data, the multiplier group is composed of two complex multipliers. In this embodiment, the multiplier bank multiplies the first set of N-path complex data by the twiddle factor in a first clock cycle, and multiplies the second set of N-path complex data by the twiddle factor in a second clock cycle.
In step S404, the switch unit group converts the received data into 2N channel complex data. In this embodiment, the 2N-path complex data is an intermediate result or an operation result, specifically, when the count of the counter in the middle of the iteration control counter 5 does not reach the maximum value, the 2N-path complex data is an intermediate result, and when the count of the counter in the middle of the iteration control counter 5 reaches the maximum value, the 2N-path complex data is an operation result. Referring to fig. 4, in the embodiment, the switching unit group converts two sets of N-channel complex data in two cycles into an operation result or an intermediate result of a set of 2N-channel complex data, when the 2N-channel complex data is the intermediate result, the arithmetic unit 3 writes the intermediate result into the memory unit 2, and when the 2N-channel complex data is the operation result, the arithmetic unit 3 outputs the operation result.
In an alternative embodiment, referring to fig. 1, before executing step S400, the method further includes:
in step S600, the arithmetic unit receives a transform mode signal for characterizing the determined fourier transform mode. In this embodiment, the fourier transform method includes a fast fourier transform or an inverse fast fourier transform. In the present embodiment, the arithmetic unit 3 receives a transform mode signal for characterizing the determination of the fourier transform mode, and performs the fast fourier transform or inverse fast fourier transform determination on the input data according to the current operation scenario of the fourier transform, and in a specific embodiment, the mode selection signal for characterizing the data operation mode of the arithmetic unit 3 is received by an I/O device, but may be preset.
Step S700, determining whether the fourier transform method is inverse fast fourier transform. If the fourier transform method is inverse fast fourier transform, step S800 is performed, and if the fourier transform method is fast fourier transform, step S400 is directly performed.
And step S800, conjugate processing is carried out on the rotation factors, and real and virtual exchange processing is carried out on the intermediate result.
In an alternative embodiment, referring to fig. 1, before executing step S400, the method further includes:
in step S900, the arithmetic unit receives a transform mode signal for characterizing the determined fourier transform algorithm. In the present embodiment, the fourier transform algorithm includes a radix-2 algorithm and a radix-4 algorithm. In the present embodiment, when the input data is a power of 2 instead of a power of 4, the radix-2 algorithm is used as the fourier transform algorithm, and when the input data is both a power of 2 and a power of 4, the radix-4 algorithm is used as the fourier transform algorithm, improving the processing efficiency on the input data.
And S1000, judging whether the Fourier transform algorithm is a base-2 algorithm. If the Fourier transform algorithm is the radix-2 algorithm, step S1100 is performed. If the Fourier transform algorithm is the radix-4 algorithm, step S400 is directly performed.
In step S1100, a part of butterfly units in the butterfly unit group performs butterfly operations.
In an optional embodiment, the processing method of the fast fourier transform further includes: the iteration control counter unit 5 counts the butterfly operations in the operator unit 3, wherein: a butterfly calculator in the iteration control counter unit 5 counts butterfly operations in each section to obtain the value of a butterfly counter; the segment counter in the iteration control counter unit 5 calculates the number of segments of butterfly operation to obtain the value of the segment counter. In this embodiment, the butterfly calculator in the iteration control counter unit 5 sequentially counts each section of butterfly operations in the operator unit 3, when the count of the butterfly calculator reaches a maximum value, the section counter starts counting, and when the section counter counts to the maximum value, a fourier transform operation is completed, and both the section counter and the butterfly calculator are reset.
In an alternative embodiment, the twiddle factor generation unit 4 includes: the system comprises an index generation module, an address conversion module and a real-virtual exchange module; referring to fig. 6, a flowchart of the operation of the twiddle factor generating unit 4 is shown, and the step S200 is executed and includes:
in step S210, the twiddle factor generation unit stores the effective twiddle factors into the read only memory. In the present embodiment, the twiddle factor generation unit 4 includes two read only memories in which all the effective twiddle factors are stored, and in a specific embodiment, according to the twiddle factorPeriodicity and symmetry of the children, for three twiddle factors of the radix-4 algorithm
And
is composed of
Store "FFT Length/8" effective twiddle factors in a first ROM
And
the "FFT length/8" effective twiddle factors are stored in a second read only memory.
In step S220, the index generation module generates an index of the twiddle factor according to the count value of the iteration control counter unit. In the present embodiment, the index generation module generates the index of the twiddle factor according to the count value of the iteration control counter unit 5 using the following formula:
where k is the exponent of the twiddle factor of the radix-4 algorithm, k1And k2Is the exponent of the twiddle factor of the radix-2 algorithm, N is the length of the input data, J is the value of the butterfly counter, and I is the value of the segment counter. In this embodiment, when the input data is 4-channel complex data, there are three indices of the twiddle factor of the radix-4 algorithm, the indices are k, 2k and 3k respectively, 2k is twice k, 3k is three times k, and in a specific embodiment, 3k can also be obtained by 2k + k.
In step S230, the address conversion module converts the exponent of the twiddle factor of the radix-4 algorithm or the exponent of the twiddle factor of the radix-2 algorithm into a ROM address.
In step S240, the real-virtual switching module reads the effective twiddle factor from the rom according to the rom address and converts the effective twiddle factor into a twiddle factor. In this embodiment, according to the periodicity and symmetry of the twiddle factors, the real-virtual switching module performs real-virtual switching on the effective twiddle factors, and converts the effective twiddle factors into twiddle factors required for performing butterfly operations.
In an alternative embodiment, the memory address generation unit 1 generates memory addresses using a natural sequential address generation approach. In the present embodiment, the read address and the write address generated by the memory address generation unit 1 are generated in a natural number order, and thus the calculation order of the operators is top-down within the operation section of each operator unit 3.
The technical scheme provided by the embodiment of the invention has the following advantages: because the arithmetic unit 3 receives the mode selection signal for representing and determining the data operation mode of the arithmetic unit 3, the data operation mode comprises a time extraction mode or a frequency extraction mode, and then butterfly operation is performed, the configurable fast Fourier transform processing method can process data in different scenes of applying the time extraction mode or the frequency extraction mode, and the application flexibility of the processing method is improved.
In addition, the switching unit group in the arithmetic unit 3 converts the input data or the intermediate result of the 2N-path complex data into the N-path complex data, so that the arithmetic unit converts the 2N-path complex data calculated in one cycle into the N-path complex data calculated in one cycle, and the two cycles complete the calculation of the input data or the intermediate result of the 2N-path complex data, thereby reducing the number of multipliers in the butterfly operation and reducing the area of the processor when the processing method of fast fourier transform is used.
In addition, the operator unit 3 receives a transformation pattern signal for characterizing the fourier transform algorithm, so that the algorithm for performing the fourier transform by the operator unit 3 is determined to be the radix-2 algorithm or the radix-4 algorithm, instead of only the radix-2 algorithm or only the radix-4 algorithm for performing the butterfly operation, and thus, when the data length of the input data is a power of 4, the operator unit 3 receives the transformation pattern signal for characterizing the fourier transform algorithm, so that the algorithm for performing the fourier transform by the operator unit 3 is determined to be the radix-4 algorithm instead of continuously using the radix-2 algorithm, thereby improving the processing efficiency of the input data.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (8)
1. A processing method capable of configuring fast Fourier transform is characterized by comprising the following steps:
the arithmetic unit receives input data;
the twiddle factor generating unit generates twiddle factors required by butterfly operation and sends the twiddle factors to the arithmetic unit;
the arithmetic unit receives a mode selection signal for representing and determining a data operation mode of the arithmetic unit, wherein the data operation mode comprises a time extraction mode or a frequency extraction mode;
the arithmetic unit carries out butterfly operation on the input data under an operation mode corresponding to the mode selection signal according to the twiddle factor to obtain an operation result;
the arithmetic unit outputs the arithmetic result;
before the arithmetic unit performs a butterfly operation on the input data in an operation mode corresponding to the mode selection signal according to the twiddle factor to obtain an operation result, the arithmetic unit further includes:
the arithmetic unit receives an algorithm selection signal for characterizing and determining a Fourier transform algorithm, wherein the Fourier transform algorithm comprises a base-2 algorithm and a base-4 algorithm;
judging whether the Fourier transform algorithm is a base-2 algorithm;
and when the Fourier transform algorithm is the radix-2 algorithm, performing butterfly operation on a part of butterfly units in the butterfly unit group.
2. The processing method of configurable fast fourier transform of claim 1, further comprising:
the storage address generating unit generates a read address and a write address for representing an intermediate result stored in the memory unit, and sends the read address and the write address to the memory unit, wherein the intermediate result is an operation result in the process of butterfly operation of the input data by the arithmetic unit;
the arithmetic unit writes the intermediate result into the memory unit according to the write address;
the arithmetic unit reads the intermediate result mapped by the read address according to the read address.
3. The processing method of configurable fast fourier transform of claim 2, wherein the arithmetic unit comprises: the input data is 2N-channel complex data, where N is a positive integer, and when the data operation mode is a time extraction mode, the arithmetic unit performs a butterfly operation on the input data in an operation mode corresponding to the mode selection signal according to the twiddle factor to obtain an operation result, where the operation result includes:
the exchange unit group converts the input data or the intermediate result into N-channel complex data;
the multiplier group multiplies the N-channel complex data by the twiddle factor and then sends the multiplied data to the butterfly unit group;
the butterfly unit group performs butterfly operation on the received data to obtain N-channel complex data after the butterfly operation;
and the exchange unit group converts the N-channel complex data after the butterfly operation into 2N-channel complex data, wherein the 2N-channel complex data is the intermediate result or the operation result.
4. The processing method of configurable fast fourier transform of claim 2, wherein the arithmetic unit comprises: the input data is 2N-channel complex data, where N is a positive integer, and when the data operation mode is a frequency extraction mode, the arithmetic unit performs a butterfly operation on the input data in an operation mode corresponding to the mode selection signal according to the twiddle factor to obtain an operation result, where the operation result includes:
the exchange unit group converts the input data or the intermediate result into N-channel complex data and then sends the N-channel complex data to the butterfly unit group;
the butterfly unit group performs butterfly operation on the received data to obtain N-channel complex data after the butterfly operation;
the multiplier group multiplies the N-channel complex data after the butterfly operation by the twiddle factor and then sends the multiplied data to the exchange unit group;
and the exchange unit group converts the received data into 2N-channel complex data, wherein the 2N-channel complex data is the intermediate result or the operation result.
5. The method as claimed in any one of claims 2 to 4, further comprising, before said operator unit performs a butterfly operation on said input data in an operation mode corresponding to said mode selection signal according to said twiddle factor to obtain an operation result:
the arithmetic unit receives a transformation mode signal used for representing and determining a Fourier transformation mode, wherein the Fourier transformation mode comprises fast Fourier transformation and inverse fast Fourier transformation;
judging whether the Fourier transform mode is inverse fast Fourier transform or not;
and when the Fourier transform mode is inverse fast Fourier transform, performing conjugation processing on the twiddle factors and performing real-virtual exchange processing on the intermediate result.
6. The processing method of the configurable fast fourier transform as recited in any one of claims 1 to 4, further comprising:
an iteration control counter unit counts the butterfly operations in the operator unit, wherein:
a butterfly calculator in the iteration control counter unit counts butterfly operations in each section to obtain the value of a butterfly counter;
and calculating the number of sections of butterfly operation by using a section counter in the iteration control counter unit to obtain the value of the section counter.
7. The configurable fast fourier transform processing method of claim 2, wherein the memory address generating unit generates the memory address using a natural sequential address generation manner.
8. The configurable fast fourier transform processing method of claim 2, wherein the read address and the write address have a same physical address.
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| CN109117188B (en) * | 2018-08-06 | 2022-11-01 | 合肥工业大学 | Multi-path mixed-basis FFT (fast Fourier transform) reconfigurable butterfly operator |
| CN112163184B (en) * | 2020-09-02 | 2024-06-25 | 深聪半导体(江苏)有限公司 | Device and method for realizing FFT (fast Fourier transform) |
| CN112966209B (en) * | 2021-03-11 | 2023-05-05 | 北京理工大学 | FFT processor and method for processing data thereof |
| CN115882967A (en) * | 2022-12-01 | 2023-03-31 | 电子科技大学 | Frequency template trigger device based on MonoFFT |
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