WO2010010541A1 - Procédé de correction d’une gigue de synchronisation dans un can, et can - Google Patents

Procédé de correction d’une gigue de synchronisation dans un can, et can Download PDF

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Publication number
WO2010010541A1
WO2010010541A1 PCT/IB2009/053265 IB2009053265W WO2010010541A1 WO 2010010541 A1 WO2010010541 A1 WO 2010010541A1 IB 2009053265 W IB2009053265 W IB 2009053265W WO 2010010541 A1 WO2010010541 A1 WO 2010010541A1
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adc
sampling
signal
timing
sample
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PCT/IB2009/053265
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English (en)
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Doris Konstantinos
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Nxp B.V.
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Publication of WO2010010541A1 publication Critical patent/WO2010010541A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0836—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of phase error, e.g. jitter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • This invention relates to Analog to Digital Converters (ADCs), and more particularly to a method of correcting timing jitter in analog to digital converters. It further relates to ADCs operating according to such a method.
  • ADCs Analog to Digital Converters
  • Timing jitter or phase noise is a fundamental error mechanism in receiver and sampling systems.
  • phase noise forms a major performance obstacle.
  • jitter problems appear also in the sampling stage, that is, the ADC.
  • the combination of mixer and sampling noise due to jitter establishes limitations on the noise performance of the complete receiver.
  • timing jitter or phase noise in the clock signal is a major performance limiter in wideband SDR receivers.
  • Another field of application of relevance to the present invention is that of cable and terrestrial TV receivers for DOCSIS and DVB-C standards,
  • Satellite receivers basestation receivers for GSM/EDGE, UMTS, WiMAX, etc.
  • ADC based receiver architectures are used to digitize large portions of spectrum in one action.
  • digital oscilloscopes where jitter in the ADC is a main issue.
  • the range of application includes among other things, cable/terrestrial TV receivers and set-top boxes, base-station receivers for wireless communications, oscilloscopes, radar, etc.
  • phase noise problem is to make a cleaner clock signal by making a better PLL, or a better frequency synthesizer circuit.
  • This has significant consequences in power consumption, and in very low noise receivers requires the explicit use of resonator circuits with bulky LC tanks, adding in cost (due to silicon area), and allowing interference via electromagnetic coupling.
  • Signal sampling in the context of communications is periodic. That means, the signal is sampled every Ts seconds. In signal processing this way of sampling is usually called periodic sampling, or repetitive sampling.
  • Figure 1 shows the conventional periodic sampling method.
  • Figure 1 shows the variation in time (x-axis or abcissa), of the amplitude (y-axis or ordinate), of a signal 1.
  • Sampling is repeated every Ts sec in a periodic, or repetitive, fashion at moments 2.
  • the type of noise added reflects to the properties of the sequence of errors ⁇ , which in turn are directly related to the physical origin of noise (thermal noise, interference, etc.) and the circuit topology used to generate the clock signal.
  • the typical manifestations of noise in the sampled signal are: (1 ) a White noise spectral floor originating from thermal noise in clock handling circuits, like clock buffers; (2) discrete spectral tones around the wanted signal caused from unwanted periodic modulation of the clock signal period; (3) spectrally shaped noise that follows an 1/f relationship around the main signal tone, relating to White and 1/f noise generated in the circuit elements of a phase lock loop (PLL), or frequency synthesis, circuit.
  • PLL phase lock loop
  • FIG. 3 A conventional sampling architecture is illustrated in Figure 3.
  • An analog signal in is input to an ADC, to produce a digitised output signal out.
  • the ADC samples the input signal every Ts seconds, corresponding to the clock signal elk.
  • FIG. 4 An example of the effects of phase noise is given in Figure 4 using the sampling architecture of Figure 3.
  • a single frequency carrier signal 41 at 0.45 GHz is sampled, at 1 Gsamples/s with an ADC according to Figure without any correction for clock jitter.
  • Figure 4(a) shows a white noise floor 42 away from the carrier frequency
  • Figure 4(b) shows the 1/f noise behaviour 43 near to the carrier frequency.
  • noise around a carrier impacts neighbouring or far-away carriers and limits the achievable carrier to noise ratio per carrier. This translates directly to bit errors in the demodulation process.
  • a method of correcting timing jitter in a first ADC comprising sampling an input signal using the first ADC at a nominal clock time c(t,) of an ADC clock signal c(t) to provide a first sample, sampling the input signal at a moment separated from c(t ⁇ ) by a delay ⁇ t to provide a reference sample, determining the signal slope from the first sample, the reference sample and the delay ⁇ t, estimating a timing error ⁇ , of the ADC, and determining a corrected first sample from the timing error ⁇ , and the signal slope.
  • the reference sample is provided by a second ADC.
  • the invention is based on the realisation that a form of burst mode sampling may be applied to the problem of the present invention, to result in a method of correcting for timing jitter.
  • the delay ⁇ t may be positive.
  • the delay ⁇ t may be negative, such that the reference sample precedes the first sample.
  • the delay ⁇ t may be determined by means of a clock buffer.
  • the clock buffer is simply a wire link.
  • the step of estimating a timing error ⁇ , of the ADC comprises comparing a falling edge or a rising edge of the nominal clock time c(t,), with a respective rising edge or falling edge r(t,) of a reference clock signal r(t).
  • a global reference clock signal without a significant level of jitter, is frequently present an applications utilising a method according to the invention, and such a reference clock signal r(t) can provide a convenient reference against which to estimate the timing jitter.
  • the ADC clock signal c(t) may have a frequency which is higher than that of the reference clock signal r(t), and subsequent timing errors ⁇ l+n for nominal clock times c(t l+n ) intermediate the times r(t,) and r(t',) of consecutive rising edges or falling edges or reference clock are estimated to be the same as the timing error ⁇ ,.
  • the ADC clock signal c(t) may be an integer multiple of the reference clock signal r(t).
  • an accurate - but relatively slow - reference clock may be used to advantage.
  • a timing offset may be subtracted from the timing error ⁇ , prior to determining the corrected first sample, and beneficially, the timing offset is calculated from an average of the timing error ⁇ , over a plurality of cycles. Separating out such an offset, from the random timing jitter, allows the correction of just the jitter, and makes the correction easier, since the (possibly large) offset can be accounted for, with a consequential improvement of the Taylor expansion estimation of the amplitude error from the slope and the timing error.
  • the method further comprises sampling the input signal at the end of one or more further delays
  • the step of determining the signal slope from the first sample, the reference sample and the delay ⁇ t comprises calculating a polynomial best fit from the reference sample and the one or more further reference samples, and the delay ⁇ t and the one or more further delays ⁇ (t)n.
  • Calculation of a polynomial, rather than merely a linear calculation of the slope, provides for a more accurate calculation of the amplitude error, albeit at the expense of the requirement for additional ADCs to carry out the additional sampling.
  • the step of estimating the timing error ⁇ , of the ADC is effected by means of a time-to-digital converter circuit.
  • the step of estimating the timing error ⁇ , of the ADC is effected by means of a phase detector combined with a charge-pump, and a measurement ADC.
  • Such circuit provide particularly convenient methods of estimating the timing error.
  • a phase detector combined with a charge-pump, configured as a phase lock loop (PLL) is frequently already available in the ADC circuit, to provide the ADC clock signal, so this embodiment minimises the additional circuitry required to put the embodiment into effect.
  • PLL phase lock loop
  • the invention may be considered to be based on the realisation that it is possible to use a combination of burst sampling with uniform sampling to provide a plurality of samples (nominal sample plus redundant samples), around the nominal sampling moment. Using this redundancy and using also extra information about the actual timing errors extracted with timing error extraction means, the actual sampling error is calculated. This error will then be subtracted from the nominal sample, so that an error free sample is obtained.
  • a method according to the invention may result in a high performance improvement; this may potentially open the way, for example, to replacement of bulky LC tank based oscillators with highly integrated RC based ones.
  • the method may be of wide applicability, and be suitable for broadband and narrowband signals, independent of their jitter properties; yet further, no additional reference signal need be required than what already exists in a conventional receiver.
  • the method may be capable of having a highly integrated implementation, especially considering the recent developments and trends in integrated receivers using highly digitized frequency reference synthesis circuits.
  • an ADC which is adapted to operate according to a method as described above.
  • Fig. 1 illustrates a repetitive of periodic sampling schema
  • Fig. 2 shows the effects of timing errors on the amplitude of a sampled signal
  • Fig. 3 is a schematic of a conventional ADC
  • Fig. 4 shows the effect of 1/f noise and white noise on a single frequency signal sampled with an ADC not having jitter correction
  • Fig. 5 shows the architecture of an ADC configured according to an embodiment of the invention
  • Fig. 6 illustrates burst mode sampling
  • Fig. 7 shows the effect of jitter correction on white Gaussian jitter according to an embodiment of the invention
  • Fig. 8 shows the effect of jitter correction on 1/f sideband noise according to an embodiment of the invention
  • Fig. 9 shows an architecture of a digital phase lock loop arrangement
  • Fig.10 shows timing error, normalized to a sampling period, per sampling period
  • Fig. 11 shows the effect of jitter correction on 1/f sideband noise according to a second embodiment of the invention.
  • Fig. 12 and Fig 13 show the effect of jitter correction a multi-carrier signal according to a second embodiment of the invention.
  • FIG. 5 shows a first ADC 51 , to which an input signal x(t) is applied.
  • the input signal x(t) is also input to a second ADC 52.
  • the digitised outputs from both ADCs are input to a digital processor 53.
  • a timing error estimation circuit 54 receives an ADC clock signal c(t), and a reference clock signal r(t), and provides an output to the digital processor.
  • a delay circuit 55 takes as input the ADC clock signal c(t) and outputs a delayed signal c(t + ⁇ t).
  • the ADC clock signal c(t) controls the timing of the sampling of the first ADC
  • the delayed signal controls the timing of the ADC sampling of the second ADC. Note that it is equally possible for sampling of the second ADC 52 to lead, rather than lag, that of the first ADC 51 , by the delay ⁇ t.
  • the signal to be sampled is described as x(t), and c(t) represents the dirty clock signal, that is to say the clock signal including timing jitter.
  • this instantaneous error e(i) can be easily subtracted from the signal in the digital domain.
  • the instantaneous error e(i) can be extracted with the use of the sampling architecture and a timing error estimation circuit, according to this embodiment of the invention.
  • At least two ADCs are used to sample an input signal x(t), without any loss of generality.
  • the first ADC 51 can be called the primary or nominal ADC, and its output will be eventually corrected.
  • the second ADC 52 (or more in case more redundant ADC's are used, such as will be described in more detail below) serves as an auxiliary ADC to help calculate the slope of the signal.
  • the dirty ADC clock signal c(t) is fed to the primary ADC 51.
  • the ADC receives this clock from an on-chip phase lock loop (PLL), or from frequency synthesis means.
  • PLL phase lock loop
  • the latter receives a global clock reference r(t) and interfaces properly this sensitive external reference to the internal circuits that need a clock signal.
  • the global reference signal may be, for example, a signal provided by a crystal oscillator.
  • undesirable timing jitter (which may also be referred to as phase noise) is added to c(t).
  • this clock signal c(t) is used to generate a second clock signal c(t+ ⁇ t) delayed by a fixed amount ⁇ t, which can be a-phori known, or measured with on/off chip measurement methods and subsequently be stored as digital value in an internal memory.
  • a clock buffer or delay circuit 55 and in the simplest case just an interconnecting wire, can generate c(t+ ⁇ t) from c(t) with delay differences ranging from a couple of ps to iOOps.
  • the added timing jitter from the delay circuit can be made to be negligible compared to the actual error of the clock, such that the relative timing jitter between c(t) and c(t+ ⁇ t) is negligible.
  • the delay ⁇ t is made small on purpose compared to the signal and sampling period so that the slope will stay practically constant during the delay ⁇ t, therefore introducing no extra error.
  • the timing error estimation circuit 54 receives the reference clock signal r(t) and the ADC clock c(t) and extracts tinning errors ⁇ , that will be used in equation (1 ) to calculate the error present in the signal. In particular, it identifies the delay of the rising/falling edge of the signal c(t) compared to that of r(t) for each cycle i of r(t).
  • the timing error per cycle is passed to a digital processor 53.
  • the signal processor can perform additional calculations, corresponding to further embodiments of the invention. For example, if the average timing error includes a timing offset, this offset does not cause sampling errors because it stays constant in each cycle. For implementation efficiency, and according to one further embodiment of the invention, the average timing error is calculated from each cycle error. This average error then represents the offset. The offset is then subtracted from each cycle error. The correction will then be based on the cycle error without offset.
  • more than one auxiliary ADC is used, along with more delayed clock signals.
  • more accurate calculation of the signal slope can take place. Referring to Figure 6, this shows three samples, that is to say, one nominal sample 2a, followed to two auxiliary samples 2b and 2c, corresponding to each ADC cycle Ts. The plurality of samples could as well be basis of calculation of a linear or polynomial fit of the signal slope.
  • slope dx/dt of the signal Is changing fast near to the sampling moment, or the signal is near a turning point
  • use of a plurality of auxiliary ADCs can provide a more accurate estimation of the slope of the signal, and thus the amplitude correction to be applied to correct for jitter, than in the embodiment described above, where only one reference ADC, which limits the correction to a linear slope.
  • slope is used in its broad sense synonymously with gradient, and is thus not to be taken as being limited to a straight line or linear slope.
  • the noise floor 72 results in a signal-to-noise ratio (SNR) of 30 dB: the total signal power is -15dB of signal power all concentrated at 0.49GHz, and the total jitter noise power is integrated in the 0.5GHz signal band is around -45dB, the -85dB noise floor in figure 7 corresponding to the noise power per frequency bin used in the FFT analysis.
  • the SNR is significantly improved to the level of 5OdB; this is an order of magnitude improvement
  • the improvement in terms of total SNR, between the uncorrected signal 82 and the corrected signal 83 is very large: from 26dB originally to 5OdB after correction, i.e. 24dB.
  • the timing error estimation circuit 54 can be realised in several ways, for example with Time-to-Digital Converters.
  • Time to digital converters are well known; an example is described by M. Lee and A. A. Abidi, in "A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue", 2007 Symposium on VLSI Circuits, Digest of Technical Papers, the whole contents of which are incorporated herein by reference.
  • CMOS 90nm for example, in the above paper, a 9b 1.25ps resolution time-to- digital converter is reported in CMOS 90nm, making possible to identify timing intervals between a reference signal and another (both at 10MHz) with 1.25psec step.
  • the timing error estimation circuit 54 may be realised with Phase-Detectors combined with charge-pump circuits followed by measurements ADC's; such circuits are also well-known, and an example is described by M. Takamiya, et.al. in "On-Chip Jitter-Spectrum-Analyzer for High-Speed Digital Designs", IEEE Solid State Circuits Conference, ISSCC 2004, the whole contents of which are also incorporated herein by reference. In this paper the second method is applied to identify timing errors with approximately I Opsec resolution at 1 GHz clock.
  • timing measurement devices such as time-to- digital converters have brought a major change in the way modern Phase- Lock-Loops (PLL) and Delay-Locked-Loops are designed, allowing the replacement of conventional analog loop filters with digital ones, as has been described, for example by R. B. Staszewski, et.al. in "All-digital PLL and GSM/EDGE transmitter in 90-nm CMOS," IEEE Solid State Circuits Conference, 2005 the whole contents of which are incorporated herein by reference. There, the phase detector and charge-pump circuits that compare the (external) crystal oscillator reference with one generated by the PLL are replaced. A digital filter replaces the analog loop filter as well.
  • Figure 9 depicts a time-to-digital converter 91 , which has as an input global reference clock r(t), and as output error estimation ⁇ (i).
  • the error estimation is fed into a digital loop filter 92, the output from which is input into a digitally controlled voltage controlled oscillator (VCO) 93.
  • VCO voltage controlled oscillator
  • the VCO outputs c(t) corresponds to the ADC clock signal.
  • This signal is fed into the time-to- digital converter along with the global reference clock signal r(t), in order to close the feedback loop.
  • timing extraction circuit necessary for the error extraction shown in figure 5 can actually be the same circuit that is used in a modern Digital PLL.
  • a PLL is typically integrated together with the ADC to generate the ADC clock signal c(t).
  • this circuit is a time-to-digital converter, which compares the delay between the low frequency signal reference (e.g. 26MHz) with the generated (dirty) high frequency signal c(t) (e.g. 2 GHz).
  • ADC clock signal c(t) is not matched to that of the global reference clock signal r(t), will now described.
  • Global reference clock signals are typically provided from crystal oscillators. Conventionally, due to the low frequency at which crystal oscillators can oscillate (in the order of 1 -10 MHz) there is a significant difference between the high frequency of the clock signal c(t) generated at the output of the PLL and the clean input signal r(t) provided by this crystal oscillator.
  • PLL compares only a fraction fr/fc of rising (falling) edges of the signal c(t) to that of r(f), fc and fr being the frequencies of the signals c(t) and r(t), respectively. Consequently, it adjusts the frequency of the high frequency clock such that the two rising (falling) edges have almost zero difference.
  • fr edges of the ADC clock c(t) are measured instead of fc, consequently, only fr out of fc tinning errors per cycle can be measured.
  • FIG 10 demonstrates a main underlying concept where the actual timing error per cycle is plotted.
  • the dashed curve 101 shows the timing error per each of the shown 7000 cycles.
  • the random walk characteristic of this error is representative of timing jitter with 1/f characteristics.
  • a white noise part is superimposed on it, but is relatively small.
  • the solid line 102 shows the timing error sampled once every 10 cycles and quantized with a resolution of 6bits. This is representative of the timing error result delivered form the time- to-digital converter of a Digital PLL, which compares an input frequency 10 times lower than its output. In this case, once an error is measured, all following 10 cycles will be corrected with the same amount.
  • figure 12 and 13 is plotted a multi-carrier signal 121 contaminated with jitter.
  • the frequency ratio between the global reference clock, and the ADC is 10.
  • the response without correction is shown (in figure 12) at 122; that with the correction is shown in figure 13 at 133.
  • the present invention is not restricted to any one specific design of ADC.
  • the ADC may be a time-interleaved ADC, or a non-time-interleaved ADC.
  • the ADC may be a single ADC unit of a time-interleaved ADC, and first and second ADCs may refer to first and second ADC units in a time-interleaved ADC having multiple unit ADCs.
  • a method of correcting an ADC for timing jitter is disclosed. From one aspect, the method is based on a novel sampling architecture that applies burst sampling and digital signal processing to eliminate the impact of timing jitter.
  • burst sampling with uniform sampling provides a plurality of samples (nominal sample plus redundant samples), around the nominal sampling moment. Using this redundancy to determine the signal slope near the sampling moment, and using also extra information about the actual timing errors extracted with timing error extraction means, the actual sampling error will be calculated. This error will then be subtracted from the nominal sample, so that an error free sample is obtained.
  • An ADC with timing jitter correction operating according to the above method, is also disclosed. From reading the present disclosure, it will be appreciated that embodiments may be applicable in any highly digitized radio receiver and in more generally in Software Radio receivers. In particular, its use may provide significant benefit in Digital Cable TV receivers and set-top boxes, PC-TV applications and cable modems.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

La présente invention concerne un procédé de correction d’une gigue de synchronisation dans un CAN (convertisseur analogique-numérique). Dans un aspect, le procédé se fonde sur une nouvelle architecture d’échantillonnage qui applique un échantillonnage de salve et un traitement de signaux numériques pour éliminer l’impact de la gigue de synchronisation. La combinaison de l’échantillonnage de salve avec l’échantillonnage uniforme offre une pluralité d’échantillons (échantillon nominal plus échantillons redondants), autour du moment d’échantillonnage nominal. L’erreur d’échantillonnage réelle sera calculée à l’aide de cette redondance pour déterminer la pente du signal près du moment d’échantillonnage, et à l’aide également d’informations supplémentaires sur les erreurs de synchronisation réelles extraites avec des moyens d’extraction d’erreurs de synchronisation. Cette erreur sera alors soustraite de l’échantillon nominal de sorte qu’un échantillon exempt d’erreur soit obtenu. L’invention concerne également un CAN doté d’une correction de gigue de synchronisation fonctionnant selon le procédé ci-dessus.
PCT/IB2009/053265 2008-07-25 2009-07-27 Procédé de correction d’une gigue de synchronisation dans un can, et can WO2010010541A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011003736B4 (de) 2011-02-08 2022-08-11 Robert Bosch Gmbh Messsignal-Korrekturvorrichtung und Verfahren zur Korrektur eines Messsignals
US11650285B2 (en) * 2015-08-13 2023-05-16 Texas Instruments Incorporated Chirp frequency non-linearity mitigation in radar systems

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