WO2010002875A1

WO2010002875A1 - Neutron detection semiconductor device and method for manufacture

Info

Publication number: WO2010002875A1
Application number: PCT/US2009/049232
Authority: WO
Inventors: David V. Jr. Kerns; Sherra E. Kerns; Matthew J. Schor
Original assignee: Kerns David V Jr; Kerns Sherra E; Schor Matthew J
Priority date: 2008-06-30
Filing date: 2009-06-30
Publication date: 2010-01-07

Abstract

A semiconductor device for detection of neutron particles includes a detector layer (110) and an array (50) of multiple detector cells. Each detector cell (100) is switchable between first and second electrical states. Sensitive nodes (105) corresponding to each detector cell (100) cause the cells to switch electrical states in response to penetration of an alpha particle into the sensitive node. Read/write circuitry coupled to each of the detector cells (100) communicates the electrical states of each of the detector cells external to the device. A cavity (125) is etched in a cavity layer (120) over the sensitive nodes (105). A conversion layer (135) is deposited in the cavity (125) to emit alpha particles toward the sensitive zone in response to capture of neutron particles. The device may be manufactured in a conventional CMOS wafer foundry, including etching of the cavity, using conventional front side wafer processing techniques.

Description

DESCRIPTION

NEUTRON DETECTION SEMICONDUCTOR DEVICE AND METHOD

FOR MANUFACTURE TECHNICAL FIELD

[0001] The present invention pertains to neutron detection devices and methods of manufacturing such devices. More particularly, this invention is directed toward semiconductor devices and associated fabrication methods that provide for the detection of neutrons with an adjustable threshold of sensitivity and a modularity that allows multiple devices to be used in tandem for increased sensitivity.

BACKGROUND ART

[0002] The proliferation of nuclear weapons and weapons materials has caused significant concern about their unlawful transport and distribution. There is a strong need for neutron detection technology that can be produced inexpensively, occupies a small volume, and is capable of operating for long periods of time at extremely low power. Potential applications for such a detector include neutron surveillance at ports and border facilities, monitoring shipping containers on the vessels and/or trucks, on rail transport systems, widespread monitoring by placing such sensors in cell phones or PDAs, and at any other locations where radiological material (such as that used in "dirty bombs") may be potentially present.

[0003] One approach in which neutron detectors have conventionally been fabricated uses the phenomenon of scintillation. This detection mechanism operates by an energetic charged nuclei or incident neutron interacting with material in the detector, producing photon-emitting reactions. Typically scintillation devices designed for neutron detection generate light upon receipt of incident neutrons within a neutron sensitive gas or liquid. The packaging of this device involves a container that is larger than a typical silicon chip and is subject to failure through breakage.

[0004] Neutrons may also be detected in a gas filled detection device, typically a tube containing helium-3 at high pressure. These detectors contain electrodes operated at relatively high voltage and require significant operating power, are delicate to handle and often produce false detection outputs under mechanical stress.

[0005] Solid-state electronic detection devices have many advantages.

Semiconductor detectors have been produced in which a conversion material layer (often boron— 10) is placed in close proximity to a silicon-based semiconductor diode. As shown in Fig. 1, an incoming neutron reacts in the conversion layer to produce an alpha particle, which is subsequently detected by the diode junction. Large area PIN diodes with boron— 10 or lithium as conversion layers have been utilized. Such devices have numerous deficiencies. These deficiencies include relatively high noise levels without special cooling, relatively large leakage currents, requirement for analog signal processing consuming continuous power, and sensitivity to gamma rays. [0006] Recent developments have included the utilization of various semiconductor memory cells in conjunction with a conversion layer to realize a neutron detection device. There exists prior art disclosing circuit designs and semiconductor device structures tailored to create devices that are less sensitive to, or more hardened to, incident radiation, enhancing their ability to process information without errors. However for the present applications, novel circuit design and device structure must be utilized to fabricate devices with detector cells in which the data stored may be more sensitive and susceptible to change of electrical state due to incident radiation. The change in memory state within a memory cell induced by incident ionizing radiation is called a soft error or a single event upset. Several attempts have been proposed to utilize a memory array in proximity to a conversion layer, which converts the incoming neutron to an alpha particle, the alpha particle then causing a single event upset in the memory array. The entire device thereby functions as a neutron detector. [0007] Hassain et al (US Patent No. 6,075,261) produced arrays of flash memory cells in which a borophosphosilicate glass containing a high percentage of boron— 10 was deposited on the semiconductor memory device. As noted in the August et al (US Patent No. 7,271,389), "These efforts to date have resulted in insensitive detectors primarily because the boron conversion material that is not located close enough to the active semiconductor layer." Thus alpha particles generated by the boron conversion material dissipate their energy prior to reaching the active semiconductor layer, or so-called sensitive node. In addition, such glass does not have the conversion efficiency of boron- 10. [0008] There have been several attempts to place the boron-10 conversion layer close to the active semiconductor node (sensitive node) by utilizing MEMS (microelectromechanical systems) processing on the backside of the silicon wafer. Typically this involves fabricating the memory array on a SOI (silicon on insulator) substrate and then using substantial additional processing to etch cavities in the backside of the wafer, and deposit and seal the boron or other conversion layer in said cavities. This approach is described in the August '389 patent and in the Hughes patent (U.S. Patent No. 6,867,444). The structures shown in Fig. 4 are representative of prior art neutron detector structures formed using conventional backside bulk CMOS or SOI fabrication methods. [0009] The use of backside processing introduces substantial processing complexity and corresponding increased cost. Wafers prepared for backside processing much be polished on both sides, there is generally a requirement for backside alignment to front side features, additional mechanical stress, support and reliability issues, and many other disadvantages. Further the Hughes patent discusses etching trenches lateral to the sensitive node and depositing conversion material therein. This also introduces complexity in processing, has limited cross-section for neutrons, and the proximity of the conversion material to the active node is determined by photo processing of materials not standard in foundry CMOS processes. The backside and trench processing often on SOI wafers typically involves substantial wafer grinding and deep etching after circuit fabrication on the front side, thus reducing overall process yield and increasing device cost.

[0010] Therefore, what is needed is a semiconductor device comprising a memory array which quiescently draws very little power, each memory cell capable of having its memory state altered by an alpha particle from a proximal conversion layer, the sensitivity of such cells is electronically controllable, and the electronic device fabrication is compatible with standard CMOS foundry fabrication processes, resulting in low cost base wafers.

[0011] What is also needed is a manufacturing process in which wafers completed by the foundry may be subsequently processed to add the boron-10 or other conversion layer at a separate facility. Such a modular manufacturing method may utilize the low cost derived from volume foundry production of CMOS chips, coupled with the specialty deposition processing required for the conversion layer.

DISCLOSURE OF THE INVENTION

[0012] The present invention provides a semiconductor-based neutron detector device compatible with fabrication at modern CMOS foundry facilities and utilizing standard foundry processes. Within the detector device and chip is contained an array of memory-type detector elements or cells, each having structure and circuitry designed so that its memory state can be switched by an incident alpha particle of predetermined energy. Further each detector element may have its sensitivity to such upset controlled by either inherent design parameters or an external programming variable, such as a voltage, supply voltage, or other input.

[0013] Within each detector cell is at least one sensitive node, a circuit node at which charge injected or removed causes the data stored in the cell to change states. One aspect of the invention includes physically enhancing the sensitive node, such by increasing the cross- section of a CMOS transistor drain, for capturing alpha particles, and thereby the efficiency of the detector, in a manner consistent with post-processing of the critical conversion layer from the front- side of the wafer.

[0014] In one embodiment, the detector cell is fabricated using conventional CMOS technology, and therefore gains the benefit of cost-effective wafer foundry production capability. The conversion layer, which converts incoming neutrons to alpha particles, is deposited after wafer fabrication, and therefore separating the steps of wafer fabrication from conversion layer deposition, a key element for cost-effective production.

[0015] Thus, according to one aspect of the invention, a semiconductor device for detection of neutron particles has a detector layer comprising an array of multiple CMOS memory cells, each resembling a static RAM cell circuit, each cell being switchable between first and second electrical states. A physically enhanced drain in the cell provides a sensitive node that is functional to cause the cell to switch electrical states in response to the presence of an alpha particle intersecting the sensitive node. The device further includes read/write circuitry coupled to each of the detector cells and functional to set (write) and communicate the electrical states of each of the detector cells external to the device (read). A cavity layer includes a cavity disposed over a majority of and proximate to the sensitive node. At least a portion of the cavity layer includes a conversion layer, such as boron- 10, deposited in the cavity to emit alpha particles toward the detector layer in response to entry of a neutron particle into the conversion layer.

[0016] In one embodiment of the device, each of the detector cells includes multiple CMOS transistors arranged to form cross-coupled inverters. At least one CMOS transistor drain is physically enhanced with respect to the source to define the sensitive node for that detector cell.

[0017] In accordance with another aspect of the invention, the cavity may be positioned in the cavity layer substantially away from other functional structures in the cavity layer so that the cavity bottom surface is optimally positioned near the top surface of the drain, and does not intersect other circuit elements.

[0018] In yet another aspect, the device includes an array power circuit functional to supply an inverter operating voltage to the array of detector cells, and a device power circuit functional to provide device operating power to the other circuitry in the device excluding the array. The array power circuit is functional to operate in cell writing/reading and cell detection modes, the detection mode characterized by providing a reduced inverter operating voltage to the first and second inverters in each cell thereby increasing the sensitivity of the detector cells during particle detection, and the cell writing/reading mode characterized by providing an increased inverter operating voltage to the first and second inverters to inhibit accidental changes to the electrical states of the cells during writing (setting the initial state) or reading of the cells. [0019] Further, the array power circuit may have a first inverter power circuit functional to provide a first inverter operating voltage to the first inverter in each cell and a second inverter power circuit functional to provide a second inverter operating voltage to the second inverter in each cell. In this embodiment, the detector power circuit may selectively adjust the first inverter operating voltage separately from the second inverter operating voltage. [0020] Another embodiment of the invention includes a method of manufacturing a semiconductor device for neutron detection. The method may include fabricating an array of CMOS memory cells (similar to static memory cells) in a detection layer, each memory cell having at least one sensitive node formed therein, the sensitive node having a sensing volume for collection of deposited charge. A cavity layer is fabricated over the detection layer. Cavities are etched in the cavity layer over at least one of the sensitive nodes in the memory cells, each of the cavities having a bottom surface at or near the top surface of the corresponding sensitive node. An insulating layer may be deposited against the bottom surface of the cavities. A layer of a conversion or neutron capture material is deposited in the cavities.

[0021] In yet another aspect, the invention includes a method of operating a neutron detector device that has a conversion layer and an array of CMOS memory cells operative to change memory states in response to alpha particles emitted by the conversion layer. The CMOS memory cells include first and second cross-coupled inverters. In one embodiment of the method, the neutron detector is operated in a detecting mode and in a writing or reading mode. An array operating voltage is supplied to the memory cells, including providing a separate inverter supply voltage to the memory cells such that that the inverter supply voltage can be different from a device operating voltage supplied to other device circuitry. During the writing of the initial state and the detecting mode, the inverter supply voltage is reduced compared to the device detector operating voltage to enhance the alpha particle sensitivity of the memory cell. [0022] The device operating method may include, at the completion of the detecting mode, increasing the inverter supply voltage to inhibit accidental changes in the memory state of the memory cells prior to reading of data in the cells during the reading mode.

[0023] The operating method may also include providing different inverter supply voltages to first and second cross-coupled inverters in the memory cell so that the memory cell is more sensitive to being switched into one of the memory states. [0024] The net result is a neutron detection semiconductor device that can be produced at low cost, at reasonable efficiency and is modular in structure so multiple chips can be stacked together to detector modules with higher efficiencies, is insensitive to gamma radiation, and suited for a wide range of applications. Another aspect of the invention is the separation of the standard CMOS fabrication from the unique cavity etch and conversion layer deposition which is performed from the front-side of the wafer. Further the detector devices and modules of this invention may be integrated with simple data writing, recording and counting circuitry to create a cost-effective neutron detection and characterization system. Such systems may also be interfaced with satellite or other communication systems to establish broad networks of neutron detection capability, including mapping of neutron flux over wide areas, identifying and quantifying anomalies and assessing potential threat level. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Fig. 1 is a schematic diagram representative of a conversion layer of neutron capture material (e.g., boron- 10) emitting an alpha particle in response to capture of a neutron particle.

[0026] Fig. 2 is a graph showing the change in energy of a 1.47 MeV alpha particle as a function of depth into a silicon target (detector). [0027] Fig. 3 is a schematic diagram of one embodiment of a CMOS memory cell that can be used in the present invention.

[0028] Fig. 4 is a cutaway side view of prior art neutron detector structures formed using conventional backside bulk CMOS or SOI fabrication methods. [0029] Fig. 5 is a cutaway side view of one embodiment of a neutron detector structure formed using a CMOS fabrication process followed by front- side post-processing method in accordance with the present invention. [0030] Fig. 6 is a plan view of an array of detector cells arranged on a substrate to provide a neutron detector device in accordance with the present invention in which multiple sensitive nodes from multiple cells reside under a single conversion layer cavity.

BEST MODE FOR CARRYING OUT THE INVENTION

[0031] The present invention addresses and solves critical problems associated with the design, manufacture, and use of solid-state neutron detector devices. One of these problems is providing a device that provides consistently reliable sensitivity to neutron particles while being insensitive to gamma radiation. A second problem is cost-effective manufacturing. [0032] The concepts of ionization loss or "stopping power" dE/dx (measured in electron hole pair/particle track length) and range can be used to summarize the interaction of charged particles in semiconductor detectors. The specific ionization loss measures the amount of energy lost by the particle per unit- length of its track. The range indicates how deeply the particle penetrates the absorbing material. These concepts are illustrated for a 1.47 MeV alpha particle in Fig. 2 which graphically represents dE/dx of the alpha particle as it penetrates into a silicon target. From this we know that for optimal sensitivity, the conversion layer in a semiconductor neutron detector device must be closely proximate to the detector layer so that the alpha particles emitted from the conversion layer retain sufficient energy to cause a change in the electrical state of the detector cell.

[0033] In one embodiment of the present invention, the detector cell can include CMOS memory cell circuitry, such as the detector cell circuit 10 schematically shown in Fig. 3. Four CMOS transistors Ml, M2, M3 and M4 are arranged to form a pair of conventional cross-coupled CMOS inverters. More specifically, a first CMOS inverter 15 includes a p-channel transistor M3 with its drain coupled to the drain of an n-channel transistor Ml. The second CMOS inverter 20 has a p-channel transistor M4 with its drain coupled to the drain of an n-channel transistor M2.

[0034] The operation of a six transistor CMOS memory cell circuit 10 as shown in Fig. 3 is generally known in the art. For example, it is understood that the cell circuit 10 can be switched between first and second electrical states, sometimes referred to as data states, memory states, or "1" and "0" states. Thus, the detector cell circuit 10 further includes conventional read/write circuitry to read and/or write data, to determine the cell state. Access to the cell is enabled by the word line WL which controls the two cell access transistors M5 and M6. The access transistors M5 and M6 control whether the cell should be connected to the bit lines BL and BL_. The bit lines BL and BL_ are used to transfer data external to the cell for both read and write operations. During cell reading, the bit lines BL and BL_ are actively driven high and low by the inverters 15 and 20. Capacitances Cl and C2 are included to model or represent the bit-line capacitance and are not an integral part of the cell circuit.

[0035] It is also known that penetration of alpha particles into the drain of one of the inverter transistors can cause a change in the electrical state of the cell circuit 10. When this detector cell drain is positioned to receive alpha particles emitted from a neutron capture material or conversion layer, the drain is sometimes referred to as a sensitive node. For example, the drain associated with the CMOS transistor Ml can function as the sensitive node in the detector cell circuit 10 when the cell is set with the drain of transistor Ml at a high voltage level. The action of an ion hit will be to reduce this voltage. [0036] In a CMOS cell circuit as shown, there are two drains that are sensitive to being hit with an ion, and as a result of the charge deposited (electron-hole pairs created) by the ion, changing the logic state of the cell. The two sensitive nodes are the drains of the "off transistors. In one embodiment, n- channel transistor Ml is "off which requires that the voltage at the drain of transistor Ml, the sensitive node, be high. In the embodiment of Fig. 3, this would mean that p-channel transistor M3 is "on" and the voltage at the sensitive node is essentially the same as the supply voltage Va dj. The action of an ion striking the drain of transistor Ml is to cause positive charge to be removed from that node (node Q), reducing the voltage from its high state to a lower value. If sufficient charge is removed, the cell flips states, and transistor Ml turns "on" and the voltage at node Q is latched in a low state. Similarly, the drain of transistor M4 also can also be a sensitive node with the cell biased as above, as an ion hit to this node would increase its voltage from its initial low state and also act to change the cell's state.

[0037] A diode 25 may connected across the drain and source of the transistor Ml to enhance the performance of the sensitive node. In this embodiment, the drain node of transistor Ml (labeled Q) is the sensitive node, assuming this node is initially set at the "high" voltage level. Such a diode is generally fabricated from the same implant or diffusion forming the drain, and connected in parallel, so that an ion hit to the diode or the drain will cause the voltage of the node to be altered and flip the state of the cell. [0038] In another embodiment which increases the resistance of transistor M3, the transistor can be replaced by a resistor of high value, typically of more than 5OK ohms. There is little degradation in the total supply current, because node Q is nominally "high", and the voltage across the resistor is therefore zero. Only cells that are flipped to the opposite state encounter increased supply current drain. However, since these are normally small in number, and the resistance value is high, the effect is negligible. In applications where quiescent supply current is not an issue, both transistors M3 and M4 could be replaced by high value resistors.

[0039] In another embodiment, the highest possible resistance could be created by removing transistor M3 entirely, and provide an open circuit. Such a configuration would require the stored charge at Q to hold the voltage on Q high, similar to a dynamic memory cell. This would make it quite sensitive to an ion strike. Such a configuration could employ periodic read and refresh cycles to assure data integrity.

[0040] In another embodiment configured to increase the cell sensitivity to an ion hit, the W/L ratio, the width-to-length ratio of p-channel transistor M3 connected to the sensitive node, is modified. When the cell is set in the sensing mode, and if the drain of transistor Ml (node Q) is the sensitive node caused by setting this node high, then the voltage on Q is held high by the "on" p-channel transistor, M3. The "on resistance" of transistor M3 affects its effectiveness in holding that voltage high. To create a detector cell that is more sensitive to upset, the "on resistance" of transistor M3 can be increased by reducing the W/L ratio. If this resistance is increased, the supply voltage is more isolated from node Q, and the node Q voltage is more easily reduced. In one embodiment, the W/L ratio is reduced by increasing the length L by at least 150% compared to nominal or to W.

[0041] Because there can be two sensitive nodes in each cell for each of the two logic states, a further variation of the embodiment described above is to also increase the area of the drain of transistor M4, the "off p-channel transistor. It is understood that if transistor M4 is hit by an ion, the cell can be made more sensitive by increasing the on resistance of transistor M2, by replacing it with a high value resistor, or increasing its W/L ratio, analogous to the embodiment just described. [0042] Yet another alternate embodiment would include writing a logic state to the cell opposite to that described above in the cell for the sensing mode. That is, in Fig. 3 set node Q to a low level and node Q_ at a high level. For this embodiment, the sensitive nodes would then be the drains of transistors M2 and M3. By analogy to that previously described, to enhance the detection efficiency, the drain of either transistor M2 or M3 (or both) could be enhanced such as by increasing the area of drain. Likewise, the on resistance of the other transistor in each of the inverters, associated with the enhanced drain of transistor M4 and/or Ml respectively, could be modified to have their effective "on" resistance increased, either by replacement with a high value resistor, or increasing the W/L ratio of the transistor.

[0043] Fig. 5 illustrates one embodiment of a detector cell structure 100 in which a CMOS transistor corresponding to transistor Ml in Fig. 5 is optimized for use in a neutron detector device. The transistor gate and source are conventionally fabricated and arranged on a substrate. The drain or sensitive node 105 is physically enhanced within detector layer 110 to have a larger surface area as compared to the nominal surface area of the source. When the circuit is placed in a neutron flux, this increases the probability of an alpha particle hit in the sensitive node, and therefore, the detector cell circuit 10 having its data state switched; the efficiency of the detector is thereby increased. The detector structure 100 further includes a cavity layer 120 disposed over the detector layer 110. In accordance with one novel aspect of the invention, a cavity 125 is etched into cavity layer 120 so that the bottom surface 130 of the cavity 125 is closely proximate the top surface of the sensitive node 105. A conversion layer 135 is deposited in the cavity 125. Typically, the cavity layer 120 will be fabricated as an insulating layer, including depositing a thin layer of insulating material that separates the bottom surface of the cavity 125 from the sensitive node 105. In the embodiment shown in Fig. 5, the cavity layer 120 is also the device top layer. In other embodiments, this may not be the case. A layer of titanium or similar material can be placed under the conversion layer in some embodiments to provide a diffusion barrier to boron and enhance adhesion of the next layer. [0044] Although not shown in the drawing, the cavity layer 120 may also incorporate structures that interconnect circuit components in the detector layer 110. However, these structures are arranged such that they do not interfere with etching of the cavity 125 down toward the sensitive node 105. [0045] The conversion layer 135 can be a layer of a boron isotope material such as boron- 10, a layer of lithium, or layers of both. In one embodiment, the conversion layer 135 uses boron- 10 and the sensitive node 105 will cause the electrical state of the detector cell circuit 10 to change if the sensitive node is penetrated by an alpha particle having an energy of at least 1.46 MeV. In another embodiment, the conversion layer 135 includes lithium and the sensitive node 120 will cause the detector cell circuit 10 to switch states if penetrated by a lithium ion of at least 840 KeV.

[0046] As shown in Figs. 5 and 6, preferably the cavity 125 is positioned in the cavity layer 120 substantially away from other functional structures in the cavity layer 120 (such as other device structures or conducting paths) so that the cavity bottom surface 130 and conversion layer 135 are optimally positioned near the top surface of the sensitive node 105. Stated another way, the circuit interconnect structures and the like are arranged in the device so that the cavity 125 can be effectively etched proximate the sensitive nodes 105 without interference from other circuit structures.

[0047] For example, in one embodiment the conversion layer 135 of boron-

10 is between 1 and 4 microns thick, and more preferably between 2 and 4 microns thick, and is separated from the top surface of the sensitive node 105 by less than 2 microns, and preferably by less than 1 micron. A thin layer (less than 2 microns thick) of insulating material may be deposited in the bottom of the cavity, before the conversion layer is deposited.

[0048] In fabricating a practical neutron detecting device, there will preferably be an array of multiple detector cells forming a device detector layer, each detector cell having a cell circuit such as that shown in Fig. 3 and at least one CMOS detector structure similar to that shown in Fig. 5. One embodiment of an array of detector cells is shown in Fig. 6. In this embodiment of an array 50, four CMOS transistors are shown on a single substrate, each with a source 55, a gate 60, and an enlarged drain or sensitive node 105. A single cavity 125 is positioned over multiple sensitive nodes. The cavity 125 contains the conversion layer 135. Thus it can be seen that no other device elements or wiring are physically present between the conversion layer and the sensitive nodes enabling the etch of a cavity proximate to the sensitive node and thereby providing optimal sensitivity for detection of neutron particles. The data states of each of the detector cells in the array 50 can be read from the device to determine a level of detection of neutrons by the device.

[0049] Referring again to Fig. 3, additional device enhancements can improve the sensitivity of the detector cells. In particular, the device can include an array power circuit functional to supply an inverter operating voltage VDD to the array of detector cells. In one embodiment, the array power circuit can operate separately from a device power circuit that provides operating power to the other device circuitry excluding the array. Further, the array power circuit is functional to operate in a cell writing and reading mode, and in a cell detection mode. In the cell detection mode, the inverter operating voltage VDD to the first and second inverters is reduced, thereby increasing the sensitivity of the detector cells during particle detection. In the cell writing or reading mode the inverter operating voltage is increased to the first and second inverters to inhibit accidental changes to the electrical states of the cells during reading of the cells. [0050] In yet another embodiment of the detector cell circuit, the array power circuit provides a first inverter operating voltage Vadj to the first inverter 15 and a second inverter operating voltage VDD to the second inverter. The first inverter operating voltage can be selectively adjusted separately from the second inverter operating voltage VDD. A differential in inverter operating voltages between the first inverter 15 and second inverter 20 can render the detector circuit 10 more sensitive to being switched into one of its memory states. This can enhance the detection sensitivity of the device.

[0051] The voltages on the source of transistors M3 and M4 (Vadj and

VDD=I.8 respectively) are only examples of possible voltages. These are the supply voltages for each side of the memory cell. As described, in certain embodiments these can be separate voltages as shown in Fig. 3. (VDD is not limited to 1.8 as shown). These voltages can also be the same, and both adjusted, generally lowered, together, to enhance the sensitivity of the cell in detecting an alpha particle. [0052] A semiconductor device for neutron detection as described above, in combination with conventional write circuitry, writes a known bit pattern into the detector array or any portion thereof, such pattern designed to place the enhanced node or nodes in its sensitive state. Subsequently, read circuitry reads the bit pattern from the array or portion thereof, and provides data whereby a comparison of the two bit patterns is made. The number or percentage of changed bit elements may be computed, thereby enabling computation of the neutron field over the time between said writing and reading of the bit pattern. [0053] Another aspect of this invention includes a novel and low cost method of manufacturing a semiconductor neutron detection device. The essence of cost-effective volume CMOS integrated circuit fabrication is planar processing on the front side of the wafer. In order to achieve a cost-effective product, one or more fabrication objectives should be achieved. First, substantially all processing for device fabrication should be performed from the front side of the wafer. Second, the CMOS wafer fabrication must be completed at the foundry, and subsequent post-processing performed to add the neutron conversion layer. [0054] To accomplish these goals, the present invention encompasses a fabrication sequence which creates a detector device having a memory cell array, or other charge sensing array, and all supporting decoding, addressing and interface circuitry needed to implement a detector system. The device is fabricated utilizing substantially standard foundry CMOS processing. [0055] Each memory cell contains at least one sensitive node at which charge that is injected or removed can alter the memory state of the cell. The physical layout of the memory cell expands the semiconductor region representing the sensitive node to a relatively large area, in order to increase the probability for capture of alpha particles.

[0056] Further, routing or interconnect lines including metal and polysilicon are configured to avoid the region over this sensitive node. Using this novel design, a window or cavity can be etched by the foundry from the front surface of the device chip down to the surface of the semiconductor region representing the sensitive node. This cavity and the sensitive node may have an area more than 20% of the total area of the memory cell. This device and chip architecture is generally shown in Figs. 4, 5 and 6. [0057] The foundry etches this cavity through the silicon dioxide or other passivation over-layer, also referred to herein as the cavity layer, and the bottom surface of this etched cavity will extend downward to the top surface of the silicon material composing the sensitive node of the circuit. The etch may be stopped by the suicide layer at the surface of the silicon, by the silicon itself, or by another etch stop appropriately inserted in the process.

[0058] In a next step, a thin layer of passivating/insulating material (such as silicon dioxide or silicon nitride) may be deposited into the cavity, to form a thin barrier between the sensitive node and the conversion layer yet to be deposited. This layer prevents direct contact between the conversion layer and the silicon and by the addition of adhesion and diffusion barrier layers, such as titanium, further limits boron out- diffusion, and enhances long term stability of doping profiles.

[0059] After completing the foundry phase of manufacturing process, the entire CMOS cell circuit can be tested using conventional memory test techniques, after which the wafer is removed from the foundry for the postprocessing stage. Alternatively, the foundry may defer the etching of the cavity over the sensitive node to the post-processing phase. The entire chip can still be electrically tested as noted above.

[0060] After CMOS wafer fabrication, the wafer undergoes post-processing which will place the neutron conversion layer in close proximity to the sensitive node. This series of post-processing steps may be performed in a separate facility, and therefore not interrupt the normal flow of the CMOS foundry. [0061] After the cavity is etched over the sensitive node (either at the foundry or at the post processing facility), a cleaning operation is performed. Subsequently a thin layer of the material may be deposited in the cavity on top of the insulating layer for assuring adhesion of the neutron conversion layer. This thin material may be for example 250 A of titanium. Following this, the neutron conversion layer, such as boron- 10 is deposited in the cavity to the thickness of approximately 2.5 microns. Finally, a passivation layer may be deposited over the top to seal and protect the conversion layer.

[0062] The deposition of the materials into the cavity is normally patterned in a manner such that the layers of materials are localized to the region of the cavity and do not extend over the entire surface of the chip in ways that could interfere with bond pads or other interconnect. The patterning of these layers can be accomplished by traditional photolithography or shadow masks utilized during the film process.

[0063] Further, as illustrated in Fig. 6, another aspect of this invention can be a novel device layout in which multiple sensitive nodes from multiple cells fabricated and positioned to be under a single cavity and conversion layer. There are no other circuit elements in the area defined by the cavity. This simplifies the conversion layer processing and enhances the processing yield by requiring fewer total cavities and increasing the size of each cavity.

[0064] This sequence of manufacturing steps creates a neutron sensor device with the advantages described above, including low cost, high-yield, low quiescent power dissipation, small size, modularity compatible with stacking for increased efficiency, and a range of stacking depths to tailor the efficiency for a wide range of neutron sensing applications.

[0065] Although the embodiment of the device shown is a chip having a flat, planar structure, the present invention allows multiple chips to be "stacked" in packaging similar to the way that memory chips are conventionally stacked in "thumb drives" or "memory sticks". If multiple chips are stacked, the detection efficiency of the total sensor device, which is now a combination of such chips, can be increased with each chip added, while the total volume of the sensor remains small compared to other prior art detector.

[0066] The inventions described herein are not restricted to the particular details described herein. Indeed many other variations of the foregoing description and drawings may be made within the scope of the present inventions.

[0067] Thus, although there have been described particular embodiments of the present invention of a new and useful Neutron Detection Semiconductor Device and Method for Manufacture, it is not intended that such references be construed as limitations upon the scope of this invention except as set forth in the following claims.

Claims

CLAIMSWhat is claimed is:

1. A semiconductor device for detection of neutron particles comprising: a detector layer comprising an array of multiple detector cells; each detector cell being switchable between first and second electrical states and further comprising at least one sensitive node that is functional to cause the cell to switch electrical states in response to the presence of an alpha particle intersecting the sensitive node; read/write circuitry coupled to each of the detector cells and functional to communicate the electrical states of each of the detector cells external to the device; and a cavity layer disposed over and proximate to the detector layer, at least a portion of the cavity layer comprising a conversion layer functional to emit an alpha particle toward the detector layer in response to capture of a neutron particle in the conversion layer.

2. The device of Claim 1 wherein each of the detector cells comprises at least one CMOS transistor having a gate, a source and a drain, and wherein at least one drain of one CMOS transistor is physically enhanced with respect to the source of that CMOS transistor to define a sensitive node for that detector cell.

3. The device of Claim 2 wherein the cavity layer comprises a cavity defined in the cavity layer proximate the sensitive node, the cavity having a cavity bottom surface, and wherein the conversion layer is deposited in the cavity proximate the cavity bottom surface.

4. The device of Claim 3 wherein the conversion layer comprises a layer of a boron isotope.

5. The device of Claim 3 wherein the conversion layer comprises a layer of lithium.

6. The device of Claim 3 wherein the conversion layer comprises a layer of lithium and a layer of a boron isotope.

7. The device of Claim 3 wherein the drain is physically enhanced to define the sensitive node by increasing the surface area of a top surface of the drain with respect to the nominal surface areas of the source.

8. The device of Claim 7 wherein the cavity is positioned in the cavity layer substantially away from other functional structures in the cavity layer so that the cavity bottom surface is optimally positioned near the top surface of the drain.

9. The device of Claim 2 wherein each of the detector cells comprises at least first and second pairs of an n- channel and a p-channel CMOS transistor electrically arranged as first and second cross-coupled inverters to define a static CMOS memory cell circuit.

10. The device of Claim 9 further comprising an array power circuit functional to supply an inverter operating voltage to the array of detector cells, and a device power circuit functional to provide device operating power to the circuitry device excluding the array, and wherein the array power circuit is functional to operate in cell reading/writing and cell detection modes, the detection mode characterized by providing a reduced inverter operating voltage to the first and second inverters thereby increasing the sensitivity of the detector cells during particle detection, and the cell reading/writing mode characterized by providing an increased inverter operating voltage to the first and second inverters to provide proper cell writing and to inhibit accidental changes to the electrical states of the cells during reading of the cells.

11. The device of Claim 10 wherein the array power circuit comprises a first inverter power circuit functional to provide a first inverter operating voltage to the first inverter in each cell and a second inverter power circuit functional to provide a second inverter operating voltage to the second inverter in each cell, and wherein the array power circuit is functional to selectively adjust the first inverter operating voltage separately from the second inverter operating voltage.

12. The device of Claim 4 wherein the boron isotope is deposited in the cavity to a thickness of 2 to 4 microns, and the top surface of the sensitive node is separated from the bottom surface of the cavity by less than 2 microns.

13. The device of Claim 12 wherein the top surface of the sensitive node is separated from the bottom surface of the cavity by less than 1 micron.

14. The device of Claim 2 wherein each of the detector cells comprises a static CMOS memory cell circuit having first and second cross-coupled inverters, and wherein the first inverter comprises a resistor connected in series with a drain of a first CMOS transistor, and the second inverter comprises a second CMOS transistor having a drain coupled to a drain of a third CMOS transistor.

15. The device of Claim 14 wherein the first CMOS transistor is an n-channel transistor, the second CMOS transistor is a p-channel transistor, and the third CMOS transistor is an n-channel transistor.

16. The device of Claim 2 wherein each of the detector cells comprises a static CMOS memory cell circuit having first and second cross-coupled inverters, and wherein the first inverter comprises a first CMOS transistor, and the second inverter comprises a second CMOS transistor having a drain coupled to a drain of a third CMOS transistor.

17. The device of Claim 2 wherein each of the detector cells comprises a static CMOS memory cell circuit having first and second cross-coupled inverters, and wherein the first inverter comprises a first resistor connected in series with a drain of a first CMOS transistor, and the second inverter comprises a second resistor connected in series with a drain of a second CMOS transistor.

18. The device of Claim 16 wherein the first CMOS transistor is an n-channel transistor and the second CMOS transistor is an n-channel transistor.

19. The device of Claim 9 wherein each of the CMOS transistors has a drain, and the drain of one of the n-channel CMOS transistors is the sensitive node, the device further comprising a diode connected from the sensitive node to ground.

20. A method of manufacturing a semiconductor device for neutron detection comprising:

(a) fabricating an array of CMOS memory cells in a detection layer, each memory cell having at least one sensitive node formed therein, the sensitive node having a sensing volume for collection of deposited charge;

(b) fabricating a cavity layer over the detection layer;

(c) etching cavities in the cavity layer over at least one of the sensitive nodes in the memory cells, each of the cavities having a bottom surface at or near the top surface of the corresponding sensitive node; and

(d) depositing a conversion layer in the cavities.

21. The method of Claim 20 further comprising depositing an insulating layer against the bottom surface of the cavities

22. The method of Claim 21 further comprising depositing a top passivation layer over the conversion layer.

23. The method of Claim 20 wherein each of the CMOS memory cells comprise at least one CMOS transistor having a drain, source and gate, and wherein the method further comprises enlarging the drain of the at least one CMOS transistor compared to the source to define the sensitive node.

24. The method of Claim 20 wherein the CMOS memory cell comprises a first CMOS transistor with a drain connected to a drain of a second CMOS transistor, and wherein the drain of the first CMOS transistor is the sensitive node, and the method further comprises decreasing a nominal W/L ratio of the second CMOS transistor to increase transistor on resistance relative to the first CMOS transistor.

25. The method of Claim 20 wherein steps (a) and (b) are performed in a wafer foundry phase in a wafer foundry from a front side of a CMOS wafer and steps (c) and (d) are performed in a post-processing stage.

26. The method of Claim 20 wherein steps (a), (b) and (c) are performed in a wafer foundry phase in a wafer foundry from a front side of a CMOS wafer and step (d) is performed in a post- processing phase.

27. The method of Claim 26 wherein the memory cells are electrically tested between the foundry phase and the post-processing phase.

28. A method of operating a neutron detector, the neutron detector including a conversion layer and at least one CMOS memory cell operative to change memory states in response to alpha particles emitted by the conversion layer, the CMOS memory cell including first and second cross-coupled inverters, the method comprising: operating the neutron detector in a detecting mode and in a read/write mode; providing a detector operating voltage to the memory cell; providing a separate inverter supply voltage to the memory cell such that that the inverter supply voltage can be different from the detector operating voltage; and at least during the detecting mode, reducing the inverter supply voltage compared to the detector operating voltage to enhance the alpha particle sensitivity of the memory cell.

29. The method of Claim 28 further comprising: at the completion of the detecting mode, increasing the inverter supply voltage to inhibit accidental changes in the memory state of the memory cells prior to reading of data in the cells during the reading/writing mode.

30. The method of Claim 28 further comprising: providing different inverter supply voltages to the first and second cross- coupled inverters in the memory cell so that the memory cell is more sensitive to being switched into one of the memory states.

31. A semiconductor device for detection of neutron particles comprising: a detector layer comprising a plurality of detector cells; each of the detector cells comprising cell circuitry operable to being switchable between first and second electrical states; each detector cell comprising at least one sensitive node that is functional to cause the cell circuitry to switch electrical states in response to the presence of an alpha particle intersecting the sensitive node; a cavity layer disposed over and proximate to the detector layer, at least a portion of the cavity layer comprising a cavity and conversion layer in the cavity functional to emit an alpha particle toward the detector layer in response to capture of a neutron particle in the conversion layer; and wherein the device has a single cavity and a single conversion layer in an overlapping relationship with a plurality of sensitive nodes corresponding to the plurality of detector cells.

32. The method of Claim 31 wherein the detector cell circuitry is positioned in the device away from the overlapping relationship between the cavity and the sensitive nodes.