WO2010001541A1 - Inductor and method for manufacturing the same - Google Patents

Inductor and method for manufacturing the same Download PDF

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Publication number
WO2010001541A1
WO2010001541A1 PCT/JP2009/002809 JP2009002809W WO2010001541A1 WO 2010001541 A1 WO2010001541 A1 WO 2010001541A1 JP 2009002809 W JP2009002809 W JP 2009002809W WO 2010001541 A1 WO2010001541 A1 WO 2010001541A1
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Prior art keywords
inductor
wiring
recess
insulating film
film
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PCT/JP2009/002809
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French (fr)
Japanese (ja)
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井戸田健
中村敦
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パナソニック株式会社
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Publication of WO2010001541A1 publication Critical patent/WO2010001541A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H01F41/041—Printed circuit coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F2017/0086—Printed inductances on semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to an inductor and a manufacturing method thereof, and more particularly to an inductor in which a metal layer is embedded in an insulating film formed on a semiconductor substrate and a manufacturing method thereof.
  • An inductor is one of the passive elements mounted on a high-frequency circuit LSI (large-scale integrated circuit).
  • FIG. 5A is a plan view of a conventional inductor
  • FIG. 5B is a cross-sectional view taken along the line VB-VB shown in FIG.
  • the inductor 20 has a spiral inductor wiring 11.
  • the inductor wiring 11 has an outer terminal 11 a and an inner terminal 11 b, the outer terminal 11 a is connected to the lower layer wiring 14 through a conductive material provided in the via 12, and the inner terminal 11 b is in the via 13. Is connected to the lower layer wiring 15 through a conductive material provided on the substrate, and electricity is drawn out by the lower layer wirings 14 and 15.
  • an LSI multilayer wiring layer 10 is formed on the upper surface of a semiconductor substrate 1 having active elements such as MOS (metal oxide semiconductor) transistors or bipolar transistors.
  • An insulating layer 16 is provided on the upper surface of the layer 10, the inductor wiring 11 is formed on the upper surface of the insulating layer 16, and the cross-sectional shape of the inductor wiring 11 is rectangular.
  • a Q value (Quality Factor) is used as an index representing the characteristics of an inductor.
  • the Q value is determined by a value obtained by dividing the inductor value at the resonance frequency by the series resistance of the circuit, and is expressed by the following (Equation 1).
  • Patent Document 1 discloses that the cross-sectional shape of the inductor wiring is U-shaped in order to increase the surface area of the inductor wiring.
  • an inductor wiring generally, an aluminum alloy film (Al alloy film) is etched using a resist mask.
  • Al alloy film Al alloy film
  • increasing the thickness of the resist mask causes an increase in the amount of impurities attached to the side walls of the Al alloy film when the resist mask is removed.
  • the side wall of the Al alloy film is the side wall of the Al alloy film formed by etching.
  • Impurities are products generated when the resist is removed, for example, etching residues. If an inductor wiring having a large film thickness is to be formed in this way, an amount of etching residue or the like adhering to the side surface of the inductor wiring formed by etching is increased. Therefore, it is difficult to accurately form an inductor wiring having a large film thickness and excellent reliability.
  • Patent Document 2 A method for solving this problem is disclosed in Patent Document 2, for example.
  • JP 09-82708 A Japanese Patent Laid-Open No. 2002-217372
  • the present invention has been made in view of such a point, and using a new method different from the known method, it is possible to suppress a decrease in the Q value of the inductor due to the skin effect in a high frequency region where the operating frequency is high, Furthermore, an inductor wiring having a large film thickness and excellent reliability is formed with high accuracy.
  • an insulating film is provided on a semiconductor substrate, and an inductor wiring is embedded in the insulating film.
  • the inductor wiring is made of metal and formed in a spiral shape, and its cross-sectional shape is U-shaped.
  • the surface area of the inductor wiring can be increased, it is possible to suppress a decrease in the Q value in the high frequency region.
  • the inductor wiring is embedded in the insulating film, it is possible to prevent the side walls of the inductor wiring from being exposed during the manufacture of the inductor. Therefore, an inductor having excellent reliability can be formed with high precision even when the inductor wiring is thick.
  • a recess is formed on the upper surface of the insulating film.
  • the recess may be narrower as it is recessed from the upper surface of the insulating film, and it is only necessary that the inductor wiring is provided in the recess.
  • the insulating film may be made of non-doped silicate glass.
  • the method for manufacturing an inductor according to the present invention includes a step (a) of providing an insulating film on a semiconductor substrate, and a step of forming a recess on the upper surface of the insulating film so that the shape of the upper surface of the insulating film is spiral (b) And a step (c) of providing the inductor wiring in the recess so that the cross-sectional shape is U-shaped.
  • the cross-sectional shape of the inductor wiring is U-shaped, the surface area of the inductor wiring can be increased. Further, the step (c) can prevent the side wall of the inductor wiring from being exposed during the manufacture of the inductor.
  • a recess may be formed on the upper surface of the insulating film so as to become narrower as it is recessed from the upper surface of the insulating film. Thereby, the thickness of the inductor wiring can be made uniform.
  • an insulating layer made of non-doped silicate glass may be formed using a high-density plasma CVD (chemical vapor deposition) method.
  • the step (c) includes a step (c1) of forming a metal layer on the insulating film and a step (c2) of removing the metal layer until the upper surface of the portion of the insulating film where the recess is not formed is exposed. It is preferable. In this step (c1), it is only necessary that the upper surface of the portion of the metal layer formed on the bottom surface of the recess is located below the upper surface of the portion of the insulating film where the recess is not formed. Thereby, the cross-sectional shape of inductor wiring can be made into a U-shape.
  • the metal layer may be removed by wet etching using an aqueous tetramethylguanidine solution.
  • the present invention it is possible to suppress a decrease in the Q value of the inductor due to the skin effect in a high frequency region, and it is possible to accurately form an inductor wiring having a large film thickness and excellent reliability.
  • FIG. 1A is a plan view showing the inductor according to the first embodiment of the present invention
  • FIG. 1B is a cross-sectional view taken along the line IB-IB shown in FIG.
  • FIGS. 2A to 2C are cross-sectional views showing the inductor manufacturing method according to the first embodiment of the present invention in the order of steps.
  • 3A to 3B are cross-sectional views showing the inductor manufacturing method according to the first embodiment of the present invention in the order of steps.
  • 4A to 4B are cross-sectional views showing the inductor manufacturing method according to the first embodiment of the present invention in the order of steps.
  • FIG. 5A is a plan view showing a conventional inductor
  • FIG. 5B is a cross-sectional view taken along the line VB-VB shown in FIG.
  • FIG. 1A is a plan view of the inductor 100 of the present embodiment
  • FIG. 1B is a cross-sectional view taken along the line IB-IB shown in FIG. 1A.
  • the inductor 100 has a spiral inductor Al wiring (inductor wiring) 111, and the inductor Al wiring 111 is referred to as a non-doped silicate glass film (hereinafter referred to as “NSG film”). NSG is an abbreviation for non-doped silicate glass and is an “insulating film” in claims.
  • the inductor Al wiring 111 has an outer terminal 111 a at the outer end of the spiral, and the outer terminal 111 a is connected to the upper wiring 114 through a conductive material provided in the via 112.
  • the inductor Al wiring 111 has an inner terminal 111 b at the inner end of the spiral, and the inner terminal 111 b is connected to the upper layer wiring 115 through a conductive material provided in the via 113.
  • an LSI multilayer wiring layer 10 is formed on the upper surface of the semiconductor substrate 1 having active elements such as MOS transistors or bipolar transistors. Is provided with an insulating layer 116. A silicon oxide film 117 is provided on the upper surface of the insulating layer 116, and a first recess 118 is formed on the upper surface of the silicon oxide film 117. The first recess 118 is formed in a spiral shape on the upper surface of the silicon oxide film 117 and has a square cross-sectional shape. An NSG film 119 is formed in the first recess 118, and a second recess (recess) 120 is formed on the upper surface of the NSG film 119.
  • the second recess 120 is located in the first recess 119 and is formed so as to become narrower as it is recessed.
  • An inductor Al wiring 111 is provided in the second recess 120, and a third recess 121 is formed at the center of the upper surface of the inductor Al wiring 111. Thereby, the cross-sectional shape of the inductor Al wiring 111 is U-shaped. Vias 112 and 113 are provided in some of the third recesses 121 (the vias 112 are not shown in FIG. 1B).
  • a silicon oxide film 123 is provided.
  • the silicon oxide film 123 is not provided on the bottom surfaces of the via 112 and the via 113, so that the inductor Al wiring 111 is respectively formed on the upper layer via the conductive material provided in the via 112 and the via 113.
  • the wirings 114 and 115 are connected.
  • FIG. 2 (a) to 4 (b) are cross-sectional views showing the manufacturing method of the inductor 100 of this embodiment in the order of steps, and each cross-sectional view is a cross-sectional view taken along line IB-IB shown in FIG. 1 (a). .
  • an LSI multilayer wiring layer 10 and an insulating layer 116 are sequentially formed on the upper surface of a semiconductor substrate 1 having active elements such as MOS transistors or bipolar transistors.
  • a silicon oxide film 117 having a thickness of about 2 to 3 ⁇ m is formed on the upper surface of the insulating layer 116.
  • a first recess 118 having a square cross section is formed on the upper surface of the silicon oxide film 117 by using a normal photolithography technique.
  • the depth of the first recess 118 depends on the thickness of the silicon oxide film 117, but may be about 1.5 to 2.5 ⁇ m.
  • the first recess 118 is spiral on the upper surface of the silicon oxide film 117.
  • an NSG film 119 is formed on the upper surface of the silicon oxide film 117 by using a high-density plasma CVD method (step (a)).
  • a second recess 120 that becomes narrower as the recess is formed is formed on the upper surface of the portion of the NSG film 119 located in the first recess 118 (step (b) )).
  • an Al alloy film (metal layer) 111c having a thickness of 1.5 to 3 ⁇ m is formed on the entire top surface of the NSG film 119 by sputtering or the like (step (c1)).
  • the second recessed portion 120 becomes narrower as it is recessed, the thickness of the Al alloy layer 111c can be made uniform. Therefore, as shown in FIG. 3A, the upper surface of the portion of the Al alloy layer 111c provided on the bottom surface of the second recess 120 is the upper surface of the portion of the NSG film 119 where the second recess 120 is not formed.
  • a recess is formed at the center of the upper surface of the portion of the Al alloy layer 111c provided in the second recess 120.
  • the resist 122 is formed thick in the recess of the Al alloy layer 111c, and the resist 122 is thinly formed in a portion of the Al alloy layer 111c where the recess is not formed. Therefore, as shown in FIG. 3B, the upper surface of the resist becomes flat.
  • step (c2) gas reactive ion etching is performed using BBr 3 and Cl 2 (step (c2)).
  • step (c2) gas reactive ion etching is performed using BBr 3 and Cl 2 (step (c2)).
  • BBr 3 / BBr 3 + Cl 2 is about 60%
  • the etching rate of the Al alloy layer 111c and the etching rate of the resist 122 become substantially equal, and the etching progresses while maintaining the state that the upper surface is flat.
  • the etching is stopped when the upper surface of the portion of the NSG film 119 where the second recess 120 is not formed is exposed, as shown in FIG. 4A, the NSG film 119 is embedded in the second recess 120 and has a cross-sectional shape.
  • a U-shaped Al alloy inductor Al wiring 111 is formed (step (c)).
  • the resist 122 a remains in the third recess 121 of the inductor Al wiring 111. Therefore, the resist 122a remaining in the third
  • a silicon oxide film 123 is formed on the upper surface of the portion of the NSG film 119 where the second recess 120 is not formed and the upper surface of the inductor Al wiring 111, and then silicon oxide is formed at the position where the via 112 and the via 113 are provided.
  • the membrane 123 is opened.
  • the upper layer wiring 115 is formed through the conductive material provided in the via 113 and the upper layer wiring 114 is formed through the conductive material provided in the via 112 using a normal wiring formation method. To do. Thereby, the inductor shown in FIG. 4B is formed.
  • the cross-sectional shape of the inductor Al wiring 111 is U-shaped, the surface area of the inductor Al wiring 111 is increased, and the increase in resistance of the inductor wiring due to the skin effect during high-frequency operation can be suppressed. . Therefore, the Q value of the inductor can be increased.
  • the inductor Al wiring 111 is embedded in the NSG film 119. Therefore, it is possible to prevent the residue generated during etching from adhering to the side wall of the inductor Al wiring 111. Further, due to the fact that the lower side of the upper side of the Al alloy layer is hard to be etched, the lower side of the inductor Al wiring 111 may be slightly wider than the upper side (having a hem-expanded shape). Can be suppressed. Therefore, an inductor having excellent reliability can be formed with high accuracy.
  • the Al alloy layer 111c is etched in a state where the Al alloy layer 111c is embedded in the NSG film 119. Therefore, since the side wall of the Al alloy layer 111c can be prevented from being exposed during etching, it is possible to suppress the etching residue from adhering to the side wall of the Al alloy layer 111c. Further, since the side wall of the Al alloy layer 111c is not etched, it is possible to prevent the lower side of the inductor Al wiring 111 from becoming slightly wider (become flared) than the upper side.
  • the inductor Al wiring 111 since the surface area of the inductor Al wiring 111 is increased, the inductor Al wiring 111 has a heat dissipation effect. Thereby, since the temperature rise of inductor Al wiring 111 itself can be suppressed, the reliability of an inductor can be improved.
  • the upper surface of the portion of the Al alloy layer 111c provided on the bottom surface of the second recess 120 is the same as that of the NSG film 119. 2 Located below the upper surface of the portion where the recess 120 is not formed. 4A, when the etching of the Al alloy layer 111c is stopped when the upper surface of the portion of the NSG film 119 where the second recess 120 is not formed is exposed, the cross-sectional shape is U-shaped. Inductor Al wiring 111 can be formed.
  • the Al alloy layer 111c and the resist 122 are etched using reactive ion etching, but the Al alloy layer 111c and the resist 122 may be etched by wet etching using a tetramethylguanidine aqueous solution.
  • the present invention is useful for an inductor, a manufacturing method thereof, and the like, and can be applied to an LSI used for a communication device or the like.
  • Multilayer wiring layer 100 Inductor 111 Inductor Al wiring (Inductor wiring) 111a Outer terminal 111b Inner terminal 111c Al alloy layer 112 Via 113 Via 114 Upper layer wiring 115 Upper layer wiring 116 Insulation layer 117 Silicon oxide film 118 First recess 119 NSG film (insulating film) 120 Second recess (recess) 121 Third recess 122 resist 122a resist 123 Silicon oxide film

Abstract

An insulating film (119) is arranged on a semiconductor substrate (1), and an inductor wiring (111) is embedded in the insulating film (119). The inductor wiring (111) is composed of a metal and is spirally formed. The inductor wiring (111) has a U-shaped cross-section.

Description

インダクタ及びその製造方法Inductor and manufacturing method thereof
　本発明は、インダクタ及びその製造方法に関し、特に半導体基板上に形成された絶縁膜内に金属層が埋め込まれてなるインダクタ及びその製造方法に関する。 The present invention relates to an inductor and a manufacturing method thereof, and more particularly to an inductor in which a metal layer is embedded in an insulating film formed on a semiconductor substrate and a manufacturing method thereof.
　近年、携帯電話機などの通信機器に用いられる高周波回路の高性能化が要求されている。高周波回路用ＬＳＩ（large‐scale integrated circuit）に搭載される受動素子の１つにインダクタがある。 In recent years, there has been a demand for higher performance of high-frequency circuits used in communication devices such as mobile phones. An inductor is one of the passive elements mounted on a high-frequency circuit LSI (large-scale integrated circuit).
　以下、従来のインダクタについて図５（ａ）及び（ｂ）を参照して説明する。図５（ａ）は従来のインダクタの平面図であり、図５（ｂ）は図５（ａ）に示すVB－VB線における断面図である。 Hereinafter, a conventional inductor will be described with reference to FIGS. 5 (a) and 5 (b). FIG. 5A is a plan view of a conventional inductor, and FIG. 5B is a cross-sectional view taken along the line VB-VB shown in FIG.
　図５（ａ）に示すように、インダクタ２０は、渦巻き状のインダクタ配線１１を有する。インダクタ配線１１は外側端子１１ａ及び内側端子１１ｂを有しており、外側端子１１ａはヴィア１２内に設けられた導電性材料を介して下層配線１４に接続されており、内側端子１１ｂはヴィア１３内に設けられた導電性材料を介して下層配線１５に接続されており、下層配線１４及び１５により電気が引き出されている。また、図５（ｂ）に示すように、ＭＯＳ（metal oxide semiconductor）トランジスタ又はバイポーラトランジスタ等の能動素子を有する半導体基板１の上面上にはＬＳＩの多層配線層１０が形成されており、多層配線層１０の上面上には絶縁層１６が設けられており、インダクタ配線１１は絶縁層１６の上面上に形成されており、インダクタ配線１１の横断面形状は方形である。 As shown in FIG. 5A, the inductor 20 has a spiral inductor wiring 11. The inductor wiring 11 has an outer terminal 11 a and an inner terminal 11 b, the outer terminal 11 a is connected to the lower layer wiring 14 through a conductive material provided in the via 12, and the inner terminal 11 b is in the via 13. Is connected to the lower layer wiring 15 through a conductive material provided on the substrate, and electricity is drawn out by the lower layer wirings 14 and 15. Further, as shown in FIG. 5B, an LSI multilayer wiring layer 10 is formed on the upper surface of a semiconductor substrate 1 having active elements such as MOS (metal oxide semiconductor) transistors or bipolar transistors. An insulating layer 16 is provided on the upper surface of the layer 10, the inductor wiring 11 is formed on the upper surface of the insulating layer 16, and the cross-sectional shape of the inductor wiring 11 is rectangular.
　次に、渦巻き状のインダクタの特性について説明する。インダクタの特性を表す指標として、一般に、Ｑ値（Quality Factor）が用いられている。例えば、直列共振ＬＣ回路において、Ｑ値は、共振周波数におけるインダクタ値を回路の直列抵抗で割った値により決定され、次の（式１）で表される。 Next, the characteristics of the spiral inductor will be described. In general, a Q value (Quality Factor) is used as an index representing the characteristics of an inductor. For example, in a series resonance LC circuit, the Q value is determined by a value obtained by dividing the inductor value at the resonance frequency by the series resistance of the circuit, and is expressed by the following (Equation 1).
　Ｑ＝ωＬ／Ｒ　……　（式１）
　（式１）において、ωは２πｆ、πは円周率、ｆは周波数、Ｌはインダクタンス値、Ｒは抵抗値である。 Q = ωL / R (Formula 1)
In (Equation 1), ω is 2πf, π is the circumference, f is the frequency, L is the inductance value, and R is the resistance value.
　Ｑ値が大きな値であるほどインダクタは電気特性に優れ、また、Ｑ値が大きいことは回路の低消費電力化に寄与する。（式１）からわかるように、Ｑ値を大きくするためには抵抗値Ｒを小さくすればよい。 ¡The larger the Q value, the better the electrical characteristics of the inductor, and the larger the Q value, the lower the power consumption of the circuit. As can be seen from (Equation 1), in order to increase the Q value, the resistance value R may be decreased.
　しかし、駆動周波数が高くなると、表皮効果によりインダクタ配線の表面（図５（ｂ）のインダクタ配線１１のように横断面形状が矩形であれば、上面、下面及び両側面）近傍に電流が集中しやすい。その結果、高周波動作時には、インダクタ配線の抵抗成分が大きくなるのでＱ値が減少してしまう。この問題は、携帯電話機などで使用される１～６ＧＨｚの周波数帯においても生じる。この問題を解決するためには、インダクタ配線の表面積を大きくすることが効果的である。例えば特許文献１には、インダクタ配線の表面積を大きくするためにインダクタ配線の横断面形状をＵ字型とするということが開示されている。 However, when the drive frequency increases, current concentrates near the surface of the inductor wiring (upper surface, lower surface, and both side surfaces if the cross-sectional shape is rectangular like the inductor wiring 11 in FIG. 5B) due to the skin effect. Cheap. As a result, at the time of high frequency operation, the resistance component of the inductor wiring becomes large, so that the Q value decreases. This problem also occurs in the 1 to 6 GHz frequency band used for mobile phones and the like. In order to solve this problem, it is effective to increase the surface area of the inductor wiring. For example, Patent Document 1 discloses that the cross-sectional shape of the inductor wiring is U-shaped in order to increase the surface area of the inductor wiring.
　一方、インダクタ配線の膜厚を大きくすることによって抵抗値Ｒを小さくするという方法がある。しかし、インダクタ配線の膜厚が大きくなると、次に示す不具合を招来する。インダクタ配線を形成する場合、一般に、レジストマスクを用いてアルミ合金膜（Ａｌ合金膜）をエッチングする。膜厚の大きなインダクタ配線を形成するためには、レジストマスクのエッチング耐性等の問題から、レジストマスクの膜厚を大きくすることが好ましい。ところが、レジストマスクの膜厚を大きくすると、レジストマスクを除去するときにＡｌ合金膜の側壁へ付着する不純物の量の増加を招来する。ここで、Ａｌ合金膜の側壁とは、エッチングにより形成されたＡｌ合金膜の側壁である。不純物とは、レジストを除去する際に発生する生成物であり、例えばエッチング残渣物である。このように膜厚の大きなインダクタ配線を形成しようとすると、エッチングにより形成されたインダクタ配線の側面に付着するエッチング残渣物などの量の増加を招来する。そのため、膜厚が大きく信頼性に優れたインダクタ配線を精度良く形成することは困難である。この不具合を解決する方法は例えば特許文献２に開示されている。 On the other hand, there is a method of reducing the resistance value R by increasing the film thickness of the inductor wiring. However, when the thickness of the inductor wiring is increased, the following problems are caused. When forming an inductor wiring, generally, an aluminum alloy film (Al alloy film) is etched using a resist mask. In order to form an inductor wiring having a large film thickness, it is preferable to increase the film thickness of the resist mask in view of problems such as etching resistance of the resist mask. However, increasing the thickness of the resist mask causes an increase in the amount of impurities attached to the side walls of the Al alloy film when the resist mask is removed. Here, the side wall of the Al alloy film is the side wall of the Al alloy film formed by etching. Impurities are products generated when the resist is removed, for example, etching residues. If an inductor wiring having a large film thickness is to be formed in this way, an amount of etching residue or the like adhering to the side surface of the inductor wiring formed by etching is increased. Therefore, it is difficult to accurately form an inductor wiring having a large film thickness and excellent reliability. A method for solving this problem is disclosed in Patent Document 2, for example.
特開平０９－８２７０８号公報JP 09-82708 A 特開平２００２－２１７３７２号公報Japanese Patent Laid-Open No. 2002-217372
　インダクタの動作周波数が高い高周波領域では、表皮効果によってインダクタのＱ値が減少する虞がある。また、膜厚の大きなインダクタ配線を精度且つ信頼性良く形成することは困難を伴う。 In the high frequency region where the operating frequency of the inductor is high, there is a risk that the Q value of the inductor will decrease due to the skin effect. In addition, it is difficult to form a thick inductor wiring with high accuracy and reliability.
　本発明は、かかる点に鑑みてなされたものであり、公知の方法とは異なる新たな方法を用いて、動作周波数が高い高周波領域において表皮効果に起因するインダクタのＱ値の減少を抑制でき、さらには、膜厚が大きく信頼性に優れたインダクタ配線を精度良く形成することである。 The present invention has been made in view of such a point, and using a new method different from the known method, it is possible to suppress a decrease in the Q value of the inductor due to the skin effect in a high frequency region where the operating frequency is high, Furthermore, an inductor wiring having a large film thickness and excellent reliability is formed with high accuracy.
　本発明に係るインダクタでは、半導体基板の上に絶縁膜が設けられており、絶縁膜内にはインダクタ配線が埋め込まれている。インダクタ配線は金属からなり渦巻き状に形成されており、その横断面形状はＵ字型である。 In the inductor according to the present invention, an insulating film is provided on a semiconductor substrate, and an inductor wiring is embedded in the insulating film. The inductor wiring is made of metal and formed in a spiral shape, and its cross-sectional shape is U-shaped.
　これにより、インダクタ配線の表面積を大きくすることができるので、高周波領域におけるＱ値の減少を抑制することができる。また、インダクタ配線が絶縁膜内に埋め込まれているので、インダクタの製造中にインダクタ配線の側壁が露出することを防止できる。よって、インダクタ配線の膜厚が分厚い場合であっても信頼性に優れたインダクタを精度良く形成することができる。 Thereby, since the surface area of the inductor wiring can be increased, it is possible to suppress a decrease in the Q value in the high frequency region. In addition, since the inductor wiring is embedded in the insulating film, it is possible to prevent the side walls of the inductor wiring from being exposed during the manufacture of the inductor. Therefore, an inductor having excellent reliability can be formed with high precision even when the inductor wiring is thick.
　絶縁膜の上面には凹部が形成されていることが好ましい。凹部は絶縁膜の上面から凹むにつれて幅狭であれば良く、凹部内にインダクタ配線が設けられていれば良い。 It is preferable that a recess is formed on the upper surface of the insulating film. The recess may be narrower as it is recessed from the upper surface of the insulating film, and it is only necessary that the inductor wiring is provided in the recess.
　これにより、インダクタの製造中におけるインダクタ配線の側壁の露出を阻止できる。 This can prevent the exposure of the inductor wiring sidewalls during the manufacture of the inductor.
　絶縁膜は、ノンドープトシリケートガラスからなれば良い。 The insulating film may be made of non-doped silicate glass.
　本発明に係るインダクタの製造方法は、半導体基板の上に絶縁膜を設ける工程（ａ）と、絶縁膜の上面における形状が渦巻き状となるように絶縁膜の上面に凹部を形成する工程（ｂ）と、横断面形状がＵ字型となるようにインダクタ配線を凹部内に設ける工程（ｃ）とを備えている。 The method for manufacturing an inductor according to the present invention includes a step (a) of providing an insulating film on a semiconductor substrate, and a step of forming a recess on the upper surface of the insulating film so that the shape of the upper surface of the insulating film is spiral (b) And a step (c) of providing the inductor wiring in the recess so that the cross-sectional shape is U-shaped.
　これにより、インダクタ配線の横断面形状がＵ字型となるので、インダクタ配線の表面積を大きくすることができる。また、工程（ｃ）により、インダクタの製造中にインダクタ配線の側壁が露出することを防止できる。 Thereby, since the cross-sectional shape of the inductor wiring is U-shaped, the surface area of the inductor wiring can be increased. Further, the step (c) can prevent the side wall of the inductor wiring from being exposed during the manufacture of the inductor.
　工程（ｂ）では、絶縁膜の上面から凹むにつれて幅狭となるように凹部を絶縁膜の上面に形成すれば良い。これにより、インダクタ配線の厚みを均一にすることができる。 In step (b), a recess may be formed on the upper surface of the insulating film so as to become narrower as it is recessed from the upper surface of the insulating film. Thereby, the thickness of the inductor wiring can be made uniform.
　工程（ａ）では、高密度プラズマＣＶＤ（chemical vapor deposition）法を用いてノンドープトシリケートガラスからなる絶縁層を形成すれば良い。 In step (a), an insulating layer made of non-doped silicate glass may be formed using a high-density plasma CVD (chemical vapor deposition) method.
　工程（ｃ）は、絶縁膜上に金属層を形成する工程（ｃ１）と、絶縁膜のうち凹部が形成されていない部分の上面が露出するまで金属層を除去する工程（ｃ２）とを有していることが好ましい。この工程（ｃ１）では、金属層のうち凹部の底面上に形成された部分の上面が、絶縁膜のうち凹部が形成されていない部分の上面よりも下に位置していれば良い。これにより、インダクタ配線の横断面形状をＵ字型とすることができる。また、工程（ｃ２）では、テトラメチルグアニジン水溶液を用いたウェットエッチングにより金属層を除去すれば良い。 The step (c) includes a step (c1) of forming a metal layer on the insulating film and a step (c2) of removing the metal layer until the upper surface of the portion of the insulating film where the recess is not formed is exposed. It is preferable. In this step (c1), it is only necessary that the upper surface of the portion of the metal layer formed on the bottom surface of the recess is located below the upper surface of the portion of the insulating film where the recess is not formed. Thereby, the cross-sectional shape of inductor wiring can be made into a U-shape. In the step (c2), the metal layer may be removed by wet etching using an aqueous tetramethylguanidine solution.
　本発明によれば、高周波領域において表皮効果に起因するインダクタのＱ値の減少を抑制でき、膜厚が大きく信頼性に優れたインダクタ配線を精度良く形成することができる。 According to the present invention, it is possible to suppress a decrease in the Q value of the inductor due to the skin effect in a high frequency region, and it is possible to accurately form an inductor wiring having a large film thickness and excellent reliability.
図１（ａ）は本発明の第１の実施形態に係るインダクタを示す平面図であり、図１（ｂ）は図１（ａ）に示すIB－IB線における断面図である。FIG. 1A is a plan view showing the inductor according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line IB-IB shown in FIG. 図２（ａ）～（ｃ）は、本発明の第１の実施形態に係るインダクタの製造方法を工程順に示す断面図である。FIGS. 2A to 2C are cross-sectional views showing the inductor manufacturing method according to the first embodiment of the present invention in the order of steps. 図３（ａ）～（ｂ）は、本発明の第１の実施形態に係るインダクタの製造方法を工程順に示す断面図である。3A to 3B are cross-sectional views showing the inductor manufacturing method according to the first embodiment of the present invention in the order of steps. 図４（ａ）～（ｂ）は、本発明の第１の実施形態に係るインダクタの製造方法を工程順に示す断面図である。4A to 4B are cross-sectional views showing the inductor manufacturing method according to the first embodiment of the present invention in the order of steps. 図５（ａ）は従来のインダクタを示す平面図であり、図５（ｂ）は図５（ａ）に示すVB－VB線における断面図である。FIG. 5A is a plan view showing a conventional inductor, and FIG. 5B is a cross-sectional view taken along the line VB-VB shown in FIG.
　以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、本発明は、以下に示す実施形態に限定されない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to embodiment shown below.
　（第１の実施形態）
　以下、本発明の第１の実施形態に係るインダクタについて、図面を参照しながら説明する。 (First embodiment)
Hereinafter, an inductor according to a first embodiment of the present invention will be described with reference to the drawings.
　図１（ａ）は本実施形態のインダクタ１００の平面図であり、図１（ｂ）は図１（ａ）に示すIB－IB線における断面図である。 1A is a plan view of the inductor 100 of the present embodiment, and FIG. 1B is a cross-sectional view taken along the line IB-IB shown in FIG. 1A.
　図１（ａ）に示す通り、インダクタ１００は渦巻き状のインダクタＡｌ配線（インダクタ配線）１１１を有しており、インダクタＡｌ配線１１１はノンドープトシリケートガラス膜（以下では、「ＮＳＧ膜」という。なおＮＳＧは、non-doped silicate glassの略であり、特許請求の範囲における「絶縁膜」である。）１１９に埋め込まれている。インダクタＡｌ配線１１１は渦巻きの外側の末端に外側端子１１１ａを有しており、外側端子１１１ａはヴィア１１２内に設けられた導電性材料を介して上層配線１１４に接続されている。同様に、インダクタＡｌ配線１１１は渦巻きの内側の末端に内側端子１１１ｂを有しており、内側端子１１１ｂはヴィア１１３内に設けられた導電性材料を介して上層配線１１５に接続されている。 As shown in FIG. 1A, the inductor 100 has a spiral inductor Al wiring (inductor wiring) 111, and the inductor Al wiring 111 is referred to as a non-doped silicate glass film (hereinafter referred to as “NSG film”). NSG is an abbreviation for non-doped silicate glass and is an “insulating film” in claims. The inductor Al wiring 111 has an outer terminal 111 a at the outer end of the spiral, and the outer terminal 111 a is connected to the upper wiring 114 through a conductive material provided in the via 112. Similarly, the inductor Al wiring 111 has an inner terminal 111 b at the inner end of the spiral, and the inner terminal 111 b is connected to the upper layer wiring 115 through a conductive material provided in the via 113.
　また、図１（ｂ）に示すように、ＭＯＳトランジスタ又はバイポーラトランジスタ等の能動素子を有する半導体基板１の上面上にはＬＳＩの多層配線層１０が形成されており、多層配線層１０の上面上には絶縁層１１６が設けられている。絶縁層１１６の上面上にはシリコン酸化膜１１７が設けられており、シリコン酸化膜１１７の上面には第１凹部１１８が形成されている。第１凹部１１８はシリコン酸化膜１１７の上面において渦巻き状に形成されており、その横断面形状は方形である。この第１凹部１１８内にはＮＳＧ膜１１９が形成されており、ＮＳＧ膜１１９の上面には第２凹部（凹部）１２０が形成されている。第２凹部１２０は、第１凹部１１９内に位置しており、凹むにつれて幅狭となるように形成されている。第２凹部１２０内にはインダクタＡｌ配線１１１が設けられており、インダクタＡｌ配線１１１の上面の中央部には第３凹部１２１が形成されている。これにより、インダクタＡｌ配線１１１の横断面形状はＵ字型となっている。一部の第３凹部１２１内にはヴィア１１２及びヴィア１１３が設けられており（図１（ｂ）にはヴィア１１２は示されてない）、インダクタＡｌ配線１１１の上面及びＮＳＧ膜１１９の上面にはシリコン酸化膜１２３が設けられている。なお、シリコン酸化膜１２３はヴィア１１２及びヴィア１１３の各底面上には設けられておらず、これにより、インダクタＡｌ配線１１１はヴィア１１２及びヴィア１１３内に設けられた導電性材料を介してそれぞれ上層配線１１４，１１５に接続されている。 Further, as shown in FIG. 1B, an LSI multilayer wiring layer 10 is formed on the upper surface of the semiconductor substrate 1 having active elements such as MOS transistors or bipolar transistors. Is provided with an insulating layer 116. A silicon oxide film 117 is provided on the upper surface of the insulating layer 116, and a first recess 118 is formed on the upper surface of the silicon oxide film 117. The first recess 118 is formed in a spiral shape on the upper surface of the silicon oxide film 117 and has a square cross-sectional shape. An NSG film 119 is formed in the first recess 118, and a second recess (recess) 120 is formed on the upper surface of the NSG film 119. The second recess 120 is located in the first recess 119 and is formed so as to become narrower as it is recessed. An inductor Al wiring 111 is provided in the second recess 120, and a third recess 121 is formed at the center of the upper surface of the inductor Al wiring 111. Thereby, the cross-sectional shape of the inductor Al wiring 111 is U-shaped. Vias 112 and 113 are provided in some of the third recesses 121 (the vias 112 are not shown in FIG. 1B). A silicon oxide film 123 is provided. Note that the silicon oxide film 123 is not provided on the bottom surfaces of the via 112 and the via 113, so that the inductor Al wiring 111 is respectively formed on the upper layer via the conductive material provided in the via 112 and the via 113. The wirings 114 and 115 are connected.
　図２（ａ）～図４（ｂ）は本実施形態のインダクタ１００の製造方法を工程順に示す断面図であり、各断面図は図１（ａ）に示すIB－IB線における断面図である。 2 (a) to 4 (b) are cross-sectional views showing the manufacturing method of the inductor 100 of this embodiment in the order of steps, and each cross-sectional view is a cross-sectional view taken along line IB-IB shown in FIG. 1 (a). .
　まず、図２（ａ）に示すように、ＭＯＳトランジスタ又はバイポーラトランジスタ等の能動素子を有する半導体基板１の上面上に、ＬＳＩの多層配線層１０及び絶縁層１１６を順に形成する。 First, as shown in FIG. 2A, an LSI multilayer wiring layer 10 and an insulating layer 116 are sequentially formed on the upper surface of a semiconductor substrate 1 having active elements such as MOS transistors or bipolar transistors.
　次に、図２（ｂ）に示すように、絶縁層１１６の上面上に、膜厚が約２～３μｍであるシリコン酸化膜１１７を形成する。その後、通常のフォトリソグラフィー技術を用いて、横断面形状が方形である第１凹部１１８をシリコン酸化膜１１７の上面に形成する。第１凹部１１８の深さは、シリコン酸化膜１１７の厚さによるが、約１．５～２．５μｍであれば良い。また、図示していないが、第１凹部１１８は、シリコン酸化膜１１７の上面上において渦巻き状である。その後、高密度プラズマＣＶＤ法を用いて、シリコン酸化膜１１７の上面上にＮＳＧ膜１１９を形成する（工程（ａ））。このとき、図３（ｃ）に示すように、ＮＳＧ膜１１９のうち第１凹部１１８内に位置する部分の上面には、凹むにつれて幅狭となる第２凹部１２０が形成される（工程（ｂ））。 Next, as shown in FIG. 2B, a silicon oxide film 117 having a thickness of about 2 to 3 μm is formed on the upper surface of the insulating layer 116. Thereafter, a first recess 118 having a square cross section is formed on the upper surface of the silicon oxide film 117 by using a normal photolithography technique. The depth of the first recess 118 depends on the thickness of the silicon oxide film 117, but may be about 1.5 to 2.5 μm. Although not shown, the first recess 118 is spiral on the upper surface of the silicon oxide film 117. Thereafter, an NSG film 119 is formed on the upper surface of the silicon oxide film 117 by using a high-density plasma CVD method (step (a)). At this time, as shown in FIG. 3C, a second recess 120 that becomes narrower as the recess is formed is formed on the upper surface of the portion of the NSG film 119 located in the first recess 118 (step (b) )).
　次に、スパッタ法等によりＮＳＧ膜１１９の上面全体に、膜厚が１．５～３μｍであるＡｌ合金膜（金属層）１１１ｃを形成する（工程（ｃ１））。このとき、第２凹部１２０は凹むにつれて幅狭であるので、Ａｌ合金層１１１ｃの厚みを均一にすることができる。よって、図３（ａ）に示すように、Ａｌ合金層１１１ｃのうち第２凹部１２０の底面上に設けられた部分の上面はＮＳＧ膜１１９のうち第２凹部１２０が形成されていない部分の上面よりも下に位置し、Ａｌ合金層１１１ｃのうち第２凹部１２０内に設けられた部分の上面の中央には窪みが形成される。 Next, an Al alloy film (metal layer) 111c having a thickness of 1.5 to 3 μm is formed on the entire top surface of the NSG film 119 by sputtering or the like (step (c1)). At this time, since the second recessed portion 120 becomes narrower as it is recessed, the thickness of the Al alloy layer 111c can be made uniform. Therefore, as shown in FIG. 3A, the upper surface of the portion of the Al alloy layer 111c provided on the bottom surface of the second recess 120 is the upper surface of the portion of the NSG film 119 where the second recess 120 is not formed. A recess is formed at the center of the upper surface of the portion of the Al alloy layer 111c provided in the second recess 120.
　その後、スピンコート法によってレジストを塗布すると、Ａｌ合金層１１１ｃの窪み内にはレジスト１２２が厚く形成され、Ａｌ合金層１１１ｃのうち窪みが形成されていない部分にはレジスト１２２が薄く形成される。よって、図３（ｂ）に示すように、レジストの上面は平坦になる。 Thereafter, when a resist is applied by spin coating, the resist 122 is formed thick in the recess of the Al alloy layer 111c, and the resist 122 is thinly formed in a portion of the Al alloy layer 111c where the recess is not formed. Therefore, as shown in FIG. 3B, the upper surface of the resist becomes flat.
　そして、ＢＢｒ３およびＣｌ２を用いてガス反応性イオンエッチングを施す（工程（ｃ２））。このとき、ＢＢｒ３／ＢＢｒ３＋Ｃｌ２を約６０％とすると、Ａｌ合金層１１１ｃのエッチング速度とレジスト１２２のエッチング速度とがほぼ等しくなり、上面が平坦である状態を維持しながらエッチングが進行する。ＮＳＧ膜１１９のうち第２凹部１２０が形成されていない部分の上面が露出した時点でエッチングを止めると、図４（ａ）に示すように、第２凹部１２０内に埋め込まれ且つ横断面形状がＵ字型であるＡｌ合金のインダクタＡｌ配線１１１が形成される（工程（ｃ））。なお、ここでは、図４（ａ）に示すように、インダクタＡｌ配線１１１の第３凹部１２１内にレジスト１２２ａが残っている。そこで、第３凹部１２１内に残ったレジスト１２２ａをＯ２アッシングなどにより除去する。 Then, gas reactive ion etching is performed using BBr 3 and Cl 2 (step (c2)). At this time, if BBr 3 / BBr 3 + Cl 2 is about 60%, the etching rate of the Al alloy layer 111c and the etching rate of the resist 122 become substantially equal, and the etching progresses while maintaining the state that the upper surface is flat. . When the etching is stopped when the upper surface of the portion of the NSG film 119 where the second recess 120 is not formed is exposed, as shown in FIG. 4A, the NSG film 119 is embedded in the second recess 120 and has a cross-sectional shape. A U-shaped Al alloy inductor Al wiring 111 is formed (step (c)). Here, as shown in FIG. 4A, the resist 122 a remains in the third recess 121 of the inductor Al wiring 111. Therefore, the resist 122a remaining in the third recess 121 is removed by O 2 ashing or the like.
　それから、ＮＳＧ膜１１９のうち第２の凹部１２０が形成されていない部分の上面とインダクタＡｌ配線１１１の上面とにシリコン酸化膜１２３を形成した後、ヴィア１１２及びヴィア１１３が設けられる位置においてシリコン酸化膜１２３を開口させる。最後に、通常の配線形成方法を用いて、ヴィア１１３内に設けられた導電性材料を介して上層配線１１５を形成し、ヴィア１１２内に設けられた導電性材料を介して上層配線１１４を形成する。これにより、図４（ｂ）に示すインダクタが形成される。 Then, a silicon oxide film 123 is formed on the upper surface of the portion of the NSG film 119 where the second recess 120 is not formed and the upper surface of the inductor Al wiring 111, and then silicon oxide is formed at the position where the via 112 and the via 113 are provided. The membrane 123 is opened. Finally, the upper layer wiring 115 is formed through the conductive material provided in the via 113 and the upper layer wiring 114 is formed through the conductive material provided in the via 112 using a normal wiring formation method. To do. Thereby, the inductor shown in FIG. 4B is formed.
　本実施形態のインダクタによると、インダクタＡｌ配線１１１の横断面形状がＵ字型であるので、インダクタＡｌ配線１１１の表面積が増加し、高周波動作時の表皮効果によるインダクタ配線の高抵抗化を抑制できる。よって、インダクタのＱ値を大きくすることができる。 According to the inductor of this embodiment, since the cross-sectional shape of the inductor Al wiring 111 is U-shaped, the surface area of the inductor Al wiring 111 is increased, and the increase in resistance of the inductor wiring due to the skin effect during high-frequency operation can be suppressed. . Therefore, the Q value of the inductor can be increased.
　また、本実施形態のインダクタでは、インダクタＡｌ配線１１１はＮＳＧ膜１１９内に埋め込まれている。よって、エッチング時に生じた残渣物がインダクタＡｌ配線１１１の側壁に付着することを防止できる。また、Ａｌ合金層の上側よりも下側の方がエッチングされにくいことに起因して、インダクタＡｌ配線１１１の下側の方が上側よりも若干幅広となる（裾拡がりの形状となる）ことも抑制することができる。よって、信頼性に優れたインダクタを精度良く形成することができる。 Further, in the inductor of the present embodiment, the inductor Al wiring 111 is embedded in the NSG film 119. Therefore, it is possible to prevent the residue generated during etching from adhering to the side wall of the inductor Al wiring 111. Further, due to the fact that the lower side of the upper side of the Al alloy layer is hard to be etched, the lower side of the inductor Al wiring 111 may be slightly wider than the upper side (having a hem-expanded shape). Can be suppressed. Therefore, an inductor having excellent reliability can be formed with high accuracy.
　具体的には、本実施形態のインダクタの製造方法では、Ａｌ合金層１１１ｃがＮＳＧ膜１１９内に埋め込まれている状態でＡｌ合金層１１１ｃをエッチングしている。よって、Ａｌ合金層１１１ｃの側壁がエッチング中に露出することを防止できるので、エッチング残渣物がＡｌ合金層１１１ｃの側壁に付着することを抑制できる。また、Ａｌ合金層１１１ｃの側壁はエッチングされないので、インダクタＡｌ配線１１１の下側の方が上側よりも若干幅広となる（裾拡がりの形状となる）ことも抑制することができる。 Specifically, in the inductor manufacturing method of the present embodiment, the Al alloy layer 111c is etched in a state where the Al alloy layer 111c is embedded in the NSG film 119. Therefore, since the side wall of the Al alloy layer 111c can be prevented from being exposed during etching, it is possible to suppress the etching residue from adhering to the side wall of the Al alloy layer 111c. Further, since the side wall of the Al alloy layer 111c is not etched, it is possible to prevent the lower side of the inductor Al wiring 111 from becoming slightly wider (become flared) than the upper side.
　さらに、インダクタＡｌ配線１１１の表面積が増加するので、インダクタＡｌ配線１１１は放熱効果を奏する。これにより、インダクタＡｌ配線１１１自体の温度上昇を抑えることができるので、インダクタの信頼性を向上させることができる。 Furthermore, since the surface area of the inductor Al wiring 111 is increased, the inductor Al wiring 111 has a heat dissipation effect. Thereby, since the temperature rise of inductor Al wiring 111 itself can be suppressed, the reliability of an inductor can be improved.
　また、本実施形態のインダクタの製造方法では、図３（ａ）に示すように、Ａｌ合金層１１１ｃのうち第２凹部１２０の底面上に設けられた部分の上面は、ＮＳＧ膜１１９のうち第２凹部１２０が形成されていない部分の上面よりも下に位置する。従って、図４（ａ）に示す工程においてＮＳＧ膜１１９のうち第２凹部１２０が形成されていない部分の上面が露出した時点でＡｌ合金層１１１ｃのエッチングを停止すると、横断面形状がＵ字型であるインダクタＡｌ配線１１１を形成することができる。 In the inductor manufacturing method of the present embodiment, as shown in FIG. 3A, the upper surface of the portion of the Al alloy layer 111c provided on the bottom surface of the second recess 120 is the same as that of the NSG film 119. 2 Located below the upper surface of the portion where the recess 120 is not formed. 4A, when the etching of the Al alloy layer 111c is stopped when the upper surface of the portion of the NSG film 119 where the second recess 120 is not formed is exposed, the cross-sectional shape is U-shaped. Inductor Al wiring 111 can be formed.
　なお、本実施形態では、反応性イオンエッチングを用いてＡｌ合金層１１１ｃ及びレジスト１２２をエッチングしたが、テトラメチルグアニジン水溶液を用いたウェットエッチングによりＡｌ合金層１１１ｃ及びレジスト１２２をエッチングしても良い。 In this embodiment, the Al alloy layer 111c and the resist 122 are etched using reactive ion etching, but the Al alloy layer 111c and the resist 122 may be etched by wet etching using a tetramethylguanidine aqueous solution.
　以上説明したように、本発明は、インダクタ及びその製造方法等に有用であり、通信機器等に用いられるＬＳＩに応用できる。 As described above, the present invention is useful for an inductor, a manufacturing method thereof, and the like, and can be applied to an LSI used for a communication device or the like.
　1　　　　半導体基板 
　10　　 　多層配線層 
　100　　　インダクタ
　111　　　インダクタＡｌ配線 （インダクタ配線） 
　111a 　　外側端子 
　111b 　　内側端子 
　111c 　　Ａｌ合金層 
　112　　　ヴィア 
　113　　　ヴィア 
　114　　　上層配線 
　115　　　上層配線 
　116　　　絶縁層 
　117　　　シリコン酸化膜 
　118　　　第１凹部 
　119　　　ＮＳＧ膜 （絶縁膜）
　120　　　第２凹部 （凹部）
　121　　　第３凹部 
　122　　　レジスト 
　122a 　　レジスト 
　123　　　シリコン酸化膜  1 Semiconductor substrate
10 Multilayer wiring layer
100 Inductor 111 Inductor Al wiring (Inductor wiring)
111a Outer terminal
111b Inner terminal
111c Al alloy layer
112 Via
113 Via
114 Upper layer wiring
115 Upper layer wiring
116 Insulation layer
117 Silicon oxide film
118 First recess
119 NSG film (insulating film)
120 Second recess (recess)
121 Third recess
122 resist
122a resist
123 Silicon oxide film

Claims (8)

  1. 　金属からなり且つ渦巻き状に形成されたインダクタ配線を備え、
    　前記インダクタ配線は、半導体基板の上に設けられた絶縁膜内に埋め込まれており、
    　前記インダクタ配線の横断面形状は、Ｕ字型であることを特徴とするインダクタ。     Inductor wiring made of metal and formed in a spiral shape,
    The inductor wiring is embedded in an insulating film provided on a semiconductor substrate,
    The inductor having a U-shaped cross-sectional shape of the inductor wiring.
  2. 　前記絶縁膜の上面には、前記絶縁膜の上面から凹むにつれて幅狭である凹部が形成されており、
    　前記インダクタ配線は、前記凹部内に設けられていることを特徴とする請求項１に記載のインダクタ。     On the upper surface of the insulating film, a recess that is narrower as it is recessed from the upper surface of the insulating film is formed,
    The inductor according to claim 1, wherein the inductor wiring is provided in the recess.
  3. 　前記絶縁膜は、ノンドープトシリケートガラスからなることを特徴とする請求項１に記載のインダクタ。 2. The inductor according to claim 1, wherein the insulating film is made of non-doped silicate glass.
  4. 　半導体基板の上に、絶縁膜を設ける工程（ａ）と、
    　前記絶縁膜の上面における形状が渦巻き状となるように前記絶縁膜の上面に凹部を形成する工程（ｂ）と、
    　横断面形状がＵ字型となるようにインダクタ配線を前記凹部内に設ける工程（ｃ）とを備えていることを特徴とするインダクタの製造方法。     Providing an insulating film on the semiconductor substrate (a);
    Forming a recess on the upper surface of the insulating film such that the shape on the upper surface of the insulating film is spiral, (b);
    And (c) providing an inductor wiring in the recess so that the cross-sectional shape is U-shaped.
  5. 　前記工程（ｂ）では、前記絶縁膜の上面から凹むにつれて幅狭となるように、前記凹部を前記絶縁膜の上面に形成することを特徴とする請求項４に記載のインダクタの製造方法。 5. The method of manufacturing an inductor according to claim 4, wherein in the step (b), the concave portion is formed on the upper surface of the insulating film so as to become narrower as it is recessed from the upper surface of the insulating film.
  6. 　前記工程（ａ）では、高密度プラズマＣＶＤ法を用いてノンドープトシリケートガラスからなる前記絶縁層を形成することを特徴とする請求項４に記載のインダクタの製造方法。 5. The method of manufacturing an inductor according to claim 4, wherein in the step (a), the insulating layer made of non-doped silicate glass is formed by using a high density plasma CVD method.
  7. 　前記工程（ｃ）は、
    　前記絶縁膜上に、金属層を形成する工程（ｃ１）と、
    　前記絶縁膜のうち前記凹部が形成されていない部分の上面が露出するまで、前記金属層を除去する工程（ｃ２）とを有し、
    　前記工程（ｃ１）では、前記金属層のうち前記凹部の底面上に形成された部分の上面が、前記絶縁膜のうち前記凹部が形成されていない部分の上面よりも下に位置していることを特徴とする請求項４に記載のインダクタの製造方法。     The step (c)
    Forming a metal layer on the insulating film (c1);
    A step (c2) of removing the metal layer until an upper surface of a portion of the insulating film where the recess is not formed is exposed,
    In the step (c1), the upper surface of the portion of the metal layer formed on the bottom surface of the recess is positioned below the upper surface of the portion of the insulating film where the recess is not formed. The method of manufacturing an inductor according to claim 4.
  8. 　前記工程（ｃ２）では、テトラメチルグアニジン水溶液を用いたウェットエッチングにより、前記金属層を除去することを特徴とする請求項７に記載のインダクタの製造方法。 The method for manufacturing an inductor according to claim 7, wherein, in the step (c2), the metal layer is removed by wet etching using an aqueous tetramethylguanidine solution.
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JPH01108746A (en) * 1987-10-21 1989-04-26 Toshiba Corp Manufacture of semiconductor device
JP2000357774A (en) * 1999-06-15 2000-12-26 Matsushita Electric Ind Co Ltd Plurality of conductor lines, inductor element and monolithic microwave integrated circuit
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