WO2010001338A1 - Manufacture of semiconductor devices - Google Patents

Manufacture of semiconductor devices Download PDF

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Publication number
WO2010001338A1
WO2010001338A1 PCT/IB2009/052834 IB2009052834W WO2010001338A1 WO 2010001338 A1 WO2010001338 A1 WO 2010001338A1 IB 2009052834 W IB2009052834 W IB 2009052834W WO 2010001338 A1 WO2010001338 A1 WO 2010001338A1
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WIPO (PCT)
Prior art keywords
region
conductivity type
semiconductor body
electrode
channel
Prior art date
Application number
PCT/IB2009/052834
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French (fr)
Inventor
Phil Rutter
Steven Peake
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Nxp B.V.
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Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2010001338A1 publication Critical patent/WO2010001338A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the present invention relates to methods of manufacturing RESURF semiconductor devices, such as insulated-gate field-effect power transistors or diode structures.
  • the invention also relates to semiconductor devices manufactured by such methods.
  • RESURF structures achieve a high breakdown voltage by depleting a drift region via an electric field perpendicular to the direction of current flow. This allows the doping of the drift region to be much higher (for a given breakdown voltage) than that permissible in a non-RESURF structure. As a result, on-resistance may only increase linearly with breakdown voltage, rather to a power of more than two.
  • US5998833 describes field-effect power transistor configurations in which the drift region is provided in an epitaxially grown and doped semiconductor region.
  • the drift region doping concentration is graded such that it decreases in a direction from the drain region to the base region of the device.
  • the graded drain doping profile services to reduce the gate-to-drain capacitance of the device and therefore improve switching speed and reduce switching losses.
  • the present invention provides a method of manufacturing a semiconductor device including a semiconductor body having first region of a first conductivity type, and a field plate dielectrically coupled to the first region which extends into the semiconductor body adjacent to the first region, wherein the method includes the steps of:
  • a doping gradient is achievable in the drift region of a device in a versatile manner.
  • This approach is also relatively inexpensive in comparison to the use of substrates including an epitaxial layer having graded doping. Such substrates are not manufactured in bulk quantities and so the cost is significantly higher than that for a substrate including a uniformly doped epitaxial layer.
  • the same initial substrate may be used to manufacture a range of different voltage grades of device by appropriately controlling the implantation step (b). This reduces the number of substrate types required by device manufacturers to produce a given range of devices. It also gives manufacturers greater flexibility to respond quickly to customer requirements by controlling the implantation process to meet a given specification.
  • the device specification may readily be varied from one wafer to another, which may be particularly valuable for product development purposes.
  • the additional doping can be localized in the active area of the device. This makes termination of a vertical device more reliable.
  • implantation (b) comprises a plurality of implantations to different depths, wherein the implanted dose increases with the depth of the implantation.
  • the field plate is in the form of an insulated electrode provided in a trench which extends into the first region.
  • the first region may be the drift region of a Schottky diode having an electrode which forms a Schottky barrier with the drift region.
  • the device may include a pn junction formed by providing a second region of a second, opposite conductivity type over the first region, in which the trench extends through the second region into the first region.
  • a third region of the first conductivity type may be provided, such that the first, second and third regions form a drain, channel- accommodating and source region, respectively, with the channel- accommodating region separating the source and drain regions adjacent the trenched electrode, with the trenched electrode also acting as a gate.
  • a gate electrode may be provided in the trench above the field plate. In this configuration, the field plate may be connected to the gate electrode or the source electrode of the device.
  • Methods embodying the invention may include the steps of: measuring the breakdown voltage of the device; and carrying out a further implantation to adjust the doping profile in the first region and therefore the breakdown characteristics of the device.
  • the breakdown characteristics of the device may be adjusted by annealing to increase the level of out-diffusion from the substrate of the device.
  • the breakdown voltage of a device may be measured prior to metallization via probing or a test pattern.
  • An additional implantation and/or anneal step may then be carried out to tune the breakdown voltage to a desired level. More particularly, the implants carried out prior to measurement may be controlled so as to give a higher breakdown voltage than intended for the finished device.
  • the tuning process may then determine the final breakdown voltage of the device based on measurement of its properties taking into account any processing variations or tolerances. If the breakdown voltage is found to be too low, instead it may be increased by an appropriate implant of the opposite conductivity type to that of the drift region.
  • Figures 1 to 3 are cross-sectional views of a semiconductor body at successive stages in the manufacture of a semiconductor device in accordance with the method embodying the invention
  • Figures 4 to 6 are cross-sectional views of stages in the manufacture of other semiconductor devices according to methods embodying the invention
  • Figure 7 is a graph plotting the doping profile in the drift region of a device embodying the invention and a device formed in accordance with prior art.
  • Figure 8 is a graph of ionization integral against drain voltage generated by simulation of devices having doping profiles shown in Figure 7 and an equivalent substrate without any active area device features.
  • a method of forming a trench-gate RESURF transistor device embodying the invention will now be described with reference to Figures 1 to 3.
  • a cross-sectional side view of a semiconductor body 2 at a preliminary stage in the fabrication of the device is shown in Figure 1.
  • a uniformly low- doped n-type epitaxial layer 4 is provided on a more highly doped n-type substrate 6.
  • the epitaxial layer may be 5 microns thick and doped with red phosphorus at a concentration of 1x10 15 atoms/cm 3 . This may be capable of blocking around 70V and is provided with a view to forming a device having a breakdown voltage of around 50V or less.
  • a thick oxide layer 8 is defined at the edge of the active device area in a known manner to form part of the edge termination. It also forms part of a mask used to implant "deep p ring" 10 of the edge termination, which is doped to around 2x10 17 atoms/cm 3 .
  • the drift region 12 of the active area is defined by a series of n-type implants. In the embodiment depicted in Figure 2, four such implants have been carried out to form respective regions 12a to 12d.
  • the dopant dosage used in each implant increases with depth.
  • the respective dopant concentrations of regions 12d to 12a may be 1.3, 3, 5, and 7x10 16 atoms/cm 3 .
  • the number of implantations and their respective dosages may be changed as appropriate to meet particular requirements. Further processing is then carried out in a known manner to define further features in the active area of the device.
  • Figure 3 shows a trench-gate RESURF stepped-oxide transistor device embodying the invention. It includes a source region 14, channel- accommodating region 16, and a gate electrode 18 having field plate extension 18a. Gate electrode 18 is formed in a trench 20 which extends from the top major surface 2a of the semiconductor body down through the source, channel-accommodating and drain drift regions to close to the upper surface of the substrate 6 which forms the drain region of the device.
  • Electrode 9 in trench 11 is a peripheral electrode connected either to source or, in some cases depending on layout, to gate.
  • the breakdown voltage of the device may be measured and compared with the desired performance. Its characteristics may then be tuned by a further implant or annealing to introduce more doping into the drift region by out-diffusion from the substrate 6.
  • the additional implant may be of either conductivity type as appropriate. This may even allow the flexibility to change the specification of a device at short notice to meet customer demand.
  • FIG 4. An embodiment similar to that of Figure 3 is shown in Figure 4. It differs from that of Figure 3 in that a separate trenched electrode 22 is provided below the gate electrode instead of gate field plate extension 18a. Trench field plate electrode 22 may be connected to the gate or source electrode in the finished device.
  • Figure 5 shows a cross-sectional view of a Schottky barrier diode embodying the invention. It includes a vertical field plate in the form of a trenched insulated electrode 30. It is provided in a trench 20 which extends through regions 12d, 12c, 12b and into 12a of the drift region, and close to the upper surface of substrate 6.
  • substrate 6 forms the cathode region of the device.
  • Anode electrode 32 comprises a metal and/or metal suicide that forms a Schottky barrier with the drift region 12 and contacts this region at the top major surface 2a.
  • the anode electrode 32 is electrically connected to the trenched electrode 30.
  • a layer of insulating material 34 is provided between the trenched electrode and the semiconductor body 2.
  • a trench pn-diode embodying the invention is shown in Figure 6. It primarily differs from the diode configuration of Figure 5 in that a p-type anode region 40 is formed adjacent to the top major surface 2a of the device. It forms a pn-junction 42 with the drift region 12.
  • Figure 7 shows plots of doping concentration against depth measured from the top major surface of the semiconductor body in a simulation of a transistor device of the form shown in Figure 3.
  • Plot 50 relates to a device formed in a known manner using a graded epitaxial layer having dopant introduced during its growth, whilst plot 52 corresponds to a device embodying the invention, in which the doping gradient in the drift region is formed by implantation.
  • the doping levels of the initial epitaxial layer and of the four subsequent implantations are as indicated above in relation to the embodiment of Figures 1 to 3.
  • Figure 8 shows a simulated plot of ionization integral against drain voltage to illustrate the performance of an edge termination of the configuration shown in Figure 3 in a structure with no active device features (plot 60), a device embodying the invention of the form in Figure 3 (plot 62), and a device of the form shown in Figure 3 but having uniform doping at a concentration of 5.4x10 16 atoms/cm 3 in the drift region (plot 64).
  • a device embodying the invention is able to provide a more reliable and robust edge termination with a conventional edge termination configuration. This is because the implantation that creates the grading region in the active area of the device also grades the semiconductor material in the edge termination. The grading results in an average increase in resistivity and since the blocking capability increases as the resistivity increases the edge termination is capable of supporting a higher voltage. It will be appreciated that the conductivity types indicated in the embodiments discussed above may be reversed in other embodiments of the invention.
  • an accumulation-mode device embodying the invention Such a device of the p-channel type has p-type source and drain regions 14 and 12,6 and a p-type channel-accommodating region 16. In its operation, a hole accumulation channel is induced in the region 16 by the gate 18 in the on-state.
  • the present invention is particularly applicable to low and mid-level (up to around 200V) voltage RESURF and superjunction devices where epi dose tailoring may be beneficial.
  • the number of implantations will vary upon the voltage grade - higher voltage grades will have thicker epi and thus will require more implantations of increasingly higher energies.
  • the maximum energy of the implanter will eventually limit the depth at which an effective grading is achievable, but this can be compensated for by coupling the implants with a thermal drive.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

Methods of manufacturing semiconductor devices, such as insulated-gate field effect power transistors or diode structures, are provided. The devices include a semiconductor body (2) having first region (12) of a first conductivity type, and a field plate (18,22,30) dielectrically coupled to the first region and extending into the semiconductor body adjacent to the first region. The methods include the steps of providing a semiconductor body (2) which has substantially uniform doping in the first region and implanting additional dopant of thefirst conductivity type into the first region such that the dopant concentration in the first region increases with depth.

Description

DESCRIPTION
MANUFACTURE OF SEMICONDUCTOR DEVICES
The present invention relates to methods of manufacturing RESURF semiconductor devices, such as insulated-gate field-effect power transistors or diode structures. The invention also relates to semiconductor devices manufactured by such methods.
RESURF structures achieve a high breakdown voltage by depleting a drift region via an electric field perpendicular to the direction of current flow. This allows the doping of the drift region to be much higher (for a given breakdown voltage) than that permissible in a non-RESURF structure. As a result, on-resistance may only increase linearly with breakdown voltage, rather to a power of more than two.
US5998833 describes field-effect power transistor configurations in which the drift region is provided in an epitaxially grown and doped semiconductor region. The drift region doping concentration is graded such that it decreases in a direction from the drain region to the base region of the device. The graded drain doping profile services to reduce the gate-to-drain capacitance of the device and therefore improve switching speed and reduce switching losses.
The present invention provides a method of manufacturing a semiconductor device including a semiconductor body having first region of a first conductivity type, and a field plate dielectrically coupled to the first region which extends into the semiconductor body adjacent to the first region, wherein the method includes the steps of:
(a) providing a semiconductor body which has substantially uniform doping in the first region; and (b) implanting additional dopant of the first conductivity type into the first region such that the dopant concentration in the first region increases with depth.
In accordance with this method, a doping gradient is achievable in the drift region of a device in a versatile manner. This approach is also relatively inexpensive in comparison to the use of substrates including an epitaxial layer having graded doping. Such substrates are not manufactured in bulk quantities and so the cost is significantly higher than that for a substrate including a uniformly doped epitaxial layer. In accordance with methods embodying the invention, the same initial substrate may be used to manufacture a range of different voltage grades of device by appropriately controlling the implantation step (b). This reduces the number of substrate types required by device manufacturers to produce a given range of devices. It also gives manufacturers greater flexibility to respond quickly to customer requirements by controlling the implantation process to meet a given specification.
The device specification may readily be varied from one wafer to another, which may be particularly valuable for product development purposes.
As the doping grading in the drift region is created by implantation, the additional doping can be localized in the active area of the device. This makes termination of a vertical device more reliable.
In preferred embodiments, implantation (b) comprises a plurality of implantations to different depths, wherein the implanted dose increases with the depth of the implantation. Preferably, the field plate is in the form of an insulated electrode provided in a trench which extends into the first region. For example, the first region may be the drift region of a Schottky diode having an electrode which forms a Schottky barrier with the drift region.
Alternatively, the device may include a pn junction formed by providing a second region of a second, opposite conductivity type over the first region, in which the trench extends through the second region into the first region. In further embodiments, a third region of the first conductivity type may be provided, such that the first, second and third regions form a drain, channel- accommodating and source region, respectively, with the channel- accommodating region separating the source and drain regions adjacent the trenched electrode, with the trenched electrode also acting as a gate. Alternatively, a gate electrode may be provided in the trench above the field plate. In this configuration, the field plate may be connected to the gate electrode or the source electrode of the device.
Methods embodying the invention may include the steps of: measuring the breakdown voltage of the device; and carrying out a further implantation to adjust the doping profile in the first region and therefore the breakdown characteristics of the device.
Alternatively, or in addition, the breakdown characteristics of the device may be adjusted by annealing to increase the level of out-diffusion from the substrate of the device.
Thus, the breakdown voltage of a device may be measured prior to metallization via probing or a test pattern. An additional implantation and/or anneal step may then be carried out to tune the breakdown voltage to a desired level. More particularly, the implants carried out prior to measurement may be controlled so as to give a higher breakdown voltage than intended for the finished device. The tuning process may then determine the final breakdown voltage of the device based on measurement of its properties taking into account any processing variations or tolerances. If the breakdown voltage is found to be too low, instead it may be increased by an appropriate implant of the opposite conductivity type to that of the drift region.
Embodiments of the invention will now be described by way of example and with reference to the accompanying schematic drawings, wherein:
Figures 1 to 3 are cross-sectional views of a semiconductor body at successive stages in the manufacture of a semiconductor device in accordance with the method embodying the invention; Figures 4 to 6 are cross-sectional views of stages in the manufacture of other semiconductor devices according to methods embodying the invention;
Figure 7 is a graph plotting the doping profile in the drift region of a device embodying the invention and a device formed in accordance with prior art; and
Figure 8 is a graph of ionization integral against drain voltage generated by simulation of devices having doping profiles shown in Figure 7 and an equivalent substrate without any active area device features.
It should be noted that the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
A method of forming a trench-gate RESURF transistor device embodying the invention will now be described with reference to Figures 1 to 3. A cross-sectional side view of a semiconductor body 2 at a preliminary stage in the fabrication of the device is shown in Figure 1. A uniformly low- doped n-type epitaxial layer 4 is provided on a more highly doped n-type substrate 6. For example, the epitaxial layer may be 5 microns thick and doped with red phosphorus at a concentration of 1x1015 atoms/cm3. This may be capable of blocking around 70V and is provided with a view to forming a device having a breakdown voltage of around 50V or less.
A thick oxide layer 8 is defined at the edge of the active device area in a known manner to form part of the edge termination. It also forms part of a mask used to implant "deep p ring" 10 of the edge termination, which is doped to around 2x1017 atoms/cm3. The drift region 12 of the active area is defined by a series of n-type implants. In the embodiment depicted in Figure 2, four such implants have been carried out to form respective regions 12a to 12d. The dopant dosage used in each implant increases with depth. For example, the respective dopant concentrations of regions 12d to 12a may be 1.3, 3, 5, and 7x1016 atoms/cm3. The number of implantations and their respective dosages may be changed as appropriate to meet particular requirements. Further processing is then carried out in a known manner to define further features in the active area of the device.
Figure 3 shows a trench-gate RESURF stepped-oxide transistor device embodying the invention. It includes a source region 14, channel- accommodating region 16, and a gate electrode 18 having field plate extension 18a. Gate electrode 18 is formed in a trench 20 which extends from the top major surface 2a of the semiconductor body down through the source, channel-accommodating and drain drift regions to close to the upper surface of the substrate 6 which forms the drain region of the device.
Electrode 9 in trench 11 is a peripheral electrode connected either to source or, in some cases depending on layout, to gate.
At the stage shown in Figure 3, prior to metallisation of the device to form metal electrodes on its outer surfaces, the breakdown voltage of the device may be measured and compared with the desired performance. Its characteristics may then be tuned by a further implant or annealing to introduce more doping into the drift region by out-diffusion from the substrate 6. The additional implant may be of either conductivity type as appropriate. This may even allow the flexibility to change the specification of a device at short notice to meet customer demand.
An embodiment similar to that of Figure 3 is shown in Figure 4. It differs from that of Figure 3 in that a separate trenched electrode 22 is provided below the gate electrode instead of gate field plate extension 18a. Trench field plate electrode 22 may be connected to the gate or source electrode in the finished device.
Figure 5 shows a cross-sectional view of a Schottky barrier diode embodying the invention. It includes a vertical field plate in the form of a trenched insulated electrode 30. It is provided in a trench 20 which extends through regions 12d, 12c, 12b and into 12a of the drift region, and close to the upper surface of substrate 6. In this embodiment, substrate 6 forms the cathode region of the device. Anode electrode 32 comprises a metal and/or metal suicide that forms a Schottky barrier with the drift region 12 and contacts this region at the top major surface 2a. The anode electrode 32 is electrically connected to the trenched electrode 30. A layer of insulating material 34 is provided between the trenched electrode and the semiconductor body 2.
A trench pn-diode embodying the invention is shown in Figure 6. It primarily differs from the diode configuration of Figure 5 in that a p-type anode region 40 is formed adjacent to the top major surface 2a of the device. It forms a pn-junction 42 with the drift region 12.
Figure 7 shows plots of doping concentration against depth measured from the top major surface of the semiconductor body in a simulation of a transistor device of the form shown in Figure 3. Plot 50 relates to a device formed in a known manner using a graded epitaxial layer having dopant introduced during its growth, whilst plot 52 corresponds to a device embodying the invention, in which the doping gradient in the drift region is formed by implantation. The doping levels of the initial epitaxial layer and of the four subsequent implantations are as indicated above in relation to the embodiment of Figures 1 to 3. Figure 8 shows a simulated plot of ionization integral against drain voltage to illustrate the performance of an edge termination of the configuration shown in Figure 3 in a structure with no active device features (plot 60), a device embodying the invention of the form in Figure 3 (plot 62), and a device of the form shown in Figure 3 but having uniform doping at a concentration of 5.4x1016 atoms/cm3 in the drift region (plot 64). It can be seen that a device embodying the invention is able to provide a more reliable and robust edge termination with a conventional edge termination configuration. This is because the implantation that creates the grading region in the active area of the device also grades the semiconductor material in the edge termination. The grading results in an average increase in resistivity and since the blocking capability increases as the resistivity increases the edge termination is capable of supporting a higher voltage. It will be appreciated that the conductivity types indicated in the embodiments discussed above may be reversed in other embodiments of the invention.
Similar processing steps to those described in relation to Figure 3 may be used to manufacture an accumulation-mode device embodying the invention. Such a device of the p-channel type has p-type source and drain regions 14 and 12,6 and a p-type channel-accommodating region 16. In its operation, a hole accumulation channel is induced in the region 16 by the gate 18 in the on-state. The present invention is particularly applicable to low and mid-level (up to around 200V) voltage RESURF and superjunction devices where epi dose tailoring may be beneficial. The number of implantations will vary upon the voltage grade - higher voltage grades will have thicker epi and thus will require more implantations of increasingly higher energies. The maximum energy of the implanter will eventually limit the depth at which an effective grading is achievable, but this can be compensated for by coupling the implants with a thermal drive.
From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the art, and which may be used instead of or in addition to features already described herein.
Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims

1. A method of manufacturing a semiconductor device including a semiconductor body (2) having first region (12) of a first conductivity type, and a field plate (18,22,30) dielectrically coupled to the first region which extends into the semiconductor body adjacent to the first region, wherein the method includes the steps of:
(a) providing a semiconductor body (2) which has substantially uniform doping in the first region; and (b) implanting additional dopant of the first conductivity type into the first region such that the dopant concentration in the first region increases with depth.
2. A method of claim 1 wherein step (b) comprises a plurality of implantations (12a to 12d) to different depths, wherein the implanted dose increases with the depth of the implantation.
3. A method of claim 1 or claim 2 wherein the field plate (18,20) is in the form of an insulated electrode provided in a trench which extends into the first region.
4. A method of any preceding claim wherein the first region is a drift region (12) contacted by a Schottky electrode (32) which forms a Schottky barrier with the drift region.
5. A method of any of claims 1 to 3 including a step of providing a second region (16,40) of a second, opposite conductivity type over the first region (12) in the semiconductor body (2), the first and second regions defining a junction (42) therebetween, wherein the trench (20) extends through the second region into the first region.
6. A method of claim 5 including a step of providing a third region (14) of the first conductivity type, such that the first, second and third regions form a drain, channel-accommodating and source region (12,16,14), respectively, with the channel-accommodating region separating the source and drain regions adjacent the trenched electrode (18) and the trenched electrode also acting as a gate.
7. A method of claim 5 including a step of providing a third region of the first conductivity type, such that the first, second and third regions form a drain, channel-accommodating and source region (12,16,14), respectively, with the channel-accommodating region separating the source and drain regions adjacent a gate electrode (18) provided in the trench above the field plate (22).
8. A method of any preceding claim including the steps of: measuring the breakdown voltage of the device; and carrying out a further implantation to adjust the doping profile in the first region (12) and therefore the breakdown characteristics of the device.
9. A method of any preceding claim including the steps of: measuring the breakdown voltage of the device; and annealing the device to adjust the doping profile in the first region (12) and therefore the breakdown characteristics of the device.
10. A semiconductor device manufactured by a method of any preceding claim.
PCT/IB2009/052834 2008-07-01 2009-06-30 Manufacture of semiconductor devices WO2010001338A1 (en)

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DE102016110203B4 (en) * 2015-06-02 2019-11-21 Diotec Semiconductor Ag Improved Schottky diode semiconductor device and method of making the same

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EP1168455A2 (en) * 2000-06-30 2002-01-02 Kabushiki Kaisha Toshiba Power semiconductor switching element
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015038954A (en) * 2013-07-16 2015-02-26 株式会社東芝 Semiconductor device
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