WO2010000160A1 - 实现光电互斥的方法、以太网光电互斥接口装置和网络设备 - Google Patents

实现光电互斥的方法、以太网光电互斥接口装置和网络设备 Download PDF

Info

Publication number
WO2010000160A1
WO2010000160A1 PCT/CN2009/071910 CN2009071910W WO2010000160A1 WO 2010000160 A1 WO2010000160 A1 WO 2010000160A1 CN 2009071910 W CN2009071910 W CN 2009071910W WO 2010000160 A1 WO2010000160 A1 WO 2010000160A1
Authority
WO
WIPO (PCT)
Prior art keywords
physical layer
phy chip
ethernet physical
layer phy
data transmission
Prior art date
Application number
PCT/CN2009/071910
Other languages
English (en)
French (fr)
Inventor
金平
初利宝
张学锋
张力强
田伟平
魏伟
贺广涛
Original Assignee
成都市华为赛门铁克科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 成都市华为赛门铁克科技有限公司 filed Critical 成都市华为赛门铁克科技有限公司
Priority to US12/491,422 priority Critical patent/US20090323705A1/en
Publication of WO2010000160A1 publication Critical patent/WO2010000160A1/zh

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L12/4013Management of data rate on the bus
    • H04L12/40136Nodes adapting their rate to the physical link properties

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a method for implementing optical mutual exclusion, an Ethernet optical mutual exclusion interface device, and a network device. Background technique
  • Photoelectric mutual exclusion means that the board supports the optical port and the electrical port in physical form. However, only one port mode is supported during operation, that is, the optical port is not available after the electrical port is inserted, and the optical port is inserted after the optical port is inserted. unavailable.
  • the optical mutual exclusion technology is very mature in the application of Gigabit Ethenet (hereinafter referred to as GE).
  • GE's Physical Layer (hereinafter referred to as PHY) chip supports this optical mutual exclusion technology.
  • PHY Physical Layer
  • FE Fast Ethernet
  • FE PHY chips do not support optical multiplex technology, so they are also used in existing low-end products. It is GE's PHY chip to achieve optical mutual exclusion.
  • GE's optoelectronic mutual exclusion technology uses GE's Media Access Control (Gigabit Media Access Control, hereinafter referred to as GMAC) controller and PHY chip to realize optical mutual exclusion function once on the PHY chip.
  • GMAC Media Access Control
  • the PHY chip After sampling the in-position signal of the optical module, the PHY chip is configured to modify the relevant register to switch to the optical port mode, and adaptively connect with the optical port data transmission module 100BASE-FX, that is, support the optical port to perform 100 mega-op optical network data.
  • the electrical port data transmission module 10/100/lOOOOBASE-TX is adaptively connected, that is, it supports the transmission of 10 Mbps, 100 Mbps, and 1000 Mbps adaptive electrical port network data.
  • the embodiment of the present invention provides a method for implementing optical mutual exclusion, an Ethernet optical mutual exclusion interface device, and a network device, in order to reduce the cost of the 100 Mbps Ethernet optical and optical mutual interface device in the low-end and the low-end products. .
  • the embodiment of the present invention provides an Ethernet optical and optical mutual interface device, including a photoelectric channel switching module, a first Ethernet physical layer PHY chip, and a second Ethernet physical layer PHY chip, where: the photoelectric channel switching module passes the first The interface is connected to the first Ethernet physical layer PHY chip, and is connected to the second Ethernet physical layer PHY chip through the second interface, and is used for data transmission through the first Ethernet physical layer PHY chip, when the light is detected When the port data transmission module is in the bit signal, the data is transmitted through the second Ethernet physical layer PHY chip.
  • An embodiment of the present invention further provides a method for implementing optical mutual exclusion, including:
  • the switching uses the second interface to communicate with the second Ethernet physical layer PHY chip, and the data transmission is performed by the second Ethernet physical layer PHY chip.
  • the embodiment of the invention further provides a network device, which comprises the above-mentioned Ethernet photoelectric mutual exclusion interface device. Compared with the prior art, the embodiment of the present invention adopts two lower cost Ethernet networks.
  • the PHY chip and the photoelectric channel switching module realize optical mutual exclusion, instead of using the higher cost PHY chip to realize the optical mutual exclusion function of the Ethernet, thereby reducing the cost of implementing the Ethernet photoelectric mutual exclusion function in the product, and improving the resources. Utilization rate.
  • FIG. 1 is a schematic structural diagram of an Ethernet optical mutual exclusion interface device according to Embodiment 1 of the present invention
  • FIG. 2 is a flowchart of a method for implementing optical mutual exclusion by an Ethernet optical mutual exclusion interface device according to Embodiment 2 of the present invention
  • FIG. 3 is a flowchart of another method for implementing optical mutual exclusion on an Ethernet optical mutual exclusion interface device according to Embodiment 2 of the present invention.
  • FIG. 4 is a schematic structural diagram of an Ethernet optical and optical mutual exclusion interface device according to Embodiment 3 of the present invention
  • FIG. 5 is a schematic structural diagram of an FPGA according to Embodiment 3 of the present invention
  • FIG. 6 is a flowchart of a method for implementing optical mutual exclusion by an Ethernet optical mutual exclusion interface device according to Embodiment 4 of the present invention.
  • FIG. 7 is a flowchart of another method for implementing optical mutual exclusion on an Ethernet optical mutual exclusion interface device according to Embodiment 4 of the present invention.
  • FIG. 8 is a schematic structural diagram of an Ethernet optical and optical mutual exclusion interface device according to Embodiment 5 of the present invention
  • FIG. 9 is a flowchart of a method for implementing optical mutual exclusion by an Ethernet optical mutual exclusion interface device according to Embodiment 6 of the present invention
  • FIG. 10 is a schematic diagram of an optical and optical mutual exclusion interface device for implementing optical mutual exclusion according to Embodiment 6 of the present invention. Another method flow chart;
  • FIG. 11 is a schematic structural diagram of a network device according to Embodiment 7 of the present invention.
  • FIG. 12 is a schematic diagram of another structure of an Ethernet optical mutual exclusion interface device according to Embodiment 1 of the present invention
  • FIG. 13 is a flowchart of still another method for implementing optical mutual exclusion on an Ethernet optical mutual exclusion interface device according to Embodiment 2 of the present invention
  • FIG. 14 is a flowchart of still another method for implementing optical mutual exclusion by the Ethernet optical mutual exclusion interface device according to Embodiment 4 of the present invention. detailed description
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 1 is a schematic structural diagram of an Ethernet optical mutual exclusion interface device according to an embodiment of the present invention, where the device includes:
  • the photoelectric channel switching module 102 is configured to switch the data channel to the electrical port data transmission mode when the electrical interface (specifically, the electrical port data transmission module) is enabled, and send the received downlink data to the first Ethernet physical layer PHY.
  • the chip 104-1 when the optical port (specifically, the optical port data transmission module) is enabled, switches the data channel to the optical port transmission mode, and sends the received downlink data to the second Ethernet physical layer PHY chip 104-2.
  • the Ethernet optical and optical mutual interface device can be enabled by default when the power is turned on.
  • the electrical port data transmission mode is enabled. Once the device is inserted into the optical module, the optical path is established, the optical module LOSS signal is valid, and the optical channel switching module 102 collects After the signal is valid, the optical port data transmission mode is switched to ensure that the optical port is valid.
  • a first Ethernet physical layer PHY chip 104-1 for receiving a switch from the optoelectronic channel 102 downlink data, the data is sent to the electrical port data transmission module 106;
  • the second Ethernet physical layer PHY chip 104-2 is configured to receive downlink data from the optical channel switching module 102, and send the data to the optical port data transmission module 108;
  • the electrical port data transmission module 106 is configured to receive downlink data from the first Ethernet physical layer PHY chip 104-1, and send the data to a device (such as a router, a switch, etc.) connected to the electrical port data transmission module 106;
  • the optical port data transmission module 108 is configured to receive downlink data from the second Ethernet physical layer PHY chip 104-2, and send the data to a device (such as a router, a switch, etc.) connected to the optical port data transmission module 108.
  • a device such as a router, a switch, etc.
  • FIG. 12 is another schematic structural diagram of an Ethernet optical and optical mutual exclusion interface device according to an embodiment of the present invention.
  • the Ethernet optical and optical mutual exclusion interface device can be applied to a 100 Mbps Ethernet, and includes: a photoelectric channel switching module 1202. An Ethernet physical layer PHY chip 1204-1, a second Ethernet physical layer PHY chip 1204-2.
  • the photoelectric channel switching module 1202 includes a first interface 1206-1 and a second interface 1206-2, and the photoelectric channel switching module 1202 passes through the first interface 1206-1 and the first Ethernet physical layer PHY chip 1204-1.
  • connection is connected to the second Ethernet physical layer PHY chip 1204-2 through the second interface 1206-2 for data transmission through the first Ethernet physical layer PHY chip 1204-1, when the optical port data transmission module is detected At the time of the bit signal, data transmission is performed by the second Ethernet physical layer PHY chip 1204-2.
  • the photoelectric channel switching module 1202 in the photoelectric mutual exclusion interface device may be valid by the first interface 1206-1 connected to the first Ethernet physical layer PHY chip 1204-1 by default, that is, the default is An Ethernet physical layer PHY chip 1204-1 transmits the network data by means of electrical port transmission; when detecting the in-position signal of the optical port data transmission module, switching to use the second interface 1206-2 through the second Ethernet
  • the network physical layer PHY chip 1204-2 transmits the network data by means of optical port transmission.
  • the first interface 1206-1 and the second interface 1206-2 may be a Media Independent Interface (hereinafter referred to as ⁇ ).
  • the photoelectric mutual exclusion interface device may further include:
  • the electrical port data transmission module 1208-1 is connected to the first Ethernet physical layer PHY chip 1204-1 for data transmission by the first Ethernet physical layer PHY chip 1204-1 and the photoelectric channel switching module 1202;
  • the optical port data transmission module 1208-2 is connected to the second Ethernet physical layer PHY chip 1204-2 for data transmission by the second Ethernet physical layer PHY chip 1204-2 and the photoelectric channel switching module 1202.
  • the photoelectric channel switching module 1202 may be a Field Programmable Gate Array (FPGA), or a medium access control module and an analog switch module, and the like.
  • the first Ethernet physical layer ⁇ chip 1204-1 and the second Ethernet physical layer 120 chip 1204-2 may include, but are not limited to, a 100 Mbps Ethernet physical layer ⁇ chip.
  • the type of the electrical port data transmission module 1208-1 may include a 10 megabit/100 megabit adaptive electrical port data transmission module, and the type of the optical port data transmission module 1208-2 may include a 100 mega optical port data transmission module.
  • the optical mutual repulsion of the 100 Mbps Ethernet is realized by using two lower cost Ethernet physical layer ⁇ chips and the photoelectric channel switching module, instead of using a higher cost ⁇ chip (for example, GE ⁇ chip) To realize the optical mutual exclusion function of Ethernet, thereby reducing the equipment cost of implementing the optical mutual exclusion function of the Ethernet in the product, and improving the utilization of resources.
  • ⁇ chip for example, GE ⁇ chip
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • a flowchart of a method for implementing optical mutual exclusion by an Ethernet optical mutual exclusion interface device includes:
  • Step S202 When the electrical port (specifically, the electrical port data transmission module) is enabled, the photoelectric channel switching module switches the data channel to the electrical port transmission mode, and sends the received downlink data to the first Ethernet physical layer and the chip;
  • Step S204 The first Ethernet physical layer receives the chip from the photoelectric channel switching module. Downstream data, the data is sent to the electrical port data transmission module;
  • Step S206 The electrical port data transmission module receives downlink data from the first Ethernet physical layer PHY chip, and sends the data to the device connected to the electrical interface data transmission module;
  • the method may include:
  • Step S302 When the optical port (specifically, the optical port data transmission module) is enabled, the photoelectric channel switching module switches the data channel to the optical port transmission mode, and sends the received downlink data to the second Ethernet physical layer PHY chip.
  • the optical port specifically, the optical port data transmission module
  • Step S304 The second Ethernet physical layer PHY chip receives the downlink data from the photoelectric channel switching module, and sends the data to the optical port data transmission module.
  • Step S306 The optical port data transmission module receives downlink data from the second Ethernet physical layer PHY chip, and sends the data to the device connected to the optical port data transmission module.
  • FIG. 13 is a schematic diagram of still another method for implementing an optoelectronic mutual exclusion method according to the Ethernet optical mutual exclusion interface device shown in FIG. 12 in the foregoing embodiment, where the method includes:
  • Step S1302 Communicate with the first Ethernet physical layer PHY chip 1204-1 through the first interface 1206-1, and perform data transmission through the first Ethernet physical layer PHY chip 1204-1; specifically, through the first Ethernet physical layer
  • the PHY chip 1204-1 performs data transmission between the photoelectric channel switching module 1202 and the electrical port data transmission module 1208-1 connected to the first Ethernet physical layer PHY chip 1204-1;
  • Step S1304 When detecting the optical port data transmission module 1208-2 in the bit signal, the switching uses the second interface 1206-2 to communicate with the second Ethernet physical layer PHY chip 1204-2, and passes the second Ethernet physical layer PHY chip. 1204-2 for data transmission;
  • the photoelectric channel switching module connected to the second Ethernet physical layer PHY chip 1204-2 through the second Ethernet physical layer PHY chip 1204-2 Data transmission is performed between 1202 and optical port data transmission module 1208-2.
  • the transmission of data can be from photoelectric
  • the downlink data of the channel switching module 1202 to the electrical port data transmission module 1208-1 or the optical port data transmission module 1208-2 is transmitted, and then the downlink is sent by the electrical port data transmission module 1208-1 or the optical port data transmission module 1208-2.
  • the data transmission may also be the uplink data transmission from the electrical port data transmission module 1208-1 or the optical port data transmission module 1208-2 to the photoelectric channel switching module 1202, and then the uplink data is sent by the photoelectric channel switching module 1202. For example, it can be sent to the CPU connected to the photoelectric channel switching module.
  • the optical mutual exclusion interface device implementeds the optical mutual exclusion method, and implements a solution by using two lower cost Ethernet physical layer PHY chips (for example, FE PHY chip) and a photoelectric channel switching module.
  • the optoelectronic mutual exclusion of mega Ethernet replaces the use of high-end products (such as GE-enabled PHY chips) in existing products to achieve optical mutual exclusion, thereby reducing the cost of achieving optical mutual exclusion in low-end and mid-range products, and improving resources. Utilization rate.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 4 it is a schematic structural diagram of an Ethernet optical mutual exclusion interface device according to an embodiment of the present invention.
  • the device includes a Field-Programmable Gate Array (FPGA) 402 and a first Ethernet physical layer PHY chip. 404-1 and a second Ethernet physical layer PHY chip 404-2, a 10 megabit/100 megabit adaptive electrical port data transmission module 406 (eg, may be 10/100BASE-TX) and a 100 mega optical port data transmission module 408 ( For example, it can be 100BASE-FX), where:
  • FPGA Field-Programmable Gate Array
  • the field programmable gate array 402 is connected to the central processing unit CPU via a PCI line, and is connected to the first Ethernet physical layer PHY chip 404-1 and the second Ethernet physical layer PHY chip 404-2.
  • the field programmable gate array 402 For switching the data channel to the electrical port transmission mode or the optical port transmission mode according to the activation of the electrical port or the optical port; receiving downlink data from the CPU through the PCI bus; and when the electrical port is enabled, the field programmable gate array 402 The received downlink data is sent to the first Ethernet physical layer PHY chip 404-1. When the optical port is enabled, the field programmable gate array sends the received downlink data to the second Ethernet physical layer PHY chip 404- 2. Accordingly, the field programmable gate array 402 also receives the first Ethernet physical layer PHY chip 404-1 or the first through the UI interface.
  • the uplink data of the second Ethernet physical layer PHY chip 404-2 sends the uplink data to the CPU through the PCI bus; the Ethernet optical mutual exclusion interface device can be enabled by default when the power is turned on, and the electrical port data transmission mode is enabled.
  • the device is inserted into the optical module, the optical path is established, and the optical module LOSS signal is valid. After the field programmable gate array 402 collects the signal, it switches to the optical port data transmission mode to ensure that the optical port is valid.
  • the first Ethernet physical layer PHY chip 404-1 is connected to the field programmable gate array 402 in the uplink direction, and is connected to the 10 megabit/100 megabit adaptive electrical port data transmission module 406 in the downlink direction for receiving from The downlink data of the field programmable gate array 402 transmits the received downlink data to the 10 Mbps/100 Mbps adaptive electrical port data transmission module 406; correspondingly, the first Ethernet physical layer PHY chip 404-1 receives through the Mil interface. Upstream data from the 10 megabit/100 megabit adaptive electrical port data transmission module 406, transmitting the uplink data to the field programmable gate array 402;
  • the second Ethernet physical layer PHY chip 404-2 is connected to the field programmable gate array 402 in the uplink direction and to the 100 mega optical port data transmission module 408 in the downstream direction for receiving the field programmable gate array.
  • Downlink data of 402 the received downlink data is transmitted to the 100 mega optical port data transmission module 408; correspondingly, the second Ethernet physical layer PHY chip 404-2 receives the data transmission module 408 from the 100 mega optical port through the Mil interface.
  • Upstream data sending uplink data to the field programmable gate array 402;
  • the received downlink data is provided to a device connected to the module, such as a router, a switch, etc.; correspondingly, when the electrical port is enabled, the module receives uplink data from a device connected to the module, Transmitting the uplink data to the first Ethernet physical layer PHY chip 404-1;
  • FIG. 5 is a schematic structural diagram of a field programmable gate array (FPGA) 402 shown in FIG. 4.
  • FPGA field programmable gate array
  • switching between a MAC function and an analog switch control function is implemented by using an FPGA 402, where the FPGA 402 includes: An access control sub-module (MAC) 502 and a multi-channel analog switch sub-module (MUX) 504, and a medium access control sub-module (MAC) 502 is connected to the central processing unit CPU via a PCI line, through a medium independent interface ( ⁇ ) and The road analog switch submodule (MUX) 504 is connected, where:
  • MAC medium access control sub-module
  • the method includes: but is not limited to, converting downlink data from the CPU received through the PCI bus into data suitable for transmission by the Ethernet physical layer, and conversely, converting uplink data from the Ethernet physical layer received through the UI interface into Data that can be transferred to the CPU via the PCI bus.
  • a multi-channel analog switch module (MUX) 504 configured to open a channel connected to the first Ethernet physical layer PHY chip 404-1 when the in-position signal of the optical port data transmission module 408 is not detected, through the first Ethernet
  • the physical layer PHY chip 404-1 performs data transmission between the CPU and the 10 megabit/100 megabit adaptive electrical port data transmission module 406; when the in-situ signal of the 100 mega optical port data transmission module 408 is detected, the second and the second are opened.
  • the Ethernet physical layer PHY chip 404-2 is connected to the channel, and the second Ethernet physical layer PHY chip 404-2 is used for data transmission between the CPU and the 100 mega optical port data transmission module 408.
  • the electrical port data transmission module includes but is not limited to a 10 megabit/100 megabit adaptive electrical port data transmission module
  • the optical port data transmission module includes but is not limited to a 100 mega optical port data transmission module.
  • the interface of this embodiment is exemplified by ⁇ and PCI, but may not be limited to these modes.
  • First The type of the Ethernet physical layer PHY chip and the second Ethernet physical layer PHY chip may be a 100M Ethernet physical layer PHY chip or the like.
  • the photoelectric mutual exclusion interface device provided by the embodiment of the invention realizes the optical mutual exclusion of the 100M Ethernet by adopting the lower-cost Ethernet physical layer PHY chip and the photoelectric channel switching module, instead of using the costly PHY chip to realize
  • the optoelectronic mutual exclusion function of Ethernet reduces the cost of equipment that realizes opto-electronic mutual exclusion in products and improves the utilization of resources.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • FIG. 6 is a flowchart of a method for implementing optical mutual exclusion by an Ethernet optical mutual exclusion interface device according to an embodiment of the present invention.
  • the method includes:
  • Step S602 when the electrical port is enabled, the 10 megabit/100 megabit adaptive electrical port data transmission module receives uplink data from a device (such as a router, a switch, etc.) connected to the module, and sends the uplink data to the first ether.
  • Step S604 the first Ethernet physical layer PHY chip receives uplink data from the 10 megabit/100 megabit adaptive electrical port data transmission module, and sends the received uplink data to the field programmable gate array; or, the second Ethernet physics The layer PHY chip receives uplink data from the 100 mega optical port data transmission module, and sends the received uplink data to the field programmable gate array;
  • Step S606 the field programmable gate array receives uplink data from the first Ethernet physical layer PHY chip or the second Ethernet physical layer PHY chip;
  • Step S608 the field programmable gate array sends the uplink data to the CPU through the PCI bus.
  • the method includes:
  • Step S702 the field programmable gate array receives downlink data from the CPU through the PCI bus;
  • Step S704 the field programmable gate array passes the data according to the activation of the electrical port or the optical port. Switching to the electrical port transmission mode or optical port transmission mode;
  • Step S706 when the electrical port is enabled, the field programmable gate array transmits the received downlink data to the first Ethernet physical layer PHY chip through the UI interface; or, when the optical port is enabled, the field programmable gate array receives The downlink data is sent to the second Ethernet physical layer PHY chip; Step S708, when the electrical port is enabled, the first Ethernet physical layer PHY chip receives the downlink data from the field programmable gate array; or, when the optical port is enabled, The second Ethernet physical layer PHY chip receives downlink data from the field programmable gate array;
  • Step S710 when the electrical port is enabled, the first Ethernet physical layer PHY chip transmits the received downlink data to the 10 Mbps/100 Mbps adaptive electrical port data transmission module; or, when the optical port is enabled, the second Ethernet The physical layer PHY chip transmits the received downlink data to the 100 mega optical port data transmission module;
  • Step S712 when the electrical port is enabled, the 10 megabit/100 megabit adaptive electrical port data transmission module receives the downlink data from the first Ethernet physical layer PHY chip, and provides the downlink data to the device connected to the module (such as a router). Or, when the optical port is enabled, the 100 megabyte optical data transmission module receives the downlink data from the second Ethernet physical layer PHY chip, and provides the downlink data to the device connected to the module (for example, a router, Switch, etc.).
  • FIG. 14 is a flowchart of still another method for implementing optical mutual exclusion by the Ethernet optical mutual exclusion interface device according to Embodiment 4 of the present invention.
  • the method includes the following steps: Step S1402: determining whether light is present The in-position signal of the port data transmission module 1208-2, if not present, step 1404 is performed, otherwise, step 1408 is performed;
  • Step S1404 Open a channel connected to the first Ethernet physical layer PHY chip 1204-1 through the MUX 504.
  • Step S1406 Perform data transmission between the CPU and the electrical port data transmission module 1208-1 through the first Ethernet physical layer PHY chip 1204-1, and perform step 1412;
  • Step S1408 opening a channel connected to the second Ethernet physical layer PHY chip 1204-2 through the MUX 504;
  • Step S1410 data transmission between the CPU and the optical port data transmission module 1208-2 through the second Ethernet physical layer PHY chip 1204-2, step 1412;
  • Step 1412 end.
  • the photoelectric mutual exclusion interface device provided by the embodiment of the present invention implements the photoelectric mutual exclusion method, by adopting two lower cost Ethernet physical layer PHY chips (for example, FE PHY chip) and photoelectric channel switching module form a solution to realize the optical mutual exclusion of Ethernet, instead of using high-end products (such as GE-enabled PHY chips) in existing products to achieve optical mutual exclusion, thereby reducing The cost of achieving optical mutual exclusion in products has improved resource utilization.
  • two lower cost Ethernet physical layer PHY chips for example, FE PHY chip
  • photoelectric channel switching module form a solution to realize the optical mutual exclusion of Ethernet, instead of using high-end products (such as GE-enabled PHY chips) in existing products to achieve optical mutual exclusion, thereby reducing
  • the cost of achieving optical mutual exclusion in products has improved resource utilization.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • FIG. 8 is a schematic structural diagram of an Ethernet optical and optical mutual exclusion interface device according to an embodiment of the present invention.
  • the device includes a medium access control module (MAC) 802, an analog switch module 804, and a first Ethernet physical layer PHY chip 806. -1 and a second Ethernet physical layer PHY chip 806-2, a 10 megabit/100 megabit adaptive electrical port data transmission module 808 (10/100BASE-TX) and a 100 mega optical port data transmission module 810 (100BASE-FX), among them:
  • the medium access control module 802 is connected to the central processing unit CPU through a PCI line, and is connected to the analog switch module 804 through the Mil, and is configured to receive downlink data from the CPU through the PCI bus, and the downlink data is sent to the analog switch module 804 through the UI interface.
  • the media access control module 802 also receives the uplink data from the analog switch module 804 through the UI interface, and sends the received uplink data to the CPU through the PCI bus;
  • the analog switch module 804 is connected to the medium access control module 802 in the uplink direction and to the first Ethernet physical layer PHY chip 806-1 and the second Ethernet physical layer PHY chip 806-2 in the downlink direction, respectively. Receiving downlink data from the medium access control module 802 through the UI interface, and switching the data stream channel to the electrical port transmission mode or the optical port transmission mode according to the activation of the electrical port or the optical port; when the electrical port is enabled, the simulation is performed. The switch module 804 sends the received downlink data to the first Ethernet physical layer PHY chip 806-1. When the optical port is enabled, the The analog switch module 804 transmits the received downlink data to the second Ethernet physical layer PHY chip 806-2.
  • the analog switch module 804 also receives uplink data from the first Ethernet physical layer PHY chip 806-1 or the second Ethernet physical layer PHY chip 806-2 through the Mill interface, and sends the uplink data to the media interface through the UI interface.
  • the control module 802 Into the control module 802;
  • the first Ethernet physical layer PHY chip 806-1 is connected to the analog switch module 804 in the uplink direction, and is connected to the 10 megabit/100 megabit adaptive electrical port data transmission module 808 in the downlink direction for receiving the analog switch.
  • the downlink data of the module 804 transmits the received downlink data to the 10 Mbps/100 Mbps adaptive electrical port data transmission module 808; correspondingly, the first Ethernet physical layer PHY chip 806-1 receives 10 megabits/// Uplink data of the 100 Mbps adaptive electrical port data transmission module 808, the uplink data is transmitted to the analog switch module 804;
  • the second Ethernet physical layer PHY chip 806-2 is connected to the analog switch module 804 in the uplink direction, and is connected to the 100 mega optical port data transmission module 810 in the downlink direction for receiving downlink data from the analog switch module 804. Receiving the received downlink data to the 100 megabyte optical port data transmission module 810; correspondingly, the second Ethernet physical layer PHY chip 806-2 receives the uplink data from the 100 mega optical port data transmission module 810 through the Mil interface, The uplink data is transmitted to the analog switch module 804;
  • the 10 Mbps/100 Mbps adaptive electrical port data transmission module 808 is coupled to the first Ethernet physical layer PHY chip 806-1 for receiving downlink data from the first Ethernet physical layer PHY chip 806-1;
  • the received downlink data is provided to a device connected to the module, such as a router, a switch, etc.; correspondingly, when the electrical port is enabled, the module receives uplink data from a device connected to the module. Transmitting the uplink data to the first Ethernet physical layer PHY chip 806-1;
  • a 100 megabit optical port data transmission module 810 configured to be connected to the second Ethernet physical layer PHY chip 806-2 for receiving downlink data from the second Ethernet physical layer PHY chip 806-2; when the optical port is enabled Receiving the received downlink data to the device connected to the optical port, such as a router, a switch, etc.; correspondingly, when the optical port is enabled, the module receives the The uplink data of the device connected to the module, and the uplink data is transmitted to the second Ethernet physical layer
  • Ethernet photoelectric mutual exclusion interface device shown in FIG. 8 is different from the devices shown in FIG. 4 and FIG. 5 in that: media access is used.
  • Control module 802 and analog switch module 804 replace FPGA 402 in Figures 4 and 5.
  • the medium access control module (MAC) 802 is connected to the central processing unit CPU through a PCI line, and is connected to the analog switch module (MUX) 804 through a medium independent interface ( ⁇ ), wherein: the medium access control module 802 is configured to provide Different medium access layer control information; specifically, including but not limited to converting downlink data received from the CPU through the PCI bus into data suitable for transmission by the Ethernet physical layer, and vice versa, receiving Ethernet from the Mil interface
  • the uplink data of the physical layer of the network is converted into data that can be transmitted to the CPU through the PCI bus.
  • the analog switch module 804 is configured to: when the in-position signal of the 100-mega optical port data transmission module 810 is not detected, open a channel connected to the first Ethernet physical layer PHY chip 806-1, and pass the first Ethernet physical layer PHY.
  • the chip 806-1 performs data transmission between the CPU and the 10 mega Z100 Mbps adaptive electrical port data transmission module 808; when detecting the in-position signal of the 100 mega optical port data transmission module 810, the second Ethernet physical layer is opened.
  • the channel connected by the PHY chip 806-2 switches to use the second Ethernet physical layer PHY chip 806-2 for data transmission between the CPU and the 100 mega optical port data transmission module 810.
  • the electrical port data transmission module includes but is not limited to a 10 megabit/100 megabit adaptive electrical port data transmission module
  • the optical port data transmission module includes but is not limited to a 100 mega optical port data transmission module.
  • the interface of this embodiment is exemplified by Mil and PCI, but may not be limited to these modes.
  • the first Ethernet physical layer PHY chip and the second Ethernet physical layer PHY chip may be of a type including a 100 Mbps Ethernet physical layer PHY chip or the like.
  • the Ethernet photoelectric mutual exclusion interface device provided by the embodiment of the present invention adopts two low cost
  • the Ethernet physical layer PHY chip and the photoelectric channel switching module realize the photoelectric mutual exclusion of the 100M Ethernet, instead of using the higher cost PHY chip to realize the optical mutual exclusion function of the Ethernet, thereby reducing the realization of the Ethernet photoelectric in the product.
  • the cost of equipment for mutual exclusion increases resource utilization.
  • FIG. 9 is a flowchart of a method for implementing optical mutual exclusion in an Ethernet optical mutual exclusion interface device according to an embodiment of the present invention.
  • the method includes:
  • Step S902 when the electrical port is enabled, the 10 megabit/100 megabit adaptive electrical port data transmission module receives uplink data from a device (such as a router, a switch, etc.) connected to the module, and sends the uplink data to the first ether.
  • the first Ethernet physical layer PHY chip receives uplink data from the 10 Mbps/100 Mbps adaptive electrical port data transmission module, and sends the received uplink data to the analog switch module; or, The second Ethernet physical layer PHY chip receives the uplink data from the 100 mega optical port data transmission module, and sends the received uplink data to the analog switch module;
  • Step S906 the analog switch module receives uplink data from the first Ethernet physical layer PHY chip or the second Ethernet physical layer PHY chip;
  • Step S908 the analog switch module sends the uplink data to the medium access control module through the UI interface;
  • Step S910 The media access control module receives the uplink data from the analog switch module through the UI interface, and sends the received uplink data to the CPU through the PCI bus.
  • the method includes:
  • Step S1002 the medium access control module receives the downlink data through the PCI bus; in step S1004, the medium access control module transmits the downlink data to the analog switch module through the UI interface;
  • Step S1006 The analog switch module receives the media access control module through the UI interface.
  • the downlink data is switched to the electrical port transmission mode or the optical port transmission mode according to the activation of the electrical port or the optical port; when the electrical port is enabled, the analog switch module sends the received downlink data to the first ether.
  • Step S1008 when the electrical port is enabled, the first Ethernet physical layer PHY chip receives downlink data from the analog switch module; or, when the optical port is enabled, the second Ethernet physical layer PHY chip receives downlink data from the analog switch module. ;
  • Step S1010 When the electrical port is enabled, the first Ethernet physical layer PHY chip transmits the received downlink data to the 10 Mbps/100 Mbps adaptive electrical port data transmission module; or, when the optical port is enabled, the second Ethernet The physical layer PHY chip transmits the received downlink data to the 100 mega optical port data transmission module;
  • Step S1012 When the electrical port is enabled, the 10 Mbps/100 Mbps adaptive electrical port data transmission module receives the downlink data from the first Ethernet physical layer PHY chip, and provides the downlink data to the device connected to the module (such as a router). Or, when the optical port is enabled, the 100 megabyte optical data transmission module receives the downlink data from the second Ethernet physical layer PHY chip, and provides the downlink data to the device connected to the module (for example, a router, Switch, etc.).
  • the interface of this embodiment is exemplified by Mil and PCI, but may not be limited to these modes.
  • the first Ethernet physical layer PHY chip and the second Ethernet physical layer PHY chip may be of a type including a 100 Mbps Ethernet physical layer PHY chip or the like.
  • a lower cost Ethernet physical layer PHY chip (such as a 100M Ethernet physical layer PHY chip) is used as a solution to replace the costly Ethernet mutual exclusion interface solution, and the Ethernet can be reduced.
  • the cost of the optical mutual exclusion interface device increases the utilization of transmission resources.
  • FIG. 11 is a schematic structural diagram of a network device according to an embodiment of the present invention, including an Ethernet optical and optical mutual exclusion interface device 1102, which may be as described above.
  • the Ethernet optical mutual exclusion interface device in the embodiment is not described herein.
  • the types of network devices of this embodiment may include: switches, routers, digital line access multiplexers (DSLAMs), base stations or gateways, and the like.
  • DSLAMs digital line access multiplexers
  • the network device provided by the embodiment of the present invention implements the optical mutual exclusion of the 100 Mbps Ethernet by using two lower cost Ethernet physical layer PHY chips and the photoelectric channel switching module, instead of using a higher cost PHY chip.
  • the photoelectric mutual exclusion function of 100M Ethernet reduces the cost of realizing the photoelectric mutual exclusion function in the product and improves the utilization of resources.
  • the method and network device for implementing optical mutual exclusion by the Ethernet optical mutual exclusion interface device and the Ethernet optical mutual exclusion interface device according to the embodiment of the present invention are replaced by two lower-end FE PHY chips and a photoelectric channel switching module.
  • GE's PHY chip is used to realize the optical mutual exclusion function, thereby reducing the cost of realizing optical mutual exclusion and improving the utilization rate of transmission resources.
  • the steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both.
  • the software module can be placed in random access memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of In the storage medium.

Description

实现光电互斥的方法、 以太网光电互斥接口装置和网络设备
本申请要求于 2008 年 6 月 30 日提交中国专利局, 申请号为 200810068189.2 , 发明名称为 "实现光电互斥的方法、 以太网光电互斥接口 和网络设备" 的中国专利申请的优先权, 其全部内容通过引用结合在本申请 中。 技术领域
本发明涉及通信技术领域, 特别是涉及实现光电互斥的方法、 以太网 光电互斥接口装置和网络设备。 背景技术
光电互斥是指单板在物理形态上支持光口和电口这两种模式, 但是工 作时只支持一种端口模式, 即插了电口之后光口不可用, 插了光口之后电 口不可用。 光电互斥技术在千兆以太网 ( Gigabit Ethenet, 以下简称 GE ) 的应用中非常成熟, GE的物理层 ( Physical Layer , 以下简称 PHY ) 芯片 均支持该光电互斥技术。但是, 目前在很多百兆以太网即快速以太网( Fast Ethernet, 以下简称 FE ) 的应用中, FE的 PHY芯片并不支持光电互斥技 术,因此在现有的中低端产品中也使用的是 GE的 PHY芯片来实现光电互 斥功能。
在现有的光电互斥技术中, 该 GE的光电互斥技术采用 GE的媒质接 入控制 ( Gigabit Media Access Control , 以下简称 GMAC ) 控制器及 PHY 芯片来实现光电互斥功能, 一旦 PHY 芯片上采样到光模块的在位信号, 则该 PHY 芯片会配置修改相关寄存器切换成光口模式, 与光口数据传输 模块 100BASE-FX进行自适应连接, 即支持光口进行 100兆光口网络数据 的传输; 否则该 PHY 芯片会使用电口模式, 与电口数据传输模块 10/100/lOOOBASE-TX进行自适应连接, 即支持电口进行 10兆、 100兆、 1000兆自适应电口网络数据的传输。
发明人在实现本发明的过程中, 发现现有产品中, 通常采用 GMAC 控制器及支持 GE的 PHY芯片来实现光电互斥功能的解决方案来支持产品 的光电互斥, 此方案成本过高, 性价比低, 在中低端市场中缺乏竟争优势, 并且, GE的光电互斥技术中的 GMAC控制器及 PHY芯片所具备的千兆 比特的传输能力在这些产品中也没有被充分利用, 造成了资源的浪费。 发明内容
为了降低中低端产品中百兆以太网光电互斥接口装置的成本, 提高传 输资源利用率, 本发明实施例提供了一种实现光电互斥的方法、 以太网光 电互斥接口装置和网络设备。
本发明实施例提出一种以太网光电互斥接口装置, 包括光电通道切换 模块、 第一以太网物理层 PHY芯片、 第二以太网物理层 PHY芯片, 其中: 所述光电通道切换模块通过第一接口与所述第一以太网物理层 PHY 芯片连接, 通过第二接口与所述第二以太网物理层 PHY 芯片连接, 用于 通过第一以太网物理层 PHY 芯片进行数据传输, 当检测到光口数据传输 模块在位信号时, 通过第二以太网物理层 PHY芯片进行数据传输。
本发明实施例还提出一种实现光电互斥的方法, 包括:
通过第一接口与第一以太网物理层 PHY 芯片连通, 通过所述第一以 太网物理层 PHY芯片进行数据传输;
当检测到光口数据传输模块在位信号时, 切换使用第二接口与第二以 太网物理层 PHY芯片连通, 通过所述第二以太网物理层 PHY芯片进行数 据传输。
本发明实施例还提出一种网络设备, 包括上述的以太网光电互斥接口 装置。 与现有技术相比, 本发明实施例通过采用两个成本较低的以太网的
PHY芯片和光电通道切换模块来实现光电互斥,代替采用成本较高的 PHY 芯片来实现以太网的光电互斥功能, 从而降低了产品中实现以太网光电互 斥功能的成本, 提高了资源的利用率。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案, 下面将对 实施例或现有技术描述中所需要使用的附图作一筒单地介绍, 显而易见 地, 下面描述中的附图仅仅是本发明的一些实施例, 对于本领域普通技术 人员来讲, 在不付出创造性劳动性的前提下, 还可以根据这些附图获得其 他的附图。
图 1为本发明实施例一的以太网光电互斥接口装置结构示意图; 图 2为本发明实施例二的以太网光电互斥接口装置实现光电互斥的方 法流程图;
图 3为本发明实施例二的以太网光电互斥接口装置实现光电互斥的另 一方法流程图;
图 4为本发明实施例三的以太网光电互斥接口装置结构示意图; 图 5为本发明实施例三的 FPGA结构示意图;
图 6为本发明实施例四的以太网光电互斥接口装置实现光电互斥的方 法流程图;
图 7为本发明实施例四的以太网光电互斥接口装置实现光电互斥的另 一方法流程图;
图 8为本发明实施例五的以太网光电互斥接口装置结构示意图; 图 9为本发明实施例六的以太网光电互斥接口装置实现光电互斥的方 法流程图;
图 10 为本发明实施例六的以太网光电互斥接口装置实现光电互斥的 另一方法流程图;
图 11为本发明实施例七的网络设备结构示意图;
图 12为本发明实施例一的以太网光电互斥接口装置另一结构示意图; 图 13 为本发明实施例二的以太网光电互斥接口装置实现光电互斥的 又一方法流程图;
图 14 为本发明实施例四的以太网光电互斥接口装置实现光电互斥的 又一方法流程图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚, 下面将结合本 发明实施例中的附图, 对本发明实施例中的技术方案进行清楚、 完整地描 述, 显然, 所描述的实施例是本发明一部分实施例, 而不是全部的实施例。 基于本发明中的实施例, 本领域普通技术人员在没有作出创造性劳动前提 下所获得的所有其他实施例, 都属于本发明保护的范围。
实施例一:
如图 1所示, 为本发明实施例的以太网光电互斥接口装置的结构示意 图, 该装置包括:
光电通道切换模块 102 , 用于当电口(具体可以是电口数据传输模块) 启用时, 将数据通道切换到电口数据传输模式, 将接收到的下行数据发送 给第一以太网物理层 PHY芯片 104-1, 当光口 (具体可以是光口数据传输 模块) 启用时, 将数据通道切换到光口传输模式, 将接收到的下行数据发 送给第二以太网物理层 PHY芯片 104-2; 以太网光电互斥接口装置在上电 时可以默认是电口有效,启用电口数据传输模式,一旦该装置插入光模块, 光路通道建立, 光模块 LOSS信号有效, 光电通道切换模块 102采集到该 信号有效后, 就切换光口数据传输模式, 保证光口有效。
第一以太网物理层 PHY芯片 104-1 , 用于接收来自光电通道切换模块 102的下行数据, 将该数据发送给电口数据传输模块 106;
第二以太网物理层 PHY芯片 104-2 , 用于接收来自光电通道切换模块 102的下行数据, 将该数据发送给光口数据传输模块 108;
电口数据传输模块 106, 用于接收来自第一以太网物理层 PHY 芯片 104-1 的下行数据, 将该数据发送给与该电口数据传输模块 106连接的装 置 (如路由器、 交换机等) ;
光口数据传输模块 108, 用于接收来自第二以太网物理层 PHY 芯片 104-2的下行数据, 将该数据发送给与该光口数据传输模块 108连接的装 置 (如路由器、 交换机等) 。
如图 12 所示, 为本发明实施例的以太网光电互斥接口装置另一结构 示意图, 该以太网光电互斥接口装置可以应用在百兆以太网中, 包括: 光 电通道切换模块 1202、 第一以太网物理层 PHY芯片 1204-1、 第二以太网 物理层 PHY芯片 1204-2。 其中, 所述光电通道切换模块 1202包括第一接 口 1206-1和第二接口 1206-2, 所述光电通道切换模块 1202通过第一接口 1206-1与第一以太网物理层 PHY芯片 1204-1连接, 通过第二接口 1206-2 与第二以太网物理层 PHY芯片 1204-2连接, 用于通过第一以太网物理层 PHY芯片 1204-1进行数据传输, 当检测到光口数据传输模块在位信号时, 通过第二以太网物理层 PHY芯片 1204-2进行数据传输。
其中, 在具体应用中, 该光电互斥接口装置中的光电通道切换模块 1202 可以默认为与第一以太网物理层 PHY 芯片 1204-1 连接的第一接口 1206-1有效, 即默认为通过第一以太网物理层 PHY芯片 1204-1釆用电口 传输的方式对网络数据进行传输; 当检测到光口数据传输模块的在位信号 时, 则切换使用第二接口 1206-2通过第二以太网物理层 PHY芯片 1204-2 釆用光口传输的方式对网络数据进行传输。 需要说明的是, 该第一接口 1206-1 和第二接口 1206-2 可以是媒质无关接口 ( Media Independent Interface , 以下简称 ΜΠ ) 。 该光电互斥接口装置还可以包括:
电口数据传输模块 1208-1 , 与第一以太网物理层 PHY芯片 1204-1连 接, 用于通过第一以太网物理层 PHY 芯片 1204-1 与光电通道切换模块 1202进行数据传输;
光口数据传输模块 1208-2, 与第二以太网物理层 PHY芯片 1204-2连 接, 用于通过第二以太网物理层 PHY 芯片 1204-2 与光电通道切换模块 1202进行数据传输。
在本实施例中, 如图 12所示, 光电通道切换模块 1202可以为现场可 编程门阵列 ( Field Programmable Gate Array , 以下简称 FPGA ) , 或者包 括媒质接入控制模块和模拟开关模块, 等等。 第一以太网物理层 ΡΗΥ 芯 片 1204-1和第二以太网物理层 ΡΗΥ芯片 1204-2的类型可以包括但不限于 百兆以太网物理层 ΡΗΥ芯片。 电口数据传输模块 1208-1的类型可以包括 10兆 /100兆自适应电口数据传输模块, 光口数据传输模块 1208-2的类型 可以包括 100兆光口数据传输模块。
本发明实施例, 通过采用两个成本较低的以太网物理层 ΡΗΥ 芯片和 光电通道切换模块来实现百兆以太网的光电互斥, 代替采用成本较高的 ΡΗΥ芯片 (例如 GE的 ΡΗΥ芯片 ) 来实现以太网的光电互斥功能, 从而 降低了产品中实现以太网的光电互斥功能的设备成本, 提高了资源的利用 率。
实施例二:
如图 2所示, 为本发明实施例的以太网光电互斥接口装置实现光电互 斥的方法流程图, 该方法包括:
步骤 S202: 当电口 (具体可以是电口数据传输模块)启用时, 光电通 道切换模块将数据通道切换到电口传输模式, 将接收到的下行数据发送给 第一以太网物理层 ΡΗΥ芯片;
步骤 S204: 第一以太网物理层 ΡΗΥ芯片接收来自光电通道切换模块 的下行数据, 将该数据发送给电口数据传输模块;
步骤 S206: 电口数据传输模块接收来自第一以太网物理层 PHY芯片 的下行数据, 将该数据发送给与该电口数据传输模块连接的装置;
或者, 如图 3所示, 该方法可以是包括:
步骤 S302: 当光口 (具体可以是光口数据传输模块)启用时, 光电通 道切换模块将数据通道切换到光口传输模式, 将接收到的下行数据发送给 第二以太网物理层 PHY芯片;
步骤 S304: 第二以太网物理层 PHY芯片接收来自光电通道切换模块 的下行数据, 将该数据发送给光口数据传输模块;
步骤 S306: 光口数据传输模块接收来自第二以太网物理层 PHY芯片 的下行数据, 将该数据发送给与该光口数据传输模块连接的装置。
图 13为基于上述实施例中图 12所示的以太网光电互斥接口装置实现 光电互斥方法的又一方法示意图, 该方法包括:
步骤 S1302、 通过第一接口 1206-1 与第一以太网物理层 PHY 芯片 1204-1连通, 通过第一以太网物理层 PHY芯片 1204-1进行数据传输; 具体地, 通过第一以太网物理层 PHY芯片 1204-1在与第一以太网物 理层 PHY芯片 1204-1连接的光电通道切换模块 1202和电口数据传输模块 1208-1之间进行数据传输;
步骤 S1304、 当检测到光口数据传输模块 1208-2在位信号时, 切换使 用第二接口 1206-2与第二以太网物理层 PHY芯片 1204-2连通,通过第二 以太网物理层 PHY芯片 1204-2进行数据传输;
具体地, 当检测到光口数据传输模块 1208-2在位信号时,通过第二以 太网物理层 PHY芯片 1204-2在与第二以太网物理层 PHY芯片 1204-2连 接的光电通道切换模块 1202和光口数据传输模块 1208-2之间进行数据传 输。
可以理解的是, 本领域技术人员可以知道, 数据的传输可以是从光电 通道切换模块 1202 到电口数据传输模块 1208-1 或光口数据传输模块 1208-2 的下行数据的传输, 再由电口数据传输模块 1208-1 或光口数据传 输模块 1208-2发送该下行数据。 同样的,数据的传输也可以是从电口数据 传输模块 1208-1或光口数据传输模块 1208-2到光电通道切换模块 1202的 上行数据的传输, 再由光电通道切换模块 1202 发送该上行数据, 例如可 以发送给与该光电通道切换模块连接的 CPU。
本发明实施例提供的光电互斥接口装置实现光电互斥的方法, 通过采 用两个成本较低的以太网物理层 PHY芯片 (例如 FE的 PHY芯片) 和光 电通道切换模块组成解决方案来实现百兆以太网的光电互斥, 代替了现有 产品中采用高端产品(例如支持 GE的 PHY芯片 )来实现光电互斥功能, 从而降低了中低端产品中实现光电互斥的成本, 提高了资源利用率。
实施例三:
如图 4所示, 为本发明实施例的以太网光电互斥接口装置的结构示意 图,该装置包括现场可编程门阵列( Field-Programmable Gate Array , FPGA ) 402、 第一以太网物理层 PHY芯片 404-1 和第二以太网物理层 PHY芯片 404-2、 10 兆 /100 兆自适应电口数据传输模块 406 (例如, 可以是 10/100BASE-TX ) 和 100 兆光口数据传输模块 408 (例如, 可以是 100BASE-FX ) , 其中:
现场可编程门阵列 402 , 通过 PCI线与中央处理器 CPU连接, 与第一 以太网物理层 PHY芯片 404-1和第二以太网物理层 PHY芯片 404-2连接。
用于根据电口或光口的启用情况, 将数据通道切换到电口传输模式或 光口传输模式; 通过 PCI总线接收来自 CPU的下行数据; 当电口启用时, 该现场可编程门阵列 402 将接收到的下行数据发送给第一以太网物理层 PHY芯片 404-1, 当光口启用时, 该现场可编程门阵列将接收到的下行数 据发送给第二以太网物理层 PHY芯片 404-2。 相应地, 该现场可编程门阵 列 402也通过 ΜΠ接口接收来自第一以太网物理层 PHY芯片 404-1或第 二以太网物理层 PHY芯片 404-2的上行数据, 将上行数据通过 PCI总线 发送给 CPU; 以太网光电互斥接口装置在上电时可以默认是电口有效, 启 用电口数据传输模式, 一旦该装置插入光模块, 光路通道建立, 光模块 LOSS信号有效, 现场可编程门阵列 402釆集到该信号有效后, 就切换至 光口数据传输模式, 保证光口有效。
第一以太网物理层 PHY芯片 404-1 ,在上行方向上与现场可编程门阵列 402相连接, 在下行方向上与 10兆 /100兆自适应电口数据传输模块 406相 连接, 用于接收来自现场可编程门阵列 402的下行数据, 将接收到的下行数 据发送给 10 兆 /100 兆自适应电口数据传输模块 406; 相应地, 第一以太网 物理层 PHY芯片 404-1通过 Mil接口接收来自 10兆 /100兆自适应电口数据 传输模块 406的上行数据, 将上行数据传送给现场可编程门阵列 402;
第二以太网物理层 PHY芯片 404-2 , 在上行方向上与现场可编程门阵 列 402相连接, 在下行方向上与 100兆光口数据传输模块 408相连接, 用 于接收来自现场可编程门阵列 402的下行数据, 将接收到的下行数据传送 给 100 兆光口数据传输模块 408; 相应地, 第二以太网物理层 PHY芯片 404-2通过 Mil接口接收来自 100兆光口数据传输模块 408的上行数据, 将上行数据发送给现场可编程门阵列 402;
10兆 /100兆自适应电口数据传输模块 406 ,与第一以太网物理层 PHY 芯片 404-1相连接,用于接收来自第一以太网物理层 PHY芯片 404-1的下 行数据; 当该口启用时,将接收到的下行数据提供给与该模块连接的设备, 比如是路由器、 交换机等; 相应地, 当该电口启用时, 该模块接收来自与 该模块连接的装置的上行数据, 将该上行数据传送给第一以太网物理层 PHY芯片 404-1 ;
100兆光口数据传输模块 408, 与第二以太网物理层 PHY芯片 404-2 相连接, 用于接收来自第二以太网物理层 PHY芯片 404-2的下行数据; 当 该光口启用时, 将接收到的下行数据提供给与该光口连接的设备, 比如是 路由器、 交换机等; 相应地, 当该光口启用时, 该模块接收来自与该模块 连接的装置的上行数据, 将该上行数据传送给第二以太网物理层 PHY 芯 片 404-2;
图 5为图 4所示现场可编程门阵列 (FPGA ) 402的结构示意图, 如图 5所示,本实施例通过 FPGA 402实现 MAC功能和模拟开关控制功能的切 换, 所述 FPGA 402包括: 媒质接入控制子模块 (MAC ) 502和多路模拟 开关子模块 (MUX ) 504 , 媒质接入控制子模块 (MAC ) 502通过 PCI线 与中央处理器 CPU连接, 通过媒质无关接口 (ΜΠ ) 与多路模拟开关子模 块 ( MUX ) 504进行连接, 其中:
媒质接入控制子模块 (MAC ) 502 , 用于提供不同媒质接入层控制信 息;
具体的, 包括但不限于将通过 PCI总线接收的来自 CPU的下行数据 转换为适合于以太网物理层传输的数据, 反之, 也可以将通过 ΜΠ接口接 收的来自以太网物理层的上行数据转换为可通过 PCI总线传输给 CPU的 数据。
多路模拟开关模块 (MUX ) 504 , 用于当未检测到光口数据传输模块 408的在位信号时,打开与第一以太网物理层 PHY芯片 404-1连接的通道, 通过第一以太网物理层 PHY芯片 404-1在 CPU与 10兆 /100兆自适应电口 数据传输模块 406之间进行数据传输; 当检测到 100兆光口数据传输模块 408的在位信号时,打开与第二以太网物理层 PHY芯片 404-2连接的通道, 切换使用第二以太网物理层 PHY芯片 404-2在 CPU与 100兆光口数据传 输模块 408进行数据传输。
可以理解的是, 本领域技术人员可以知道, 电口数据传输模块包括但 不限于 10 兆 /100兆自适应电口数据传输模块, 光口数据传输模块包括但 不限于 100兆光口数据传输模块。
本实施例的接口以 ΜΠ和 PCI为例, 但可以不限于这些方式。 第一以 太网物理层 PHY芯片和第二以太网物理层 PHY芯片的类型可以是包括百 兆以太网物理层 PHY芯片等。
本发明实施例提供的光电互斥接口装置, 通过采用成本较低的以太网 物理层 PHY 芯片和光电通道切换模块来实现百兆以太网的光电互斥, 代 替采用成本较高的 PHY 芯片来实现以太网的光电互斥功能, 从而降低了 产品中实现光电互斥功能的设备成本, 提高了资源的利用率。
实施例四:
参见图 6 , 为本发明实施例提供的以太网光电互斥接口装置实现光电 互斥的方法流程图, 在上行方向上, 该方法包括:
步骤 S602 , 当电口启用时, 10兆 /100兆自适应电口数据传输模块接 收来自与该模块连接的设备(比如是路由器、 交换机等) 的上行数据, 将 该上行数据发送给第一以太网物理层 PHY 芯片; 或者, 当光口启用时, 100兆光口数据传输模块接收来自与该模块连接的设备(比如是路由器、 交换机等) 的上行数据, 将该上行数据传送给第二以太网物理层 PHY 芯 片;
步骤 S604 ,第一以太网物理层 PHY芯片接收来自 10兆 /100兆自适应 电口数据传输模块的上行数据, 将接收到的上行数据发送给现场可编程门 阵列; 或者, 第二以太网物理层 PHY芯片接收来自 100兆光口数据传输 模块的上行数据, 将接收到的上行数据发送给现场可编程门阵列;
步骤 S606 , 现场可编程门阵列接收来自第一以太网物理层 PHY芯片 或第二以太网物理层 PHY芯片的上行数据;
步骤 S608 , 现场可编程门阵列将上行数据通过 PCI总线发送给 CPU。 参见图 7 , 在下行方向上, 该方法包括:
步骤 S702, 现场可编程门阵列通过 PCI总线接收来自 CPU的下行数 据;
步骤 S704 , 现场可编程门阵列根据电口或光口的启用情况, 将数据通 道切换到电口传输模式或光口传输模式;
步骤 S706 , 当电口启用时,现场可编程门阵列将接收到的下行数据通 过 ΜΠ接口传输给第一以太网物理层 PHY芯片; 或者, 当光口启用时, 现场 可编程门阵列将接收到的下行数据发送给第二以太网物理层 PHY芯片; 步骤 S708 , 当电口启用时, 第一以太网物理层 PHY芯片接收来自现 场可编程门阵列的下行数据;或者,当光口启用时,第二以太网物理层 PHY 芯片接收来自现场可编程门阵列的下行数据;
步骤 S710 , 当电口启用时, 第一以太网物理层 PHY芯片将接收到的 下行数据传送给 10兆 /100兆自适应电口数据传输模块; 或者, 当光口启 用时, 第二以太网物理层 PHY芯片将接收到的下行数据传送给 100兆光 口数据传输模块;
步骤 S712 , 当电口启用时, 10兆 /100兆自适应电口数据传输模块接 收来自第一以太网物理层 PHY 芯片的下行数据, 将下行数据提供给与该 模块连接的设备(比如是路由器、 交换机等); 或者, 当光口启用时, 100 兆光口数据传输模块接收来自第二以太网物理层 PHY 芯片的下行数据, 将下行数据提供给与该模块连接的设备 (比如是路由器、 交换机等) 。
具体地, 图 14 为本发明实施例四的以太网光电互斥接口装置实现光 电互斥的又一方法流程图, 结合图 5和图 12 , 该方法包括如下步骤: 步骤 S1402、 判断是否存在光口数据传输模块 1208-2的在位信号, 若 不存在, 执行步骤 1404 , 否则, 执行步骤 1408;
步骤 S1404、通过 MUX504打开与第一以太网物理层 PHY芯片 1204-1 连接的通道;
步骤 S1406、通过第一以太网物理层 PHY芯片 1204-1在 CPU和电口 数据传输模块 1208-1之间进行数据传输, 执行步骤 1412;
步骤 S1408、通过 MUX504打开与第二以太网物理层 PHY芯片 1204-2 连接的通道; 步骤 S1410、通过第二以太网物理层 PHY芯片 1204-2 在 CPU与光口 数据传输模块 1208-2之间进行数据传输, 执行步骤 1412;
步骤 1412、 结束。
本发明实施例提供的光电互斥接口装置实现光电互斥的方法, 本发明 实施例提供的光电互斥接口装置实现光电互斥的方法, 通过采用两个成本 较低的以太网物理层 PHY芯片 (例如 FE PHY芯片 ) 和光电通道切换模 块组成解决方案来实现以太网的光电互斥, 代替了现有产品中釆用高端产 品 (例如支持 GE的 PHY芯片 ) 来实现光电互斥功能, 从而降低了产品 中实现光电互斥的成本, 提高了资源利用率。
实施例五:
如图 8所示, 为本发明实施例的以太网光电互斥接口装置的结构示意 图, 该装置包括媒质接入控制模块 (MAC ) 802、 模拟开关模块 804、 第 一以太网物理层 PHY芯片 806-1和第二以太网物理层 PHY芯片 806-2、 10兆 /100兆自适应电口数据传输模块 808 ( 10/100BASE-TX )和 100兆光 口数据传输模块 810 ( 100BASE-FX ) , 其中:
媒质接入控制模块 802 , 通过 PCI线与中央处理器 CPU连接, 通过 Mil与模拟开关模块 804连接,用于通过 PCI总线接收来自 CPU的下行数 据, 该下行数据通过 ΜΠ接口发送给模拟开关模块 804; 相应地, 该媒质 接入控制模块 802也通过 ΜΠ接口接收来自模拟开关模块 804的上行数据, 将接收到的上行数据通过 PCI总线发送给 CPU;
模拟开关模块 804, 在上行方向上与媒质接入控制模块 802相连接, 在下行方向上分别与第一以太网物理层 PHY芯片 806-1和第二以太网物理 层 PHY芯片 806-2连接, 用于通过 ΜΠ接口接收来自媒质接入控制模块 802的下行数据, 根据电口或光口的启用情况, 将数据流通道切换到电口 传输模式或光口传输模式; 当电口启用时, 该模拟开关模块 804将接收到 的下行数据发送给第一以太网物理层 PHY芯片 806-1 , 当光口启用时, 该 模拟开关模块 804将接收到的下行数据发送给第二以太网物理层 PHY芯 片 806-2。 相应地, 模拟开关模块 804也通过 Mil接口接收来自第一以太 网物理层 PHY芯片 806-1或第二以太网物理层 PHY芯片 806-2的上行数 据, 将上行数据通过 ΜΠ接口发送给媒质接入控制模块 802;
第一以太网物理层 PHY芯片 806-1 ,在上行方向上与模拟开关模块 804 相连接, 在下行方向上与 10兆 /100兆自适应电口数据传输模块 808相连 接, 用于接收来自模拟开关模块 804的下行数据, 将接收到的下行数据传 送给 10兆 /100兆自适应电口数据传输模块 808; 相应地, 第一以太网物理 层 PHY芯片 806-1通过 ΜΠ接口接收来自 10兆 /100兆自适应电口数据传 输模块 808的上行数据, 将上行数据传送给模拟开关模块 804;
第二以太网物理层 PHY芯片 806-2,在上行方向上与模拟开关模块 804 相连接, 在下行方向上与 100兆光口数据传输模块 810相连接, 用于接收 来自模拟开关模块 804的下行数据, 将接收到的下行数据传送给 100兆光 口数据传输模块 810; 相应地, 第二以太网物理层 PHY 芯片 806-2通过 Mil接口接收来自 100兆光口数据传输模块 810的上行数据 , 将上行数据 传送给模拟开关模块 804;
10兆 /100兆自适应电口数据传输模块 808,与第一以太网物理层 PHY 芯片 806-1相连接,用于接收来自第一以太网物理层 PHY芯片 806-1的下 行数据; 当该电口启用时, 将接收到的下行数据提供给与该模块连接的设 备, 比如是路由器、 交换机等; 相应地, 当该电口启用时, 该模块接收来 自与该模块连接的装置的上行数据, 将该上行数据传送给第一以太网物理 层 PHY芯片 806-1 ;
100 兆光口数据传输模块 810, 用于与第二以太网物理层 PHY 芯片 806-2相连接, 用于接收来自第二以太网物理层 PHY芯片 806-2的下行数 据; 当该光口启用时, 将接收到的下行数据提供给与该光口连接的设备, 比如是路由器、 交换机等; 相应地, 当该光口启用时, 该模块接收来自与 该模块连接的装置的上行数据, 将该上行数据传送给第二以太网物理层
PHY芯片 806-2。
具体地, 参考图 4和图 5所示的光电互斥接口装置, 图 8所示的以太 网光电互斥接口装置与图 4和图 5所示的装置的不同之处在于: 使用媒质 接入控制模块 802和模拟开关模块 804来替换图 4和图 5中的 FPGA402。 且媒质接入控制模块 ( MAC ) 802通过 PCI线与中央处理器 CPU连接, 通 过媒质无关接口 ( ΜΠ ) 与模拟开关模块( MUX ) 804进行连接, 其中: 媒质接入控制模块 802 , 用于提供不同媒质接入层控制信息; 具体的, 包括但不限于将通过 PCI总线接收的来自 CPU的下行数据转换 为适合于以太网物理层传输的数据, 反之, 也可以将通过 Mil接口接收的来 自以太网物理层的上行数据转换为可通过 PCI总线传输给 CPU的数据。
模拟开关模块 804, 用于当未检测到 100兆光口数据传输模块 810的 在位信号时, 打开与第一以太网物理层 PHY芯片 806-1连接的通道,通过 第一以太网物理层 PHY芯片 806-1在 CPU与 10兆 Z100兆自适应电口数据 传输模块 808之间进行数据传输; 当检测到 100兆光口数据传输模块 810 的在位信号时, 打开与第二以太网物理层 PHY芯片 806-2连接的通道,切 换使用第二以太网物理层 PHY芯片 806-2在 CPU与 100兆光口数据传输 模块 810之间进行数据传输。
可以理解的是, 本领域技术人员可以知道, 电口数据传输模块包括但 不限于 10 兆 /100兆自适应电口数据传输模块, 光口数据传输模块包括但 不限于 100兆光口数据传输模块。
其它部分的结构请参考上述图 4和图 5所示的实施例,在此不再赘述。 本实施例的接口以 Mil和 PCI为例, 但可以不限于这些方式。 第一以 太网物理层 PHY芯片和第二以太网物理层 PHY芯片的类型可以是包括百 兆以太网物理层 PHY芯片等。
本发明实施例提供的以太网光电互斥接口装置, 通过采用两个成本较低 的以太网物理层 PHY 芯片和光电通道切换模块来实现百兆以太网的光电互 斥, 代替采用成本较高的 PHY芯片来实现以太网的光电互斥功能, 从而降低 了产品中实现以太网光电互斥功能的设备成本, 提高了资源的利用率。
实施例六:
参见图 9 , 为本发明实施例提供的在以太网光电互斥接口装置实现光 电互斥的方法的流程图, 在上行方向上, 该方法包括:
步骤 S902, 当电口启用时, 10兆 /100兆自适应电口数据传输模块接 收来自与该模块连接的设备(比如是路由器、 交换机等) 的上行数据, 将 该上行数据发送给第一以太网物理层 PHY 芯片; 或者, 当光口启用时, 100 兆光口数据传输模块接收来自与该模块连接的设备(比如是路由器、 交 换机等) 的上行数据, 将该上行数据传送给第二以太网物理层 PHY芯片; 步骤 S904 ,第一以太网物理层 PHY芯片接收来自 10兆 /100兆自适应 电口数据传输模块的上行数据, 将接收到的上行数据发送给模拟开关模 块; 或者, 第二以太网物理层 PHY芯片接收来自 100兆光口数据传输模 块的上行数据, 将接收到的上行数据发送给模拟开关模块;
步骤 S906 , 模拟开关模块接收来自第一以太网物理层 PHY芯片或第 二以太网物理层 PHY芯片的上行数据;
步骤 S908 , 模拟开关模块将上行数据通过 ΜΠ接口发送给媒质接入 控制模块;
步骤 S910 , 媒质接入控制模块通过 ΜΠ接口接收来自模拟开关模块 的上行数据, 将接收到的上行数据通过 PCI总线发送给 CPU。
参见图 10 , 在下行方向上, 该方法包括:
步骤 S1002 , 媒质接入控制模块通过 PCI总线接收下行数据; 步骤 S1004, 媒质接入控制模块将该下行数据通过 ΜΠ接口传送给模 拟开关模块;
步骤 S1006 , 模拟开关模块通过 ΜΠ接口接收来自媒质接入控制模块 的下行数据, 根据电口或光口的启用情况, 将数据通道切换到电口传输模 式或光口传输模式; 当电口启用时, 该模拟开关模块将接收到的下行数据 发送给第一以太网物理层 PHY 芯片; 或者, 当光口启用时, 该模拟开关 模块将接收到的下行数据发送给第二以太网物理层 PHY芯片;
步骤 S1008 , 当电口启用时, 第一以太网物理层 PHY芯片接收来自模 拟开关模块的下行数据; 或者, 当光口启用时, 第二以太网物理层 PHY 芯片接收来自模拟开关模块的下行数据;
步骤 S1010 , 当电口启用时, 第一以太网物理层 PHY芯片将接收到的 下行数据传送给 10兆 /100兆自适应电口数据传输模块; 或者, 当光口启 用时, 第二以太网物理层 PHY芯片将接收到的下行数据传送给 100兆光 口数据传输模块;
步骤 S1012 , 当电口启用时, 10兆 /100兆自适应电口数据传输模块接 收来自第一以太网物理层 PHY 芯片的下行数据, 将下行数据提供给与该 模块连接的设备(比如是路由器、 交换机等); 或者, 当光口启用时, 100 兆光口数据传输模块接收来自第二以太网物理层 PHY 芯片的下行数据, 将下行数据提供给与该模块连接的设备 (比如是路由器、 交换机等) 。
本实施例的接口以 Mil和 PCI为例, 但可以不限于这些方式。 第一以 太网物理层 PHY芯片和第二以太网物理层 PHY芯片的类型可以是包括百 兆以太网物理层 PHY芯片等。
通过本发明实施例, 以两个成本较低的以太网物理层 PHY 芯片 (如 百兆以太网物理层 PHY 芯片 ) 组成解决方案代替成本较高的以太网互斥 接口解决方案, 可以降低以太网光电互斥接口装置的成本, 提高传输资源 利用率。
实施例七:
参见图 11 , 为本发明实施例提供的网络设备结构示意图, 包括以太网 光电互斥接口装置 1102 , 该以太网光电互斥接口装置 1102可以是如前述 实施例所述以太网光电互斥接口装置, 在此不再赘述。
本实施例的网络设备的类型可以包括: 交换机、 路由器、 数字线路接 入复用器 (DSLAM ) 、 基站或网关等。
本发明实施例提供的网络设备, 通过釆用两个成本较低的以太网物理 层 PHY 芯片和光电通道切换模块来实现百兆以太网的光电互斥, 代替采 用成本较高的 PHY 芯片来实现百兆以太网的光电互斥功能, 从而降低了 产品中实现光电互斥功能的成本, 提高了资源的利用率。
综上可见, 通过本发明实施例的以太网光电互斥接口装置、 以太网光 电互斥接口装置实现光电互斥的方法和网络设备, 采用两个较低端的 FE PHY芯片和光电通道切换模块替换现有产品中使用 GE的 PHY芯片来实 现光电互斥功能,从而降低实现光电互斥的成本,提高传输资源的利用率。
专业人员还可以意识到, 结合本文中所公开的实施例描述的各示例的 单元及算法步骤, 能够以电子硬件、 计算机软件或者二者的结合来实现, 为了清楚地说明硬件和软件的可互换性, 在上述说明中已经按照功能一般 性地描述了各示例的组成及步骤。 这些功能究竟以硬件还是软件方式来执 行, 取决于技术方案的特定应用和设计约束条件。 专业技术人员可以对每 个特定的应用来使用不同方法来实现所描述的功能, 但是这种实现不应认 为超出本发明的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以用硬件、 处 理器执行的软件模块, 或者二者的结合来实施。 软件模块可以置于随机存 储器 (RAM ) 、 内存、 只读存储器 (ROM ) 、 电可编程 ROM、 电可擦除 可编程 ROM、 寄存器、 硬盘、 可移动磁盘、 CD-ROM、 或任意其它形式 的存储介质中。
以上所述仅是本发明的具体实施方式, 应当指出, 对于本技术领域的 普通技术人员来说, 在不脱离本发明原理的前提下, 还可以做出若干改进 和润饰, 这些改进和润饰也应视为本发明的保护范围。

Claims

权 利 要 求 书
1、 一种以太网光电互斥接口装置, 其特征在于, 包括光电通道切换 模块、 第一以太网物理层 PHY芯片、 第二以太网物理层 PHY芯片, 其中: 所述光电通道切换模块通过第一接口与所述第一以太网物理层 PHY 芯片连接, 通过第二接口与所述第二以太网物理层 PHY 芯片连接, 用于 通过第一以太网物理层 PHY 芯片进行数据传输, 当检测到光口数据传输 模块在位信号时 , 通过第二以太网物理层 PHY芯片进行数据传输。
2、 如权利要求 1 所述的以太网光电互斥接口装置, 其特征在于, 还 包括:
电口数据传输模块, 与所述第一以太网物理层 PHY 芯片连接, 用于 通过所述第一以太网物理层 PHY芯片与光电通道切换模块进行数据传输; 光口数据传输模块, 与所述第二以太网物理层 PHY 芯片连接, 用于 通过所述第二以太网物理层 PHY芯片与光电通道切换模块进行数据传输。
3、 如权利要求 2 所述的以太网光电互斥接口装置, 其特征在于, 所 述光电通道切换模块包括媒质接入控制子模块和模拟开关子模块, 其中: 媒质接入控制子模块, 分别与中央处理器 CPU 和模拟开关子模块连 接, 用于提供不同媒质接入层控制信息;
模拟开关子模块, 用于当未检测到所述光口数据传输模块的在位信号 时, 打开与所述第一以太网物理层 PHY 芯片连接的通道, 通过第一以太 网物理层 PHY芯片在 CPU与所述电口数据传输模块之间进行数据传输; 当检测到所述光口数据传输模块的在位信号时, 打开与所述第二以太网物 理层 PHY芯片连接的通道,切换使用第二以太网物理层 PHY芯片在 CPU 与所述光口数据传输模块之间进行数据传输。
4、 如权利要求 1 所述的以太网光电互斥接口装置, 其特征在于, 所 述光电通道切换模块为现场可编程门阵列。
5、 如权利要求 1 所述的以太网光电互斥接口装置, 其特征在于, 所 述第一以太网物理层 PHY芯片和第二以太网物理层 PHY芯片包括百兆以 太网物理层 PHY芯片。
6、 如权利要求 2 所述的以太网光电互斥接口装置, 其特征在于, 所 述电口数据传输模块的类型包括: 10兆 /100兆自适应电口数据传输模块; 所述光口数据传输模块的类型包括: 100兆光口数据传输模块。
7、 一种实现光电互斥的方法, 其特征在于, 包括:
通过第一接口与第一以太网物理层 PHY 芯片连通, 通过所述第一以 太网物理层 PHY芯片进行数据传输;
当检测到光口数据传输模块在位信号时, 切换使用第二接口与第二以 太网物理层 PHY芯片连通, 通过所述第二以太网物理层 PHY芯片进行数 据传输。
8、 如权利要求 7所述的实现光电互斥的方法, 其特征在于, 所述通过第一接口与第一以太网物理层 PHY 芯片连通, 通过所述第 一以太网物理层 PHY 芯片进行数据传输包括: 通过所述第一以太网物理 层 PHY芯片在与所述第一以太网物理层 PHY芯片连接的光电通道切换模 块和电口数据传输模块之间进行数据传输;
所述当检测到光口数据传输模块在位信号时, 切换使用第二接口与第 二以太网物理层 PHY芯片连通, 通过所述第二以太网物理层 PHY芯片进 行数据传输包括: 当检测到所述光口数据传输模块在位信号时, 通过所述 第二以太网物理层 PHY芯片在与所述第二以太网物理层 PHY芯片连接的 光电通道切换模块和光口数据传输模块之间进行数据传输。
9、 一种网络设备, 其特征在于, 包括如权利要求 1 至 6 中任一项所 述的以太网光电互斥接口装置。
10、 如权利要求 9所述的网络设备, 其特征在于, 所述网絡设备的类 型包括:
交换机、 路由器、 数字线路接入复用器 (DSLAM ) 、 基站或网关。
PCT/CN2009/071910 2008-06-30 2009-05-21 实现光电互斥的方法、以太网光电互斥接口装置和网络设备 WO2010000160A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/491,422 US20090323705A1 (en) 2008-06-30 2009-06-25 Method for implementing photoelectric mutex, ethernet photoelectric mutex interface device and network equipment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200810068189A CN101621328A (zh) 2008-06-30 2008-06-30 实现光电互斥的方法、以太网光电互斥接口和网络设备
CN200810068189.2 2008-06-30

Publications (1)

Publication Number Publication Date
WO2010000160A1 true WO2010000160A1 (zh) 2010-01-07

Family

ID=41465484

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2009/071910 WO2010000160A1 (zh) 2008-06-30 2009-05-21 实现光电互斥的方法、以太网光电互斥接口装置和网络设备

Country Status (2)

Country Link
CN (1) CN101621328A (zh)
WO (1) WO2010000160A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE202011108919U1 (de) 2011-12-09 2012-01-30 Osram Ag Beleuchtungseinrichtung
CN106603310A (zh) * 2017-01-12 2017-04-26 深圳市恒扬数据股份有限公司 一种网络管理接口系统及网络分流器
CN109600457A (zh) * 2019-01-28 2019-04-09 伟乐视讯科技股份有限公司 一种多至一映射的phy-mac接口控制装置及方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104410505A (zh) * 2014-11-26 2015-03-11 北京中科德能科技有限公司 一种以太网光电介质转换装置
CN105553789A (zh) * 2015-11-30 2016-05-04 国家电网公司 一种ptn分组传送设备及其自动切换光电接口的方法
CN106656518A (zh) * 2016-11-11 2017-05-10 北京百卓网络技术有限公司 万兆交换机
CN106549713A (zh) * 2016-12-07 2017-03-29 深圳市飞鸿光电子有限公司 一种基于olt设备的sfp接口供电的方法及olt设备
CN111783374A (zh) * 2020-06-30 2020-10-16 Oppo广东移动通信有限公司 一种芯片和终端
CN112737794B (zh) * 2020-12-22 2024-02-09 广州市高科通信技术股份有限公司 光口与电口自适应连接装置
CN113193983B (zh) * 2021-03-31 2022-04-01 新华三信息安全技术有限公司 一种网络通信设备及其切换拓扑连接模式的方法
CN113242480B (zh) * 2021-06-24 2022-06-21 烽火通信科技股份有限公司 一种光电复用的装置和方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003056775A1 (fr) * 2001-12-30 2003-07-10 Legend (Beijing) Limited. Moyen et procede de commande permettant d'adapter differents supports de liaison de transmission de reseau a une couche physique
CN1534932A (zh) * 2003-03-27 2004-10-06 华为技术有限公司 支持多千兆以太网端口光电复用的方法
CN1725762A (zh) * 2004-07-23 2006-01-25 杭州华为三康技术有限公司 以太网光电接口复用的一种实现方法
CN101136795A (zh) * 2006-12-26 2008-03-05 中兴通讯股份有限公司 一种基于网络处理器的通讯协议监测系统及方法
CN101141451A (zh) * 2007-10-26 2008-03-12 华中科技大学 数控系统通信接口、数控系统及数据接收和发送方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003056775A1 (fr) * 2001-12-30 2003-07-10 Legend (Beijing) Limited. Moyen et procede de commande permettant d'adapter differents supports de liaison de transmission de reseau a une couche physique
CN1534932A (zh) * 2003-03-27 2004-10-06 华为技术有限公司 支持多千兆以太网端口光电复用的方法
CN1725762A (zh) * 2004-07-23 2006-01-25 杭州华为三康技术有限公司 以太网光电接口复用的一种实现方法
CN101136795A (zh) * 2006-12-26 2008-03-05 中兴通讯股份有限公司 一种基于网络处理器的通讯协议监测系统及方法
CN101141451A (zh) * 2007-10-26 2008-03-12 华中科技大学 数控系统通信接口、数控系统及数据接收和发送方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE202011108919U1 (de) 2011-12-09 2012-01-30 Osram Ag Beleuchtungseinrichtung
CN106603310A (zh) * 2017-01-12 2017-04-26 深圳市恒扬数据股份有限公司 一种网络管理接口系统及网络分流器
CN106603310B (zh) * 2017-01-12 2023-07-04 深圳市恒扬数据股份有限公司 一种网络管理接口系统及网络分流器
CN109600457A (zh) * 2019-01-28 2019-04-09 伟乐视讯科技股份有限公司 一种多至一映射的phy-mac接口控制装置及方法
CN109600457B (zh) * 2019-01-28 2022-06-03 伟乐视讯科技股份有限公司 一种多至一映射的phy-mac接口控制装置及方法

Also Published As

Publication number Publication date
CN101621328A (zh) 2010-01-06

Similar Documents

Publication Publication Date Title
WO2010000160A1 (zh) 实现光电互斥的方法、以太网光电互斥接口装置和网络设备
CN108206761B (zh) 用于设置双端口交换机的链路速度的方法
US20090323705A1 (en) Method for implementing photoelectric mutex, ethernet photoelectric mutex interface device and network equipment
RU2533291C2 (ru) Способ, устройство и система для выполнения мультимедийной услуги в беспроводной локальной сети
WO2008071131A1 (fr) Procédé de transmission de données cpri (common public radio interface), et procédés et systèmes correspondants
EP2556693A1 (en) Inter-working of efm-oam and cfm-oam for mobile backhaul networks
WO2005083932A1 (fr) Equipement reseau destine a l'acces a bande large et procede correspondant
Checko Cloud radio access network architecture. Towards 5G mobile networks
EP3614626A1 (en) Potn system, potn intercommunication module, and packet intercommunication method
CN101883117B (zh) 接口业务集中处理方法和系统
CN101800702A (zh) 一种实现接口链路切换的方法和网络设备
WO2014169557A1 (zh) 接口切换方法和装置
US9654559B2 (en) Method, apparatus, and system for exchanging data of edge area user on cloud radio access network
CN105704068B (zh) 一种业务混合集中处理方法和装置
WO2015021594A1 (zh) 一种无线接入的方法、装置和系统
WO2007079241A2 (en) Method and apparatus for enabling transport of ethernet data over a serial digital interface transport service
WO2022218179A1 (zh) 动态带宽扩容方法、装置及系统
CN102811149B (zh) 一种用于视频系统中的双卡前端设备及控制方法、系统
KR101958374B1 (ko) 네트워크 내의 지연을 정확하게 추정하는 서비스들, 시스템들 및 방법들
WO2012065419A1 (zh) 一种实现基站级联的方法、系统和级联处理逻辑子系统
Bartelt et al. Fronthaul for a flexible centralization in cloud radio access networks
CN101141676B (zh) 一种防止网络广播风暴的方法
KR100731180B1 (ko) 이동통신 시스템에서 단말기의 물리 계층 제어 방법 및 그장치
KR100655734B1 (ko) 이동통신 기지국 시스템의 물리계층 인터페이스 처리 방법 및 그 장치
CN101083592B (zh) 基站系统在链型拓扑结构中带宽共享方法和基站收发信台

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09771930

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09771930

Country of ref document: EP

Kind code of ref document: A1