WO2009140963A1

WO2009140963A1 - A display device

Info

Publication number: WO2009140963A1
Application number: PCT/DK2008/000192
Authority: WO
Inventors: Ole Henrik Moller; Christian Zilstorff
Original assignee: Mobile Internet Technology A/S
Priority date: 2008-05-22
Filing date: 2008-05-22
Publication date: 2009-11-26
Also published as: EP2351007A4; EP2351007A1

Abstract

A display system with a display control circuit (105, 200), one or more display panels (104) and configuration circuitry (106) for controlling the display control circuitry (105) and display panels (1 04). The display control circuitry (105, 200) receives and proc-ess digital video signals via a serial interface (201) e.g. Mobile Display Digital Inter-face Standard, MDDI. The digital video signals is unpacked in the pre-processor (202), stored in the frame buffer (203) and transmitted to the display panel via the postprocessor (204) and serial interface (201), the pre-processor (202), frame buffer (203) and postprocessor (204) is controlled by the central control (205). The display system further provides a clock signal for driving the display panels, which phase is adjusted according to an internal clock signal. The packet structure of MDDI is also disclosed.

Description

A DISPLAY DEVICE

FIELD OF THE INVENTION

The invention relates to a display device. More particular the invention relates to a display device having one or more display panels and a display control circuitry being adapted for receiving and processing a digital video input signal and for supplying a video output signal for driving the display panels.

DESCRIPTION OF THE PRIOR ART

The explosion of high quality data presentation has driven the need to establish interfaces that can transfer data at high rates, such that data quality is not degraded or impaired. One such interface is the Mobile Display Digital Interface (MDDI).

The Mobile Display Digital Interface (MDDI) is a cost-effective, low-power consumption, transfer mechanism that enables very high speed data transfer over a short-range communication link between a host and a client. MDDI type I requires a minimum of just four wires plus power and ground for bidirectional data transfer. The MDDI type IV may deliver a maximum bandwidth of up to 3.2 Gbits per second.

In one application, MDDI increases reliability and decreases power consumption in clamshell phones by significantly reducing the number of wires that run across a handset's hinge to interconnect the digital baseband controller with an LCD display. This reduction of wires also allows handset manufactures to lower development costs by simplifying clamshell or sliding handset designs.

MDDI is a serial transfer protocol, and, as such, data received in parallel for transmission over an MDDI link has to be serialized.

Typical MDDI interconnections include MDDI controllers connected through an MDDI link, with one controller being the MDDI host controller and the other controller being the MDDI client controller. In linking a base band processor to a device, such as an LCD display, an interface is also generally used to relay commands from the processor to the device. LCD controllers having an MDDI client interface are available on the market from suppliers such as Toshiba (TC358720XBG), California Micro Devices (CM5100), Sharp (LR38869), Samsung (S6D0142), and Seiko Epson (S1 D13751 ). More recently, the Mobile Industry Processor Interface (MIPI) Alliance have defined the MIPI Display Serial Interface (DSI) standard. The MIPI Display Serial Interface may be supported by physical layer devices being compliant to the MIPI Alliance Standard D-PHY. Toshiba (TC358730XBG) is supplying to the market a LCD controller supporting the high speed serial MIPI DSI base band for command and video data. These controllers further have an internal frame buffer and a 18- or 24-bit parallel RGB pixel data LCD interface.

Most LCD-controllers for mobile phones have a synchronous parallel RGB pixel interface with horizontal and vertical synchronization signals (HSYNC and VSYNC) intended for the main LCD, and an asynchronous microprocessor-style RGB pixel/sub-pixel and command interface without horizontal and vertical synchronization signals intended for a smaller sub-LCD, or both in the case of a clamshell mobile phone with main LCD on the inside and sub-LCD on the outside. The pixel/sub-pixel interface may transfer pixel information in 1-3 cycles, in the case of 3 cycles per pixel this would normally be one colour per cycle, typically in the order red, green, blue, also known as RGB sub-pixels.

However, microdisplay panels have emerged on the market, such as MicroEmissive Displays' P-OLED microdisplays, which microdisplay panels have a synchronous 8-bit serial RGB sub-pixel data interface.

What is needed therefore is a system for receiving a digital video input signal and for supplying a video output signal in a format suited for a microdisplay interface.

SUMMARY OF THE INVENTION

According to the present invention there is provided a display system comprising: one or more display panels; display control circuitry; and configuration circuitry for configuration of the display control circuitry and the display panel(s), wherein the display control circuitry is adapted for receiving and processing digital video input signals and for supplying digital video output signals as input for the display panel(s).

According to an embodiment of the invention the display panel(s) is/are microdisplay panel(s). According to one embodiment of the invention, the display device has one and only one display panel, but in another, preferred embodiment, the display device has two display panels, a first and a second display panel.

It is within a preferred embodiment of the invention that the display control circuitry is adapted for serially transmitting sub-pixel colour data via a sub-pixel data-bus being part of a sub-pixel interface for feeding or driving the display panel(s). Here, the sub-pixel colour data may be serially transmitted in a predetermined order, and the predetermined order of colours may be red followed by green followed by blue, RGB. It is preferred that the sub-pixel data-bus has a bit width equal to the bit width of a sub-pixel. It is within embodiments of the invention that a sub-pixel has a bit width of 6, 7 or 8 bits. It is preferred that the display control circuitry is adapted for transmitting a sub-pixel clock signal being part of the sub-pixel interface for the driving of the display panel(s). It is also preferred that the display control circuitry is adapted for transmitting a horizontal sync pulse, HSYNC, and a vertical sync pulse, VSYNC, as part of the sub-pixel interface for the driving of the display panel(s).

According to an embodiment of the invention the display system comprises at least two display panels, with the driving signals being fed in parallel from the display control circuitry to each of the display panels.

It is within one or more embodiments of the invention that the display system further comprises buffer circuitry for transferring data for driving the display panel(s) from the display control circuitry to the display panel(s). Here, the buffer circuitry may comprise up to 12 drivers for each display panel.

The present invention also covers one or more embodiments wherein the display control circuitry is adapted for receiving and processing a digital video input signal being received via packet-based serial data communication. It is also within one or more embodiments of the invention that the display control circuitry is adapted for receiving and processing a digital video input signal being received by use of differential signalling. Here, the differential signalling is performed via a receiving communication interface comprising at least one twisted conductor pairs for receiving differential data. Preferably, the receiving communications interface further comprises a twisted conductor pair for communicating clock or strobe signals, and the receiving communications interface may further comprise two conductors for power and ground.

According to an embodiment of the invention, the display control circuitry is adapted for receiving and processing a digital video input signal presented in accordance with the Display Serial Interface Standard, DSI. It is also within an embodiment of the invention that the display control circuitry is compliant with the MIPI Alliance Standard D-PHY.

According to another embodiment of the invention, the display control circuitry is adapted for receiving and processing a digital video input signal presented in accordance with the Mobile Display Digital Interface Standard, MDDI. The display system may comprise a cable connector, which includes power and ground.

It is within one or more embodiments of the invention that the display control circuitry has serial interface receiving circuitry, pre-processing circuitry, frame buffer circuitry, and post- processor circuitry. Here, the serial interface receiving circuitry may be adapted for unpacking embedded video data fields from video stream packets received as part of a serial digital video input signal and for forwarding the video data fields to the preprocessing circuitry, and the pre-processing circuitry may be adapted for writing pixel data into the frame buffer circuitry based on the received video data fields. Here, the display control circuitry may be adapted for receiving and processing the digital video input signal presented in accordance with the Mobile Display Digital Interface Standard, MDDI, and the serial interface receiving circuitry may comprise MDDI client circuitry. It is preferred that the post-processor circuitry is adapted for reading pixel data from the frame buffer circuitry, dividing the pixel data into sub-pixel data and for forwarding the sub-pixel data via a sub-pixel interface for driving the display panel(s). The post-processor circuitry may be adapted for forwarding the sub-pixel data in a predetermined order of colours for each pixel, where the predetermined order of colours may be red followed by green followed by blue. The post-processor circuitry may also be adapted for generating and determining the timing of a horizontal sync pulse, HSYNC, and a vertical sync pulse, VSYNC, which are both forwarded as part of the sub-pixel interface for the driving of the display panel(s). It is within one or more embodiments of the invention that the display control circuitry further comprises central control circuitry for accessing programmable registers of the circuitries of the display control circuitry via a serial control interface and/or via a MDDI control interface to the MDDI client circuitry. It is also within one or more embodiments of the invention that the display control circuitry further comprises clock circuitry for generating one or more clock signals for the circuitries of the display control circuitry and/or display system.

According to an embodiment of the invention wherein the display control circuitry comprises post-processor circuitry, the post-processor circuitry may be adapted for generating and forwarding a sub-pixel clock corresponding to the sub-pixel data as part of the sub-pixel interface for the driving of the display panel(s).

It is also an embodiment of the invention that for systems wherein the display control circuitry comprises post-processor circuitry, the post-processor circuitry may be adapted for generating an asynchronous write pulse signal corresponding to the sub-pixel data. Here, the asynchronous write pulse signal may be generated based on a system clock and comprise successive first signals sets, each first signal set having three successive first active write pulse periods followed by a non-active dummy period having a period length corresponding to the length of an active write pulse period. It is preferred that each first active write pulse has a period length corresponding to 2N system clock periods, where N is an integer number, and the non-active dummy period has a period length of 2N. The display system or the display control circuitry may further comprise pulse generating circuitry being adapted for generating successive second signal sets based on the system clock, each second signal set comprising four second active write or clock pulse periods, corresponding to the sub-pixel data. Here, it is preferred that each second active write pulse or clock pulse has a period length corresponding to 2N system clock periods, where N is an integer number. According to an embodiment of the invention, the display system may further comprise phase circuitry for comparing the phase of the first active write pulses with the phase of the second active write or clock pulses, and circuitry for changing the phase of the second active write or clock pulses if the detected phase difference is larger than a predetermined maximum phase value. Here, the display system or display control circuitry may be adapted for forwarding a sub-pixel clock signal corresponding to the second signal sets for the driving of the display panel(s). It is within a preferred embodiment that the configuration control circuitry is adapted for generating a change phase signal when the detected phase difference is larger than the predetermined maximum phase value. The value of N may be set to one, but the value of N may also be an equal number, and it is preferred that the value of N is 2.

The present invention also covers embodiments, wherein the display control circuitry is adapted for generating successive first signal sets based on a system clock, each set of first signal sets comprising three successive first active write pulse periods with each first active write pulse period having a period length corresponding to 2N system clock periods where N is an integer number, each first signal set further having a non-active dummy period having a period length corresponding to 2N system clock periods, said display control circuitry further being adapted for generating successive second signal sets based on the system clock, each second signal set comprising four active second active write or clock pulse periods, with each second active write or clock pulse period having a period length corresponding to 2N system clock periods; said display system further comprising circuitry for comparing the phase of the first active write pulses with the phase of the second active write or clock pulses, and for changing the phase of the second write or clock pulses when the detected phase difference is larger than a predetermined maximum phase value; and circuitry for providing a clock output corresponding to or substantially equal to the successive second signal sets. Also here, the value of N may be set to one, but the value of N may also be an equal number, and it is preferred that the value of N is 2.

For embodiments of the invention having circuitry for comparing the phase of the first active write pulses with the phase of the second active write or clock pulses, and circuitry for changing the phase of the second write or clock pulses when the detected phase difference is larger than a predetermined maximum phase value, it is preferred that the circuitry for changing the phase of the second write or clock pulses is adapted for changing said phase with about 180 degree corresponding to !4 of an active first write pulse period when the detected phase difference between the first active write pulses and the second active write pulses is larger than said predetermined maximum phase value. It is also preferred that the circuitry for changing the phase of the second write or clock pulses is adapted for changing said phase when the detected phase difference between the first active write pulses and the second active write pulses is larger than a phase difference corresponding to 1/4 of a first active write pulse period. For embodiments of the invention having circuitry for comparing the phase of the first active write pulses with the phase of the second active write or clock pulses, the circuitry for comparing the phases of the first and second active write pulses may comprise an exclusive-or gate having two input signals corresponding to the sets of first active write pulse periods and the sets of second active write pulse periods, respectively, with the output of the exclusive-or gate being fed to a low-pass RC-filter. According to a first embodiment, the circuitry for comparing the phases of the first and second active write pulses may further comprise circuitry for comparing the voltage output of the low-pass filter with a fixed threshold voltage representing the predetermined maximum phase difference. Here, a resistor divider may be used for providing the fixed threshold voltage, and a voltage comparator is used for said comparison with the fixed threshold voltage. According to a second embodiment, the circuitry for comparing the phases of the first and second active write pulses may further comprise an analogue-to-digital converter, ADC, where the output of the low-pass filter is fed to the analogue-to-digital converter, and where the display system further comprises circuitry adapted for comparing the output of the analogue-to-digital converter with stored threshold value representing the predetermined maximum phase value.

BRIEF DESCRIPTION OF THE DRAWINGS

Figs. 1a and 1b show schematic block diagrams of first and second embodiments of a display system according to the present invention,

Fig. 2 shows a schematic block diagram of a display control circuitry for use in the display device of Fig. 1b according to an embodiment of the present invention,

Fig. 3 is a clock diagram illustrating the timing of an RGB sub-pixel interface logically connecting a display control circuitry with a display panel according to an embodiment of the present invention,

Fig. 4 is a clock diagram illustrating the timing of a number of clock signals including internal display control circuitry clock signals and first and second sub-pixel write or clock signals according to an embodiment of the present invention, Fig. 5 is a circuit diagram of sub-pixel clock phase detector according to an embodiment of the present invention,

Figs. 6a and 6b are clock diagrams illustrating phase differences between first sub-pixel write or clock pulses and second sub-pixel write or clock pulses according to embodiment of the present invention,

Fig. 7 is a timing diagram showing falling edges of second sub-pixel write or clock pulses relative to data signal set-up and hold time requirements,

Fig. 8 is a flow chart illustrating an initialization process of the display device according to an embodiment of the present invention,

Fig. 9 is a flow chart illustrating a process for minimization of a sub-pixel clock phase error according to a first embodiment of the present invention, and

Fig. 10 is a flow chart illustrating a process for minimization of a sub-pixel clock phase error according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

According to a preferred embodiment of the invention the display system may be used in connection with a computer device, such as for example a PC, a laptop, a PDA, or a mobile phone. Here, the interface between the mobile phone and the display device is preferably a packet-based bi-directional serial digital interface, where the mobile phone is host and the display device is client. The interface may be capable of transferring video, bitmaps, and audio in either direction between host and client, transferring control information from host to client, and transferring status information from client to host.

The Video Electronics Standards Association ("VESA") MDDI standard, which is incorporated herein by reference in its entirety, describes the requirements of a highspeed digital packet interface that lets low-power computer devices, such as small portable computer devices, transport digital images from the computer devices to external displays. MDDI applies a miniature connector system and thin flexible cable ideal for linking portable computing, communications and entertainment to products such as wearable microdisplays. It also includes information on how to simplify connections between host processors and a display device, in order to reduce the cost and increase the reliability of these connections. Link controllers establish communication path based on the VESA MDDI standard.

In other embodiments, host and client link controllers can both be USB link controllers, but the present invention also includes embodiments wherein the host and client link controllers establish communication path based on the MIPI DSI standard specification, which is incorporated herein by reference in its entirety. According to an embodiment of the invention the MIPI DSI serial communication interface may be supported by a display control circuitry being compliant to the MIPI Alliance Standard D-PHY, which standard specification is incorporated herein by reference in its entirety. Other types of high-speed serial interfaces like interfaces being compliant to the Mobile CMADS (current-mode advanced-differential-signalling), the Mobile Video Interface, the MSDL (mobile-shrink- data-link), the MPL (mobile-pixel-link), HDMI and DisplayPort may also be used for communication between a host computer and embodiments of the display system of the invention.

Figs. 1a shows a schematic block diagram of a display system according to a first embodiment of the present invention. The display system is connected to a host device 101 , such as a mobile phone, via a cable having at least one twisted conductor pairs for data, DATA +/-, and a twisted conductor pair for clock or strobe signals, STB/CLK +/-. The cable further comprises two conductors for power and ground, PWR/GND. Data is received from the host 101 by packet-based serial data communication. It is within embodiments of the invention that digital data communication between the host 101 and the display system may be performed via a MIPI Display Serial Interface (DSI) or a MDDI Interface. The display device of Fig. 1a has two display panels 104a, 104b, which may be microdisplays, display control circuitry 105 for supplying data for the display panels 104, configuration circuitry 106 for configuration of the display control circuitry 105 and the display panels 104, and a power supply 108 for providing power to the different parts of the display system. There is a data interface 107 between the display control circuitry 105 and the display panels 104, which includes a synchronous sub-pixel interface. This sub- pixel interface 107 may use an RGB sub-pixel data bus, DO-7, where the red, green and blue sub-pixel data are transmitted serially. The sub-pixel data bus may be 8 bits wide, which is narrower than the usual interface bus between an LCD controller and a display, which may use an 18- or 24-bit parallel RGB pixel data bus, where RGB pixel data are transmitted in parallel. The sub-pixel interface 107 further has a horizontal sync pulse signal, HSYNC, a vertical sync pulse signal, VSYNC, and a sub-pixel clock signal, SPC, 5 for writing the sub-pixel data into the display panels. The sub-pixel interface may further comprise a data valid signal, DV, but this may be optional, see the discussion in the Data Valid signal section.

The microdisplays 104a,b are configured by the configuration circuitry 106 via an Inter- 10 Integrated Circuit, I²C, serial interface and a reset signal RST_M. The least significant address bit of the microdisplays 104a,b is A₀, and by having A₀ set to 1 for the right microdisplay 104a and set to 0 for the left microdisplay 104b, the configuration circuitry 106 is able to distinguish between right and left displays 104a and 104b.

15 The display control circuitry 105 is configured by the configuration circuitry 106 via a Serial Peripheral Interface, SPI, a reset signal RST_L and a signal INTF-SEL, which determines whether the display control circuitry 105 is communicating with the configuration circuitry 106 via the SPI interface, or the whether the display control circuitry 105 is communicating with the host 101.

20

The power supply 108 supplies power to the display control circuitry 105 and the configuration circuitry 106. The power supply 108 has an output signal POWER_OK that tells the configuration circuitry 106 when the display control circuitry core supply voltage is within limits, thereby enabling the configuration circuitry 106 not to proceed with

25 configuration of the display control circuitry 105 until the core is operational.

Figs. 1 b shows a schematic block diagram of a display system according to a second embodiment of the present invention. The display system of Fig. 1 b corresponds to the display system of Fig. 1a, but the system of Fig. 1b further has phase detector circuitry

30 102, buffer circuitry 103a, 103b for the transfer of data from the display control unit 105 to the microdisplays 104a, 104b, and a Vfe power circuit 109 for providing additional power to the microdisplays 104a, 104b. The Vfe power circuit 109 and the front electrode voltage DC/DC controller inside the left microdisplay 104 b together form a DC/DC converter that converts the main supply voltage (VDD) to the front electrode voltage (Vfe) for both

35 microdisplays 104a and 104b. The Vfe power circuit 109 comprises a transistor, inductor, diode, smoothing capacitor, and power supply bypass capacitor, where the gate of the transistor is controller by a pulse width modulated signal (PWM_Vfe) from the DC/DC controller of the left microdisplay 104b. The DC/DC controller of the right microdisplay 104a is left unused.

For the system of Fig. 1b, the display control circuitry 105 produces an asynchronous sub- pixel write pulse, SPC_3of4, for which there over a period corresponding to four sub-pixel clock periods are three asynchronous write pulses, SPC_3of4, one for each of the R, G, and B sub-pixels. These asynchronous write pulses together may look like a faulty clock, where every fourth clock period is missing, therefore these write pulses cannot be used as a sub-pixel clock by the sub-pixel interface 107. The display control circuitry 105 also produces the sub-pixel clock signal, SPC, with active clock signals for every clock period, but in order to fulfil requirements to set-up and hold times for transfer of data to the microdisplays 104a,b, the phase difference between the SPC_3of4 write pulses and the sub-pixel clock pulses SPC must not be too large. Thus, the phase detector circuitry produces a phase error or difference signal COMP from the SPC_3of4 and SPC signals, and the configuration circuitry 106 detects the value of the COMP signal, and based here upon decides whether a phase adjustment of the SPC signal output from the display control circuitry 105 is to be performed. See also the discussion given in the following sections.

MDDI Interface

It is within a preferred embodiment of the invention that the interface between the host device, which may be a mobile phone, and the display device is a Mobile Display Digital Interface (MDDI), which uses a thin flexible cable between host and client with multiple twisted conductor pairs for low-voltage differential signalling and two conductors for power and ground. The MDDI standard provides for four bandwidth options called MDDI I, II, III, IV with 1 , 2, 4, 8 differential data pairs and a single differential strobe pair for bandwidths of up to 400, 800, 1600, 3200 Mbit/s, respectively. According to an embodiment of the invention, the interface between the host device and the display device follows the MDDI I option.

For embodiments using the MDDI Interface, host and client each have an MDDI link controller that controls the packet stream, computes and checks Cyclic Redundancy Codes (CRC) for data integrity, serializes the data before transmission, and parallelizes data after it is received. The link controllers are fully digital except for the differential line receivers for data and strobe.

MDDI includes different packet types for video/bitmap, audio, control information, and status information. Packet-based communication allows for a mix of data including full- motion video frames, (semi)static bitmaps, and stereo audio that have mutual real-time constraints in order that video and audio stay in sync. Also, support exist for keyboard or pointing-device data from client to host.

Full-motion video may be full screen or partial screen bitmap fields or even compressed video if decompression is implemented in the display device. (Semi)static bitmaps may be full screen or partial screen bitmap fields. Partial screen updates are useful for graphical user interfaces with multiple windows and save power by leaving the surrounding pixels unchanged. Each full-screen and partial screen update requires that a rectangle of pixels with an upper left corner, a lower right corner, and a starting coordinate are transferred. The first pixel written will then be at the starting coordinate, the next at the neighbouring right coordinate, and so on until a vertical side of the delimiting rectangle is encountered in which case a wrap around to the beginning of the next line.

The following is a brief description of the packet structure of MDDI:

MDDI uses the concept of media-frame (or video frame), which in turn may be split into a number of sub-frames that each starts with a Sub-frame Header Packet followed by one or more video, audio, command, and status packets. MDDI packets all include fields for packet length, packet type, packet type specific data bytes, and a 16-bit Cyclic Redundancy Check (CRC). There are a number of packet types including:

Sub-frame Header Packet is required for host-client synchronization.

Video Stream Packet carry video data to update a rectangular region of the display. Video data may either be static graphics data or part of a full-motion video data stream. Video data may be in one of several formats including: monochrome, colour using a colour map, colour using raw red-green-blue (RGB) (used in present invention), colour component video with luminance (Y) and blue/red components (Cb/Cr), or Bayer. For monochrome, colour using a colour map, and Bayer formats the number of bits per pixel is given, for raw RGB the number of pixels for each of the three colours are given, and for colour component video the number of bits for Y, Cb, and Cr are given. The region, which may be anywhere from the full display down to a single pixel, is given by the coordinates of the upper left corner and lower right corner. Furthermore, a start coordinate within the region indicates where the first pixel of the present packet will be written.

Audio Stream Packet carry audio data to be played through the audio system of the client. Audio data may be sent via multiple audio channels including left/right front/rear, front center, sub-woofer, or left/right surround. The number of samples, the number of bits per sample, and the number of samples per second are stated in the packet. (The Audio Stream Packet is not used by the current display device.)

Reverse Link Encapsulation Package allows the host to reverse temporarily the direction of the data lines such that packets that send data from client to host may be embedded within the reverse data packets section of this package. The host will prepare for a reverse data transmission by sending a number of leading zeroes and then disable its data drivers, while the client enable its data drivers. Now the client may transmit its data in the reverse direction for a predetermined number of clock periods. Finally, the host may enable its drivers and the client disables its drivers, whereupon the host may send a number of trailing zeroes. The leading and trailing zeroes are designed to facilitate clock recovery by the client.

Client Capability Packet allows the client upon request to inform the host about its capabilities such as display width and height, RGB colour depths, minimum and maximum video frame rate, audio sample rate and resolution, manufacturer, serial number, and week and year of manufacture.

Filler Packets shall be sent when no other information is ready to be sent.

Link Shutdown Packet direct the client to enter low-power hibernation mode, where it will stay until activity resumes on the MDDI link.

Round-trip Delay Measurement Packet measures the delay from host to client and back including drivers, cable, connectors, and receivers. The client must respond with a predetermined data pattern during the measurement period. The measurement is used to set the turn-around delay etc. for the Reverse Link Encapsulation packet.

Register Access Packet allows the host to access internal registers of the client.

Display control circuitry

Fig. 2 shows a schematic block diagram of a display control circuitry 200 for use in the display systems of Figs. 1a and 1b according to an embodiment of the present invention.

The display control circuitry 200, which has functions similar to the functions of an LCD- control circuitry, receives video stream packets and other data packets via serial interface receiving circuitry 201 , which may be an MDDI client, such as an MDDI type I client, 201 , which in turn feed a pre-processor 202 that writes pixel data in a frame buffer 203. A post- processor 205 repeatedly reads the pixels in the frame buffer 203 and outputs them sub- pixel by sub-pixel to sub-pixel interface 208 according to the timing set-up in programmable timing registers for the post-processor 204. The display control circuitry 200 also contains a control unit 205 that via a relatively slow serial SPI interface allows an external microcontroller to configure the display control circuitry 200 to the extent that this configuration is not done via the serial interface receiving circuitry 201. The display control circuitry 200 furthermore contains a clock unit 206, and possibly a pulse modulation width (PWM) counter unit 207, where the latter may be used to provide a proper sub-pixel clock if the clock unit 206 cannot do so.

Serial interface receiving circuitry, MDDI client

When the serial interface receiving circuitry 201 is an MDDI client, the MDDI client 201 receives packets from a host having an MDDI link host controller and transmits packets to the host embedded within Reverse Link Encapsulation Package from the host. Transmission of packets from the client 201 to the host often occurs in response to a packet received from the host requesting information from the client 201.

Once the data of a received packet is de-serialized and CRC-checked by the client link controller 201 it can be passed on to other packet specific parts of the display control circuitry 200. Similarly the client link controller 201 will generate CRC for and serialize data from various packet specific parts of the display driver circuitry 200 before it is sent to the host.

For Video Stream Packets the client link controller 201 will unpack the embedded video data fields and pass them on to the Pre-processor 202 described below. The video data fields comprise: Video Data Format Descriptor, Pixel Data Attribute, X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge, X Start, Y Start, Pixel Count, and Pixel Data.

The MDDI client 201 receives data from the host via an MDDI Interface with an MDDI data bus, MDDI_DATA+/-, and a strobe signal, MDDI_STB+/-. The MDDI data signals normally transmits data from the host to the client, but the direction of transfer is reversed for the data embedded within Reverse Link Encapsulation Package as explained earlier. The MDDI strobe signals transmits required timing information from the host to the client, and the term required refers to the fact that transitions are omitted on the strobe signals that are already present on the data signals as long as the direction of data transfer is from host to client.

The MDDI client 201 controls the pre-processor 202 via a data bus, an address bus, and a control bus.

The MDDI client controller 201, via the MDDI control or alternatively the Serial Peripheral Interface, SPI, as selected by the signal INTF-SEL, may via the central control 205 access the programmable registers of the pre-processor 202 - via Pre-control interface, post-processor 204 - via Post control interface, clock unit 206 - via clock control interface, and PWM counter unit 207 - via PWM-control interface. This allows the MDDI host 101 via MDDI client controller 201 or alternatively the configuration circuitry 106 via SPI as selected by the signal INTF-SEL to read or write registers within preprocessor 202, post-processor 204, clock circuit 206, or PWM counter 207 as required for configuration, testing, or similar purposes. Both MDDI client controller 201 and central control 205 may be reset by asserting the RST_L signal.

Pre-processor

The pre-processor 202 receives video data fields embedded within Video Stream Packets from the MDDI client 201. Based on these data the pre-processor 201 may perform various graphics functions before writing the pixel data into the region in the frame buffer 203 given by the upper left corner (X Left Edge, Y Top Edge) and lower right corner (X Right Edge, Y Bottom Edge) starting with the first pixel at the start point (X Start, Y Start) and then progressing pixel by pixel from left to right and line to line from top to bottom until the number of pixels given by the pixel count has been written.

The various graphics functions may include conversion from YUV to RGB format, which is the inherent format of the frame buffer 203, colour palette look-up, windowing, and gamma correction.

The pre-processor 202 controls the write side of the frame buffer via a pre-RGB data bus, a pre-address bus, and a pre-write signal.

Frame buffer

The frame buffer 203 holds the image in RGB format such that it may continuously be read by the post-processor 204 described below and written at will by the pre-processor 202 described above. The frame buffer 203 is especially useful when at least some parts of the whole image are only updated occasionally such as may be the case when an image is made up of both a full-motion video window and an adjacent static menu.

The frame buffer 203 holds a number of lines that each holds a number of pixels that in turn each holds a red, a green, and a blue sub-pixel (RGB sub-pixels) that each holds an intensity level of typically 6-8 bits. The frame buffer may be implemented with a static random access memory (SRAM) - and in case of landscape QVGA resolution and 18-bit colours (3 x 6-bit RGB sub-pixels) the SRAM should have a capacity of 320 x 240 x 18 bits. The frame buffer 203 receives write data on the pre-RGB data bus, the coordinates, i.e. the line and pixel number for writing on the pre-address bus, and finally the write control signal on the pre-write signal. Likewise, the frame buffer 203 sends read data on a post-RGB data bus in response to the coordinates, i.e. the line and pixel number for reading on a post-address bus, and finally the read control signal on a post-read signal.

No effort is made in hardware to initialize the contents of the frame buffer 203, whose contents upon power-up will be random and when displayed will look like colourful static "noise". The problem should be solved in software by ensuring that the host early on has written data to every pixel in the frame buffer.

To avoid tearing effects of full-motion video caused by simultaneous writes and reads accessing the frame buffer 203, the beginning of a write may if possible be synchronized to the end of a read or multiple frame buffers 203 may be employed such that individual frame buffers are not written and read simultaneously.

Arbitration between the write access and read access should be applied to prevent simultaneous accesses unless the frame buffer has dual access capability.

Post-processor

The post-processor 204 controls the display function by reading pixels from the frame buffer 203, possibly performing additional graphics functions, dividing pixels into sub- pixels, and finally sending these in a predetermined order to the sub-pixel interface 208. This predetermined order is typically RGB, i.e. red followed by green followed by blue for each pixel. The clocking of the post-processor 204 may be determined by either an internal sub-pixel clock (internal SPC) or an internal pixel clock depending on implementation. The post-processor 204 determines the timing of the sub-pixel interface 208 via a number of programmable registers that are reachable from outside via a central controller 205, which in turn may be reached via an external SPI interface or the external MDDI interface via the MDDI client. The programmable registers determine the number of pixel clocks (depending on implementation) required for horizontal sync pulse (tHP), horizontal back-porch (tHB), pixel data (tHW), and horizontal front-porch (tHF) of each line, and vertical sync pulse (tVP), vertical back-porch (tVB), line data (tVW), vertical front- porch (tVF) of each frame. It is likely that a microdisplay will use sub-pixel clocks as the time unit, which is the situation for the microdisplay(s) according to a preferred embodiment of the invention, while a commercial available LCD-controller functioning as the display driver circuitry 200 may use pixel clocks as the time unit.

The additional graphics functions may be scrolling and stretching of the image.

Clock unit The clock unit 206 typically uses an external crystal or an internal oscillator to generate a clock, which is then input to an internal phase-locked-loop (PLL) and associated clock multiplier and divider that generate internal clocks to the other unit within the display driver circuitry. The post-processor 204 is run by a pixel clock, while the sub-pixel interface 208 is run by the internal sub-pixel clock. The pixel clock may be generated by down-dividing the sub-pixel clock by four, which corresponds to down-dividing twice by 2. This relation means that there will be a dummy sub-pixel for every three RGB sub-pixels, when using the internal sub-pixel clock as a reference. However, it is also within an embodiment of the invention that the pixel clock is generated by down-dividing the sub-pixel clock by three, which will leave out the problem of the dummy sub-pixel.

PWM unit

The PWM unit 207 contains a PWM counter, whose clock can be programmed to the same frequency as the internal sub-pixel clock. It is used to generate a sub-pixel clock with the desired frequency and phase, if a proper sub-pixel clock is not inherently included in the sub-pixel interface 208 of the display driver circuitry. The PWM unit 207 is controlled by the central control unit 205 via the PWM-control interface.

Control interface

The control interface comprises a serial control interface, SPI, a reset signal RST_L for the display control circuitry 200, and an interface select signal, INTF_SEL that select either the serial control interface SPI or the MDDI Interface as the active interface for the control circuitry 200. This allows the serial control interface, SPI, via the central control unit 205, to access the programmable registers of the MDDI client 201 - via MDDI-control interface, pre-processor 202 - via Pre-control interface, post-processor 204 - via Post control interface, clock unit 206 - via clock control interface, and PWM counter unit 207 - via PWM-control interface. It also allows the MDDI interface, via the MDDI client 201 and via the central control unit 205, to access the programmable registers of the pre-processor 202 - via Pre-control interface, post-processor 204 - via Post control interface, clock unit 206 - via clock control interface, and PWM counter unit 207 - via PWM-control interface.

Subpixel interface The post-processor 204 within the display control circuitry 200 sends sub-pixels via the synchronous sub-pixel interface 208 to one or more microdisplays 104. The interface 208 comprises a sub-pixel clock (SPC), an 8-bit RGB sub-pixel databus (DO-7), a data valid signal (DV), which may be optional, a horizontal sync pulse (HSYNC), and a vertical sync 5 pulse (VSYNC). The data and control signals of the sub-pixel interface are fed by an output register in the post-processor 204 and accepted by an input register in the microdisplays 104. The output register is clocked by the positive edge of the sub-pixel clock, SPC, while the input register is clocked by the negative edge of the sub-pixel clock, SPC₁ thus the timing of the sub-pixel interface is rather relaxed. The sub-pixel interface 10 208 of Fig. 2 also holds an asynchronous sub-pixel pulse signal, SPC_3of4, to be discussed later. The SPC_3of4 signal is not forwarded to the microdisplays 104.

The timing of the signals of the sub-pixel interface 208 is illustrated in Fig. 3. The signals of the sub-pixel interface 208 are the sub-pixel clock, SPC, the 8-bit RGB sub-pixel 15 databus, DO-7, the data valid signal, DV, which may be optional, the horizontal sync pulse, HSYNC, and the vertical sync pulse, VSYNC.

Each frame is made up by a vertical back-porch, a number of horizontal lines, a vertical front-porch, and a vertical sync pulse, VSYNC. Each horizontal line in turn is composed of 0 a horizontal back-porch, a number of pixels, a horizontal front-porch, and a horizontal sync pulse, HSYNC. Each pixel in turn is composed of a red, green, and blue sub-pixel, whose intensity is given by D[0:7]. The sub-pixel clock SPC provides the synchronous timing information, and the data valid signal DV indicates when sub-pixels are valid. 5 As mentioned above, the post-processor 204 determines the timing of the sub-pixel interface 208 via a number of programmable registers. The programmable registers determine the number of pixel clocks (depending on implementation) required for horizontal sync pulse, tHP, horizontal back-porch, tHB, pixel data, tHW, and horizontal front-porch, tHF, of each line, and vertical sync pulse, tVP, vertical back-porch, tVB, line 0 data, tVW, vertical front-porch, tVF, of each frame.

Microdisplay driver circuit

The sub-pixel interface 208 of the display control circuitry 200 provides signals for the 5 sub-pixel interfaces of the microdisplays 104, but the drivers of the post-processor 204 may not have the current drive (l_Oh and I_O|) required to drive the capacitance of two microdisplays 104 each mounted on a flexible printed circuit board (PCB) and separated by an inter-pupillary distance. Instead the post-processor 204 may drive a buffer with at least 12 drivers corresponding to SPC, DO-7, DV, HSYNC, and VSYNC, which each may drive both the left and right microdisplay. Each of the two branches of each of the 12 signals should be fitted with a series termination resistor to prevent ringing.

Microdisplays

According to an embodiment of the invention, emissive microdisplays 104 are used, i.e. they emit their own light unlike reflective or transmissive microdisplays. Polymer Organic Light Emitting Diode (P-OLED) is typical an emissive technology, whereas LCOS (Liquid Crystal on Silicon) is typical an reflective technology, and LCD is typical a transmissive technology.

Each microdisplay 104 may comprise an array of visible although minute display pixels, a sub-pixel interface, a microdisplay reset, a serial control interface, and an internal DC/DC controller. The sub-pixel interface receives the sub-pixels emitted by the sub-pixel interface 208 of the post-processor 204 in the display control circuitry 200. The microdisplay reset and serial control interface, which may use either SPI or I²C protocol, is used for configuration by the configuration circuitry 106, which may be a microcontroller. In case of an I²C interface, then for the embodiment with two microdisplays, each microdisplay 104 has a least significant address bit AO, which is tied low (0) for the left microdisplay and high (1) for the right microdisplay, such that the microdisplays 104 are uniquely addressed by the serial protocol.

Special power supplies

Each microdisplay 104 may need low-current special voltages other than the main supply voltage, which each may be produced by a DC/DC converter comprised of a DC/DC controller internal to the microdisplay 104 and a few external components (transistor, inductor, diode, smoothing capacitor, and power rail bypass capacitor). For the embodiment with two microdisplays 104, then if the difference in luminance between the left and right microdisplay at the same main supply voltage and set of special voltages is negligible, it is possible to dispense with the external components of, say, each right DC/DC converter and share the special voltage generated by each left converter between the two microdisplays 104.

Sub-pixel clock, SPC

The interface of commercial sub-LCDs, which may be used as a small secondary display on the outside of clamshell mobile phones, is often asynchronous in nature, i.e. it uses a microprocessor style data/command bus with read and write pulses, rather than the synchronous interface of typical main-LCD with clock, data bus, and dedicated control signals for data valid (DV), horizontal sync (HSYNC), and vertical sync (VSYNC). Also, sub-LCD panels may use a data bus that transfers a pixel in one, two, or three asynchronous transfers or synchronous clock cycles depending on the width of the data bus. Transfer of sub-pixels requires three transfers or clock cycles, while transfer of VA sub-pixels (all bits of one colour and about half the bits of another colour) require two transfers or clock cycles.

Microdisplays 104 with a digital interface often have a synchronous sub-pixel interface, i.e. they share the characteristics of a classical main-LCD interface except that they use a narrower bus, where RGB sub-pixel data are transmitted 8-bit serially. The display control circuitry 200 used for driving the microdisplays 104 may be programmed in such a way that it has an interface, which corresponds to a sub-LCD interface, and which emits 8-bit RGB sub-pixels serially and at the same time emits HSYNC and VSYNC pulses like a synchronous main-LCD interface.

When having the display control circuitry 200 adapted for emitting 8-bit RGB sub-pixels serially, there may over a period corresponding to four sub-pixel clock periods be three asynchronous write pulses, SPC_3of4, one for each of the R, G, and B sub-pixels. These asynchronous write pulses together may look like a faulty clock, where every fourth clock period is missing, therefore these write pulses cannot be used as a sub-pixel clock by the sub-pixel interface 208. The output, SPC, of the PWM 207 counter may act as sub-pixel write or clock signal and replace the faulty sub-pixel write or clock SPC_3of4. The PWM counter 207 should be programmed such that its number of low and high cycles, output polarity or number of delay cycles is such that the output has the same frequency and (nearly) the same phase as the faulty clock SPC_3of4 (when including the missing fourth clock period). Fig. 4 is a diagram illustrating a number of clock signals, which are used by the display control circuitry 200 according to an embodiment of the invention. Here, sys_clk is the internal clock signal of the display controller circuitry 200 from which all other clocks may be derived. The post_clk signal, which is the clock signal for the post-processor 204, and the pwm_clk signal, which is the clock signal for the PWM counter 207, are obtained from sys_clk by dividing with 2. The internal phase difference of the post_clk and pwm_clk signals is arbitrary and unknown upon power-up. Fig. 4 also shows the faulty sub-pixel clock SPC_3of4, which is also referred to as the first sub-pixel write or clock signal, and which is generated by the post-processor 204 from the post_clk signal. Fig. 4 also shows the nominal pixel clock, which is shown in order to illustrate the period length for transferring colour data for a pixel.

According to an embodiment of the invention, the frequencies of the clock signals are selected so that internal clock signal sys_clk is about 80 MHz, post_clk and pwm_clk are about 40 MHz₁ SPC and SPC_3of4 are about 20 MHz, and the nominel pixel clock is about 5 MHz.

Fig. 4 further shows different possible phases of the sub-pixel clock, SPC, which is also referred to as the second sub-pixel write or clock signal, and which is generated by the PWM counter 207 from the pwm_clk signal. The phase difference of the SPC signal relative to the pwm_clk is arbitrary and unknown upon power-up. Thus the phase difference between the faulty sub-pixel clock SPC_3of4 and the new sub-pixel clock SPC is arbitrary and unknown upon power-up. Fig. 4 illustrates four possible phase differences with f = 0, Vz, % and % of a sub-pixel clock period.

Data valid signal

According to an embodiment of the invention the sub-pixel interface 208 includes a data valid signal, DV, which indicates when a valid sub-pixel is present, i.e. the signal should be asserted during RGB sub-pixels and de-asserted during dummy sub-pixels, horizontal and vertical sync pulses, and horizontal and vertical back- and front-porches. It is also within one or more embodiments of the invention that the display control circuitry 105, 200 is not equipped with a data valid signal output DV₁ and here the microdisplays 104a, 104b may each be able to compensate for this by generating an internal alternate data valid signal, DV, which either replaces the missing external data valid signal, DV₁ or gates it via an AND-gate under the assumption that the external data valid DV is constantly asserted. The internal alternate data valid signal DV should de-assert the data valid outside the image data region (sub-pixels) and temporarily de-assert the signal during all dummy sub- sub-pixels, i.e. every fourth sub-pixel. These capabilities should be programmable during the configuration of the microdisplay.

When the display control circuitry 105, 200 does not have a DV output, then the DV input to the buffer 103a, 103b may instead be asserted with a pull-up resistor, and the microdisplays 104a, 104b may be configured to use the AND-gate function described above.

Phase detector circuitry

Fig. 5 is a circuit diagram of sub-pixel clock phase detector according to an embodiment of the present invention.

The phase adjustment of the sub-pixel clock, SPC, ensures that the phase of the PWM counter 207 output, SPC, is either identical to that of the faulty sub-pixel clock, SPC_3of4, or that the phase difference between the sub-pixel clock, SPC, and the faulty sub-pixel clock, SPC_3of4, is held at a value being small enough to ensure that set-up and hold time requirements are fulfilled for the active falling clock edges of SPC relative to data and control signals of the sub-pixel interface 208. To this end the faulty sub-pixel clock, SPC_3of4, and the sub-pixel clock, SPC, generated by the PWM counter 207 are compared by an exclusive XOR-gate 501 that generates an error signal, which is then low-pass filtered by an RC-filter 502, whose output in turn is an analogue representation of a duty cycle error signal. According to a first embodiment of the invention, this analogue signal is fed to comparator 503 for being compared to a fixed threshold voltage representing a predetermined maximum phase value. The fixed threshold voltage may be provided by a resistor network 504. The output COMP of the comparator 503 is fed to the configuration circuitry. According to a second embodiment of the invention, the output of the RC-filter 502 is fed to an analogue-to-digital converter, ADC, 505, and the output DUTY-CYCLE of the ADC 505 is fed to the configuration circuitry 106, which may be adapted for comparing the ADC signal 505 with a stored threshold value representing a predetermined maximum phase difference. It is preferred that fixed threshold voltage or the stored threshold value represents a phase value corresponding to a duty cycle error signal of 7/32.

Figs. 6a and 6b are clock diagrams illustrating phase differences between the first sub- pixel write or clock pulses, SPC_3of4, and the second sub-pixel write or clock pulses, SPC, together with the duty cycle of a generated error signal, XOR, according to embodiments of the present invention. The error signal XOR is the output of the XOR gate 501 having the faulty sub-pixel clock, SPC_3of4, and the sub-pixel clock, SPC, generated by the PWM counter 207, as input signals, and the duty cycle is given as the fraction of time the XOR signal is high within four sub-pixel clock periods. Fig. 6a shows that for a phase error f = 0, the duty cycle of the error signal XOR is 1/8, for f = 1/4, the duty cycle is 1/2, for f = 1/2, the duty cycle is 7/8, and for f = 3/4, the duty cycle is 1/2. Fig. 6b shows that for a phase error f = 1/8, the duty cycle of the error signal XOR is 5/16, for f = 3/8, the duty cycle is 11/16, for f = 5/8, the duty cycle is 11/16, and for f = 7/8, the duty cycle is 5/16.

The fixed threshold for the duty cycle (used in the resistor divider 504 or the stored value tested against the ADC output 505) may be the midpoint of the lowest duty cycle 1/8 at f = 0, and the next lowest duty cycle 5/16 at f = 1/8. Thus the threshold becomes (1/8 + 5/16)/2 = (4/32 + 10/32)/2 = 7/32.

Fig. 7 shows the active falling clock edges of the sub-pixel clock, SPC₁ relative to the setup and hold time requirement for the DATA [0:7], HSYNC, VSYNC, DV signals for phase errors of f = 0, 1/4, Y₂, 3/4. It may be seen from Fig. 7 that set-up and hold time requirements are fulfilled for phase errors of f = 0, Y* and ³A, while the requirements are not fulfilled for a phase error of f = Yz.

Configuration circuitry

Fig. 8 is a flow chart illustrating an initialization or configuration process of the display device 105, 200 according to an embodiment of the present invention. Here, the configuration circuitry 106, which may be a microcontroller, configures or initializes the display control circuitry 105, 200, adjusts the phase of the sub-pixel clock, SPC, if necessary, configures or initializes the left and right micro-displays 104, and then goes into a power down mode of the configuration circuitry 106. For adjustment of the phase of the sub-pixel clock SPC, it is seen from Fig. 7 that a phase error or difference of f = 0 is ideal, while f = % and ³A axe acceptable as the set-up and hold times for set-up and hold time requirement for the DATA [0:7], HSYNC₁ VSYNC₁ DV signals still are met. Only a phase error or phase difference of f = ^ΛA is unacceptable as the set-up and hold times may be violated. The output COMP of the comparator 503 indicates whether the duty cycle of the error signal is below 7/32, which by a safe margin indicates that f = 0 corresponding to a duty cycle error of 1/8. The configuration program running on the microcontroller is adapted for testing the comparator output COMP to decide whether the ideal phase f = 0 has already been attained at power-up, or corrective action should be taken. In the latter the configuration program inverts the SPC signal, i.e. changing the phase of the SPC signal by about 180°, by reprogramming the polarity of PWM register providing the SPC signal output from the PWM counter unit 207. If the phase error or difference was f = ^ΛA, then this action will change it to f = 0, which is ideal. If, on the other hand the phase error or difference was f = ^ΛA or ³A then the new phase difference will be f = ³A or VA, respectively. This is not ideal, but workable as the timing requirements on the set-up and hold times are rather relaxed as the signals clocked out by SPC change on the rising edge of SPC and are clocked in on the falling edge of SPC. This process is illustrated by the flow chart of Fig. 9, which shows the process for minimization of the sub-pixel clock phase error, where the SPC signal is inverted when the duty cycle error signal is equal to or larger than 7/32.

As an alternative, the configuration program may, by suitable programming of a delay register in the PWM unit 207, delay the SPC signal thus changing its phase by stepping the phase offset f through the values 0, 1/8, %, 3/8, Yi, 5/8, ³A, 7/8. For one of these value the comparator will indicate that the minimum duty cycle error of 7/32 has been met. The configuration should then stick to the current setting of the delay register. This process is illustrated by the flow chart of Fig. 10. First the phase offset is set to 0, and if the duty cycle of the error signal is below 7/32, then there is no change of the phase. If the duty cycle is equal to or above 7/32, then the phase offset is incremented by 1/8, and after a settling time, RC filter settling, the new duty cycle of the error signal is compared against the minimum duty cycle error, and this is repeated until the duty cycle is below 7/32.

Power supply The power supply 108 provides power to the different sections of the display system and comprises a DC/DC step-down converter and a low drop-out (LDO) linear regulator. The DC/DC step-down converter converts a variable supply voltage provided by a lithium-ion (polymer) battery within the host device, which may be a mobile phone, to a single fixed main supply voltage used by all sections except the core of the display control circuitry 105, 200 and any sections within the microdisplays 104 requiring special supply voltages. The LDO-linear regulator provides power to the core of the display control circuitry 105, 200 at a lower supply voltage than the main supply voltage. The difference between the two voltages will typically be less than 1 Volt and the current will be a few milliamps, and therefore the power lost in the LDO-linear regulator is typically a few milliwatts. The LDO- linear regulator has a Power_OK output that tells the configuration circuitry 106 that the display control circuitry core supply voltage is within limits, thereby enabling the configuration circuitry 106 not to proceed with configuration of the display control circuitry 105, 200 until the core is operational.

Claims

1. A display system comprising: one or more microdisplay panels; display control circuitry; and configuration circuitry for configuration of the display control circuitry and the display panel(s), wherein the display control circuitry is adapted for receiving and processing digital video input signals and for supplying digital video output signals as input for the microdisplay panel(s).

2. A display system according to claim 1, said display device comprising one and only one microdisplay panel.

3. A display system according to claim 1 , said display device comprising two micropanels, a first and a second microdisplay panel.

4. A display system according to any one of the claims 1-3, wherein the display control circuitry is adapted for serially transmitting sub-pixel colour data via a sub-pixel data-bus being part of a sub-pixel interface for feeding or driving the microdisplay panel(s).

5. A display system according to claim 4, wherein the sub-pixel data-bus has a bit width equal to the bit width of a sub-pixel.

6. A display system according to claim 4 or 5, wherein the display control circuitry is adapted for transmitting a sub-pixel clock signal being part of the sub-pixel interface for the driving of the microdisplay panel(s).

7. A display system according to claim 6, wherein the display control circuitry is adapted for transmitting a horizontal sync pulse, HSYNC, and a vertical sync pulse, VSYNC, being part of the sub-pixel interface for the driving of the microdisplay panel(s).

8. A display system according to any one of the claim 1 or claims 3-7, said system comprising at least two microdisplay panels, with the driving signals being fed in parallel from the display control circuitry to each of the microdisplay panels.

9. A display system according to any one of the claims 1-8, said system further comprising buffer circuitry for transferring data for driving the microdisplay panel(s) from the display control circuitry to the microdisplay panel(s).

10. A display system according to any one of the claims 1-9, wherein the display control circuitry is adapted for receiving and processing a digital video input signal being received via packet-based serial data communication.

11. A display system according to any one of the claims 1-10, wherein the display control circuitry is adapted for receiving and processing a digital video input signal being received by use of differential signalling.

12. A display system according to claim 11, wherein the differential signalling is performed via a receiving communication interface comprising at least one twisted conductor pairs for receiving differential data.

13. A display system according to claim 12, wherein the receiving communications interface further comprises a twisted conductor pair for communicating clock or strobe signals.

14. A display system according to claim 12 or 13, wherein the receiving communications interface further comprises two conductors for power and ground.

15. A display system according to any one of the claims 1-14, wherein the display control circuitry is adapted for receiving and processing a digital video input signal presented in accordance with the Display Serial Interface Standard, DSI.

16. A display system according to any one of the claims 1 -14, wherein the display control circuitry is adapted for receiving and processing a digital video input signal presented in accordance with the Mobile Display Digital Interface Standard, MDDI.

17. A display system according to claim 15 or 16, further comprising a cable connector.

18. A display system according to any one of the claims 1-17, wherein the display control circuitry has serial interface receiving circuitry, pre-processing circuitry, frame buffer circuitry, post-processor circuitry, with the serial interface reciving circuitry being adapted for unpacking embedded video data fields from video stream packets received as part of a serial digital video input signal and forwarding the video data fields to the preprocessing circuitry, the pre-processing circuitry being adapted for writing pixel data into the frame buffer circuitry based on the received video data fields.

19. A display system according to claim 18, wherein the display control circuitry is adapted for receiving and processing the digital video input signal presented in accordance with the Mobile Display Digital Interface Standard, MDDI, and the serial interface receiving circuitry comprises MDDI client circuitry.

20. A display system according to claim 18 or 19, wherein the post-processor circuitry is adapted for reading pixel data from the frame buffer circuitry, dividing the pixel data into sub-pixel data and for forwarding the sub-pixel data in a predetermined order via a sub- pixel interface for driving the microdisplay panel(s).

21. A display system according to claim 20, wherein the post-processor circuitry is adapted for forwarding the sub-pixel data in a predetermined order of colours for each pixel.

22. A display system according to claim 20 or 21 , wherein the post-processor circuitry is adapted for generating and determining the timing of a horizontal sync pulse, HSYNC, and a vertical sync pulse, VSYNC, being forwarded as part of the sub-pixel interface for the driving of the microdisplay panel(s).

23. A display system according to any one of the claims 18-22, wherein the display control circuitry further comprises central control circuitry for accessing programmable registers of the circuitries of the display control circuitry via a serial control interface.

24. A display system according to any one of the claims 18-23, wherein the display control circuitry further comprises central control circuitry for accessing programmable registers of the circuitries of the display control circuitry via the serial interface receiving circuitry or the MDDI client circuitry.

5

25. A display system according to any one of the claims 18-24, wherein the display control circuitry further comprises clock circuitry for generating one or more clock signals for the circuitries of the display control circuitry and/or display system.

10 26. A display system according to any one of the claims 20-25, wherein the postprocessor circuitry is adapted for generating and forwarding a sub-pixel clock corresponding to the sub-pixel data as part of the sub-pixel interface for the driving of the microdisplay panel(s).

15 27. A display system according to any one of the claims 20-25, wherein the postprocessor circuitry is adapted for generating an asynchronous write pulse signal corresponding to the sub-pixel data.

28. A display system according to claim 27, wherein the asynchronous write pulse 20 signal is generated based on a system clock and comprises successive first signals sets, each first signal set having three successive first active write pulse periods followed by a non-active dummy period having a period length corresponding to the length of an active write pulse period.

25 29. A display system according to claim 28, wherein each first active write pulse has a period length corresponding to 2N system clock periods, where N is an integer number, and the non-active dummy period has a period length of 2N.

30. A display system according to any one of the claims 27-29, wherein the display 30 system or the display control circuitry further comprises pulse generating circuitry being adapted for generating successive second signal sets based on the system clock, each second signal set comprising four second active write or clock pulse periods, corresponding to the sub-pixel data.

31. A display system according to claims 29 and 30, wherein each second active write pulse or clock pulse has a period length corresponding to 2N system clock periods, where N is an integer number.

5 32. A display system according to claim 31 , said display system or display control circuitry further comprises phase circuitry for comparing the phase of the first active write pulses with the phase of the second active write or clock pulses, and circuitry for changing the phase of the second active write or clock pulses if the detected phase difference is larger than a predetermined maximum phase value. 10

33. A display system according to claim 32, wherein the display system or display control circuitry is adapted for forwarding a sub-pixel clock signal corresponding to the second signal sets for the driving of the microdisplay panel(s).

15 34. A display system according to claim 32 or 33, wherein the configuration control circuitry is adapted for generating a change phase signal when the detected phase difference is larger than the predetermined maximum phase value.

35. A display system according to any one of the claims 1-25, wherein 0 the display control circuitry is adapted for generating successive first signal sets based on a system clock, each set of first signal sets comprising three successive first active write pulse periods with each first active write pulse period having a period length corresponding to 2N system clock periods where N is an integer number, each first signal set further having a non-active dummy period having a period length corresponding to 2N 5 system clock periods, said display control circuitry further being adapted for generating successive second signal sets based on the system clock, each second signal set comprising four active second active write or clock pulse periods, with each second active write or clock pulse period having a period length corresponding to 2N system clock periods; said display system further comprising 0 circuitry for comparing the phase of the first active write pulses with the phase of the second active write or clock pulses, and for changing the phase of the second write or clock pulses when the detected phase difference is larger than a predetermined maximum phase value; and circuitry for providing a clock output corresponding to or substantially equal to the 5 successive second signal sets.

36. A display system according to any one of the claims 32-35, wherein the circuitry for changing the phase of the second write or clock pulses is adapted for changing said phase with about 180 degree corresponding to ^yA of an active first write pulse period when

5 the detected phase difference between the first active write pulses and the second active write pulses is larger than said predetermined maximum phase value.

37. A display system according to any one of the claims 32-36, wherein the circuitry for changing the phase of the second write or clock pulses is adapted for changing said

10 phase when the detected phase difference between the first active write pulses and the second active write pulses is larger than a phase difference corresponding to 1/4 of a first active write pulse period.

38. A display system according to any one of the claims 29-37, wherein the value of N 15 is set to one.

39. A display system according to any one of the claims 29-37, wherein the value of N is an equal number.

20 40. A display system according to claim 39, wherein the value of N is 2.

41. A display system according to any one of the claims 32-40, wherein the circuitry for comparing the phases of the first and second active write pulses comprises an exclusive-or gate having two input signals corresponding to the sets of first active write

25 pulse periods and the sets of second active write pulse periods, respectively, the output of the exclusive-or gate being fed to a low-pass RC-filter.

42. A display system according to claim 41 , wherein the circuitry for comparing the phases of the first and second active write pulses further comprises circuitry for

30 comparing the voltage output of the low-pass filter with a fixed threshold voltage representing the predetermined maximum phase value.

43. A display system according to claim 42, wherein a resistor divider is used for providing the fixed threshold voltage, and a voltage comparator is used for said 5 comparison with the fixed threshold voltage.

44. A display system according to claim 41 , wherein the circuitry for comparing the phases of the first and second active write pulses further comprises an analogue-to-digital converter, ADC₁ and the output of the low-pass filter is fed to the analogue-to-digital converter, and wherein^'the display system further comprises circuitry adapted for comparing the output of the analogue-to-digital converter with stored threshold value representing the predetermined maximum phase value.