WO2009139509A1

WO2009139509A1 - Method of compensating jitters due to power supply variation and digitally controlled oscillator implemented thereof

Info

Publication number: WO2009139509A1
Application number: PCT/KR2008/002661
Authority: WO
Inventors: Deog Kyoon Jeong; Byoung-Mo Moon; Dong-Hyuk Lim
Original assignee: Snu Industry Foundation
Priority date: 2008-05-14
Filing date: 2008-05-14
Publication date: 2009-11-19
Also published as: KR101183738B1; KR20110014643A

Abstract

The present invention constitutes a pseudo-differential pair and constitutes latch in a PMOS and NMOS to symmetrically compensate for the fluctuation in power supply on both rising and falling edge sides, thereby minimizing propagation delay jitter. The present invention has two nodes on both sides of a delay line for a coarse tuning and constitutes a block for a fine tuning, thereby providing a method for compensating for strength of a feedback latch of a delay cell corresponding to the fluctuation in power supply. The present invention increases driving force of the PMOS, when VDD is increased, and then the output voltage is increased to that extent so that the increased output voltage allows the NMOS latch to be strongly closed to generate a time delay to that extent in inverting a previous state, making it possible to make the entire propagation delay to be constant. As a result, even though the power supply is slightly fluctuated, a clock having a predetermined frequency can be oscillated without jitter noise

Description

METHOD OF COMPENSATING JITTERS DUE TO POWER SUPPLY VARIATION AND DIGITALLY CONTROLLED OSCILLATOR IMPLEMENTED THEREOF

Technical Field

[1] The present invention relates to a digitally controlled oscillator (DOC), and more particularly, to a technique that an output waveform frequency of a digitally controlled oscillator is not affected by fluctuation in power supply voltage in an all-digital phase- locked loop (ADPLL) system where the entirety circuit is implemented by a digital circuit. Background Art

[2] A phase-locked loop (PLL) circuit has been widely used in a clock and data recovery

(CDR) circuit. In an analog PLL circuit in the related art using a charge pumping method, a control signal is represented as a charge amount stored in a capacitor of a loop filter. As a consequence, when a leakage gate current of a MOS transistor increases, it deteriorates the frequency spectrum characteristics as a reference spur. In order to resolve the inherent problem of the analog PPL circuit, an all-digital phase- locked loop (ADPLL) circuit scheme has been adopted. In the case of the ADPLL, a digital loop filter (DLF) 20 is employed rather than the charge pump capacitor in the related art.

[3] FIG. 1 is a diagram illustrating a constitution of an ADPPL circuit that is commonly used in this field. A time-to-digital converter (TDC) 10 converts an input timing error Θ_e into a digital code, and a digital loop filter (DLF) 20 filters the converted digital code signal to generate a control signal for controlling a digitally controlled oscillator (DCO) 30. Herein, the digital loop filter 20 is implemented with only a digital logic gate and a flip flop, not using the capacitor as in the prior art, having advantages of resolving the problem of the capacitor leakage current as well as the minimization of a chip area. The digitally controlled oscillator 30 corresponds to a voltage controlled oscillator (VCO) in an analog PLL. Herein, the performance of the digitally controlled oscillator 30 has a great influence on the property of the entire digital PLL so that the digitally controlled oscillator 30 is very important. In the meanwhile, an output clock CKO of the digitally controlled oscillator 30 is fedback through an N divider 40 to input a timing error with an input signal CKI to the TDC 10.

[4] FIG. 2 is a diagram illustrating a constitutional block of a digitally controlled oscillator, which is commonly used in this field. Referring to FIG. 2, the digitally controlled oscillator (DCO) according to the prior art includes a coarse tuning block and a fine tuning block, wherein the coarse tuning block selects an output delay in a delay stages comprising an inverter chain while the fine tuning block performs a fine tuning by changing a driving force under a predetermined load.

[5] However, an output oscillating frequency of the digitally controlled oscillator (DCO) of the prior art is affected directly by the change in power supply. A propagation delay time is approximately in inversely proportional to the magnitude of power supply. Consequently, the fluctuation in the power supply generates a jitter noise at the output signal of the digitally controlled oscillator.

[6] FIGS. 3 and 4 are diagrams illustrating jitters of the output signal of the digitally controlled oscillator and dependence according to the fluctuation in power supply, respectively. Referring to FIG. 3, a timing t_peπod of a clock fluctuates with the variation of the magnitude of the power supply. Therefore, a period is changed at every moment, which generates jitter noise. Referring to FIG. 4, the curve indicated by -*-*- reveals that a gate delay time is reduced almost in an inverse manner as the power supply voltage is increased from 0.95V to 1.55V. In FIG. 4, the curve indicated by - O - O - O -, which is data showing a case where the technique according to the present invention is applied, illustrates a case when the dependence on the fluctuation in power supply is relieved. The detailed description thereof will be described in detail in the folio wings.

[7] If a power supply V_DD level fluctuates in a digital system, the jitter noise is generated as shown in FIGS. 3 and 4. As a result, the period of the output clock of the PLL is changed and a setup/hold time violation is caused in the entire CDR circuit as shown in FIG. 5. FIG. 5 is a schematic diagram illustrating examples of the setup/hold time violation in the cases where the jitter noise exists and not, respectively.

[8] In order to improve the aforementioned power supply sensitivity of the delay cell, a method either to control the power supply of a delay cell or to control a current complementary biasing circuit has been proposed. Mozhgan Mansuri et al. have proposed a complementary biasing circuit for compensating a jitter in a paper titled with "A low- power adaptive bandwidth PLL and clock buffer with supply-noise com- pensation"(IEEE Journal of Solid-State Circuits, Vol. 39, No. 11 pp. 1804-1812, 2003).

[9] However, the method proposed by Mozhgan Mansuri has a shortcoming that the high-frequency component can not be compensated due to the slow response to the fluctuation in the power supply despite of the fact that we can expect some effect in the low-frequency component. Disclosure of Invention Technical Problem

[10] Therefore, a first object of the present invention is to provide a delay cell architecture and a digitally controlled oscillator which does not generate jitter noise even with the presence of the fluctuation in the power supply.

[11] Another object of the present invention is to provide an all-digital phase-locked loop

(ADPPL) circuit which can keep a propagation delay time constant even for the presence of the fluctuation in the power supply. Technical Solution

[12] The present invention provides a digitally controlled oscillator that is implemented by a plurality of delay cells in a chain form, the delay cell having input terminals D and DB and output terminals Q and QB, wherein the delay cell comprises: a first inverter that includes a PMOS transistor 130 and an NMOS transistor 120 whose gates receive the input D and whose drains output the output QB; a second inverter that includes a PMOS transistor 150 and an NMOS transistor 140 whose gates receive the input DB and whose drains output the output B; a pseudo-differential pair configured of a pair of NMOS transistors 160 and 170 and a pair of PMOS transistors 180 and 190, the gates of the NMOS transistors 160 and 170 being connected to the drains of other NMOS transistors 170 and 160, respectively, the gates of the PMOS transistors 180 and 190 being connected to the drains of other PMOS transistors 190 and 180, respectively, the drain outputs of the NMOS transistors 160 and 170 being connected to Q and QB, respectively, to connect the output Q of the differential pair circuit to the output of the second inverter and to connect the output QB to the output of the first inverter; a complementary biasing PMOS transistor whose source is connected to V_DD power supply line and drain is connected between sources of the PMOS transistors 180 and 190; and a complementary biasing NMOS transistor whose source is connected to GND line and drain is connected between sources of the NMOS transistors 160 and 170, wherein V_TH (threshold voltage of transistor) is applied to the complementary biasing PMOS transistor and V_DD- V_TH is applied to the gate of the NMOS transistor.

[13] The present invention constitutes a pseudo-differential pair and constitutes a latch in a PMOS and NMOS to symmetrically compensate for the fluctuation in power supply on both rising and falling edge sides, thereby minimizing the propagation delay jitter. The present invention has two nodes on both sides of a delay line for a coarse tuning and constitutes a block for a fine tuning, thereby providing a method for compensating for strength of a feedback latch of a delay cell in response to the fluctuation in power supply.

Advantageous Effects

[14] The present invention raises a driving force of the PMOS in response to the increase of V_DD, which results in the rise of the output woltage. Consequently, the increased output voltage makes the strength of the NMOS latch in such a way that an overall propagation delay can be kept constant thanks to the generation of the time delay for the inversion of the state correspondingly. We can expect to generate the oscillation of a clock with a constant frequency even with the presence of a little fluctuation of the power supply. Brief Description of Drawings

[15] FIG. 1 is a diagram showing a constitution of an ADPPL circuit in the related art;

[16] FIG. 2 is a diagram showing a construction block of a digitally controlled oscillator in the related art;

[17] FIGS. 3 and 4 are diagrams showing a jitter of the output signal of the digitally controlled oscillator and dependence according to the fluctuation in the power supply, respectively;

[18] FIG. 5 is a diagram showing examples of a setup/hold time violation when a jitter noise exists and the jitter noise does not exist;

[19] FIG. 6 is a diagram showing a delay cell structure according to an exemplary embodiment of the present invention;

[20] FIG. 7 is a diagram showing an example where a complementary biasing circuit of a delay cell is implemented by MOS diodes according to an exemplary embodiment of the present invention;

[21] FIG. 8 is a diagram showing a constitution of a delay cell according to another embodiment of the present invention;

[22] FIG. 9 is a diagram showing a structure of a delay cell according to another embodiment of the present invention;

[23] FIGS. 10 and 11 are diagrams showing a structure of a delay cell according to still another embodiment of the present invention; and

[24] FIG. 12 is a diagram showing a constitution of a digitally controlled oscillator implemented by applying a delay cell according to an exemplary embodiment of the present invention. Best Mode for Carrying out the Invention

[25] Hereinafter, the present invention will be described in detail with reference to the accompanying FIGS. 6 to 12.

[26] FIG. 6 is a diagram showing a delay cell structure according to an exemplary embodiment of the present invention. Referring to FIG. 6, an output of NMOS drivers 160 and 170 of a differential amplifier is connected to a gate terminal of NMOS transistors 170 and 160, and an output of PMOS load transistors 180 and 190 is connected to a gate of PMOS transistors 190 and 180. In the present invention, the structure of the aforementioned differential amplifier will be referred to as a pseudo-differential pair.

[27] The output QB of the pseudo-differential pair that includes the NMOS transistors 170 and 160 and the PMOS transistors 180 and 190 is connected to an output of an inverter terminal that includes transistors 120 and 130, and an input signal D is connected to a gate input of the inverter that includes the transistors 120 and 130.

[28] Further, the output B of the pseudo-differential pair that includes the NMOS transistors 170 and 160 and the PMOS transistors 180 and 190 is connected to an output of an inverter terminal that includes transistors 140 and 150, and an input signal DB is connected to a gate input of the inverter that includes the transistors 140 and 150.

[29] Herein, the transistors Nl 110 and Pl 200, which are current sources, serve to control the current flow in the pseudo-differential amplifier, that is, to control the current driving strength. As an exemplary embodiment of the present invention, a gate of the Nl transistor 110 is controlled with V_DD-V_TH (V_DD is the power supply voltage and V_TH is the threshold voltage of transistor).

[30] The driving voltage of the Nl MOS transistor 110 is V_DD-2V_TH, wherein when V_DD is low (that is, when power supply voltage is dropped), the Nl MOS transistor 10 is weakly turned on so that it takes little time to invert the previous state, however when V_DD is increased (that is, when power supply is increased), a delay time of the main invert path is reduced and the Nl MOS transistor 110 is more strongly turned on so that it takes more time to invert the state of a latch, thereby entirely being compensated to have a predetermined delay time.

[31] In the meanwhile, even in the case of the Pl MOS transistor 200, the gate of the

PMOS transistor is fixed as V_TH, and the Pl MOS transistor 200 is weakly turned on when the gate strength of the Pl MOS transistor 200 becomes V_DD-2V_TH and V_DD becomes low. However, when V_DD is increased, the driving force of the PMOS is raised to be strongly latched, such that it takes more time to invert the previous state. Therefore, even though V_DD is increased to reduce the delay time of the main inverter, the Pl MOS transistor 200 is entirely delayed constantly.

[32] FIG. 7 is a diagram showing an example where a complementary biasing circuit 100 of a delay cell is implemented using MOS diodes according to an exemplary embodiment of the present invention. Referring to FIG. 7, the complementary biasing circuit indicated by reference numeral 100 of FIG. 6 is implemented using MOS diodes 101 and 102. In other words, a gate and a drain of the NMOS transistor 102 are connected to each other to be connected to V_DD and a resistor is connected to a source thereof to be grounded, thereby allowing V_DD-V_TH to be applied to the gate of the Nl transistor 110. Also, the gate and drain of the PMOS transistor 101 are connected to each other and a resistor is connected to the source thereof to be connected to V_DD, thereby allowing V_DD-V_TH to be applied to the gate of the Pl transistor 200.

[33] The complementary biasing circuit shown in FIG. 7 has an advantage that it can be simply implemented with MOS diodes, but has disadvantages that DC current always flows and it cannot sufficiently rapidly respond to the high-frequency power noise even though it controls a predetermined delay time against low-frequency power noise.

[34] FIG. 8 is a diagram showing a constitution of a delay cell according to another embodiment of the present invention. Referring to FIG. 8, if PMOS 101 and NMOS 102 transistors are connected, respectively, as shown in the drawing, and input waveforms D and DB are connected to the respective gates, a desired biasing operation can be performed during a half-period after the input waveform D is transitioned to be high.

[35] In other words, the gate and drain of the NMOS transistor 102 are connected to each other to be connected to V_DD and the source thereof is connected to the Nl transistor 110, thereby allowing V_DD-V_TH to be applied to the gate of the Nl transistor 110. Furthermore, the gate and drain of the PMOS transistor 101 are connected to each other to be grounded to a GND and the source thereof is connected to the gate of the Pl transistor 200, thereby allowing V_DD-V_TH to be applied to the gate of the Pl transistor 200.

[36] Herein, the gate voltage of the PMOS 200 is actually set to be higher than V_TH, wherein this is affected by a body effect since the source is not V_DD- However, it is preferable that the gate voltage of the PMOS becomes high. This is the reason that the object is that the Pl PMOS 200 is weakly turned on at V_DD=1-2V. However, the complementary biasing circuit shown in FIG. 8 as an embodiment of the present invention has a problem that a situation where the gates of the Pl MOS 200 and the Nl MOS 110 are floated is generated.

[37] As an exemplary embodiment of the power supply circuit according to the present invention, a resistor is connected to the source of the PMOS transistor where gate and drain are connected to be grounded to be connected to V_DD and a source node is connected to the gate of the biasing PMOS transistor, thereby allowing V_TH to be applied, and a resistor is connected to the source of the NMOS transistor 101 where gate and drain are connected to be connected to V_DD to ground GND and a source node is connected to the gate of the biasing NMOS transistor, thereby allowing V_DD- V_TH to be applied.

[38] FIG. 9 is a diagram showing a structure of a delay cell according to another embodiment of the present invention. Referring to FIG. 9, complementary biasing circuits 103 and 104 are further included on the right side of the delay cell in order to perform the same biasing operating after an input D is transitioned to be low. In a current source of a pseudo-differential pair, a Nl transistor 111 and a N2 transistor 112 are constituted in parallel, and a Pl transistor 201 and a P2 transistor 202 are constituted in parallel. However, the complementary biasing circuit of FIG. 9 also has the gate floating situation so that it will be solved in the following manner. [39] FIG. 10 is a diagram showing a structure of a delay cell according to another embodiment of the present invention. Referring to FIG. 10, in order to solve the situation where gates of Pl MOS 201 and P2 MOS 202, and gates of Nl MOS 111 and N2 MOS 112 are floated, the positions of the PMOS and NMOS are switched and are then connected.

[40] In other words, the source of the NMOS transistor 103' where source and gate are connected to each other is connected to V_DD, and DB is connected to the gate. Also, the source of the POMOS transistor 104' where source and gate are connected to each other is connected to GND, and DB is connected to the gate. The drains of the NMOS transistor 103' and the PMOS transistor 104' are connected to each other to be connected to a current source N2 transistor 112 of a pseudo-differential pair and a gate of a P2 transistor 202.

[41] In the same manner, the source of the NMOS transistor 102' where source and gate are connected to each other is connected to V_DD, and D is connected to the gate. Also, the source of the POMOS transistor 101' where source and gate are connected to each other is connected to GND, and D is connected to the gate. The drains of the NMOS transistor 102' and the PMOS transistor 101' are connected to each other to be connected to a current source Nl transistor 111 of a pseudo-differential pair and a gate of a Pl transistor 201.

[42] FIG. 11 is a diagram where the circuit of FIG. 11 is re-constituted according to an exemplary embodiment of the present invention. Reviewing the constitution of a biasing circuit, it has an inverter structure, but sources of NMOS transistors 103' and 102' are connected to V_DD and sources of PMOS transistors 101' and 104' are connected to GNDdp. The output of a complementary biasing circuit connected to D drives gates of a Nl transistor 111 and a Pl transistor 201, and an output of the complementary biasing circuit connected to DB is connected to gates of a P2 transistor 202 and a N2 transistor 112.

[43] As an exemplary embodiment of the present invention, a power supply circuit 100 connects DB to the gate, connects a source node of the PMOS transistor 101 where drain and gate are connected to be grounded to the gate of the biasing PMOS transistor to apply V_TH, applies D to the gate, and connects a source node of the NMOS transistor 101 where drain and gate are connected to be connected to V_DD to the gate of the biasing NMOS transistor, thereby allowing V_DD-V_TH to be applied.

[44] As an exemplary embodiment of the present invention, complementary biasing

PMOS transistors 201 and 202 and complementary biasing NMOS transistors 111 and 112 each are additionally connected in parallel, respectively, and the power supply circuit connects DB to gate of the NMOS transistor 103' and the PMOS transistor 104', connects the source of the NMOS transistor 103' to V_DD, connects the source of the PMOS transistor 104' to GND, puts together the drains of the NMOS transistor 103' and the PMOS transistor 104' to connect the output thereof to the gate of one PMOS transistor 201 and 202 of biasing transistors configured of the two PMOS transistors and the gate of one NMOS transistor 111 and 112 of biasing transistors configured of the two NMOS transistors, thereby allowing V_TH to be applied. The power supply circuit connects DB to gate of the NMOS transistor 102' and the PMOS transistor 101', connects the source of the NMOS transistor 102' to V_DD, connects the source of the PMOS transistor 101' to GND, puts together the drains of the NMOS transistor 102' and the PMOS transistor 101' to connect the output thereof to the gate of the other PMOS transistor 202 and 201 of biasing transistors configured of the two PMOS transistors and the gate of the other NMOS transistor 112 and 111 of biasing transistors configured of the two NMOS transistors, thereby allowing V_DD-V_TH to be applied.

[45] FIG. 12 is a diagram showing a constitution of a digitally controlled oscillator implemented by applying a delay cell according to an exemplary embodiment of the present invention. In the present invention, an adjacent tap having disparity t_D is selected on a delay line for a coarse tuning and an interpolation circuit 300 is constituted for a fine tuning.

[46] The present invention uses an interpolation method, having monotone increase/ decrease function property while output phase performing tuning between maximum and minimum. As shown in FIG. 12, it is preferable that the unit delay cell 200 of the digitally controlled oscillator is implemented using the delay cell shown in FIGS. 10 and 11.

[47] The aformentioned somewhat widely improves the characteristics and technical advantages of the present invention so that the scope of the invention to be described later can be more clearly understood. The additional characteristics and technical advantages that constitute the scope of the present invention will be described below. The features that the disclosed concept and specific embodiments of the present invention can be instantly used as a basis designing or correcting other structure for accomplishing a similar object with the present invention should be recognized by those skilled in the art.

[48] Further, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. Industrial Applicability [49] With the delay cell architecture according to the present invention, which is applicable to the digitally controlled oscillator (DOC) that constitutes all circuits using digital circuits, the output waveform frequency of the DOC is not affected by the fluctuation in power supply voltage, making it possible to significantly reduce the generation of jitter noise.

Claims

[1] A digitally controlled oscillator which is implemented by a cascade of a plurality of delay cells, the delay cell including input terminals D and DB and output terminals Q and QB, wherein the delay cell includes: a first inverter that includes a PMOS transistor 130 and an NMOS transistor 120 whose gates receive the signed from the input D and whose drains output the output QB; a second inverter that includes a PMOS transistor 150 and an NMOS transistor 140 whose gates receive the signed from the input DB and whose drains output the output B; a pseudo-differential pair comprising a pair of NMOS transistors 160 and 170 and a pair of PMOS transistors 180 and 190, the gates of the NMOS transistors 160 and 170 being connected to the drains of the corresponding NMOS transistors 170 and 160, respectively, the gates of the PMOS transistors 180 and 190 being connected to the drains of other PMOS transistors 190 and 180, respectively, the drain outputs of the NMOS transistors 160 and 170 being connected to Q and QB, respectively to connect the output Q of the differential pair circuit to the output of the second inverter and to connect the output QB to the output of the first inverter; a complementary biasing PMOS transistor whose source is connected to V_DD power supply line and whose drain is connected between sources of the PMOS transistors 180 and 190; and a complementary biasing NMOS transistor whose source is connected to GND line and whose drain is connected between sources of the NMOS transistors 160 and 170, wherein V_TH (threshold voltage of transistor) is applied to the complementary biasing PMOS transistor and V_DD-V_TH is applied to the gate of the NMOS transistor.

[2] The digitally controlled oscillator according to claim 1, wherein the power supply circuit connects V_DD to a source of a PMOS transistor 101 through a resistor where gate and drain are connected to be grounded and connects a source node to the gate of the complementary biasing PMOS transistor in order to apply V_TH, and connects a source of an NMOS transistor 101 to the GND through a resistor where gate and drain are connected and tied to V_DD and connects a source node to the gate of the complementary biasing NMOS transistor in order to apply V_DD-V_TH.

[3] The digitally controlled oscillator according to claim 1, wherein the power supply circuit connects DB to the gate and connects the source node of the PMOS transistor 101 to the gate of the complementary biasing PMOS transistor to apply V_TH where drain and gate are tied to the GND, and applies D to the gate and connects the source node of the NMOS transistor 101, where drain and gate are connected to be connected to V_DD, to the gate of the complementary biasing NMOS transistor to apply V_DD-V_TH.

[4] The digitally controlled oscillator according to claim 1, further comprising two in parallel the complementary biasing PMOS transistors 201 and 202 and the complementary biasing NMOS transistors 111 and 112, and the power supply circuit connects DB to the gates of an NMOS transistor 103' and a PMOS transistor 104', connects the source of the NMOS transistor 103' to V_DD, connects the source of the PMOS transistor 104' to GND, ties together the drains of the NMOS transistor 103' and the PMOS transistor 104' to connect the output thereof to the gate of one PMOS transistor 201 and 202 of complementary biasing transistors including the two PMOS transistors and the gate of one NMOS transistor 111 and 112 of complementary biasing transistors including the two NMOS transistors, thereby applying V_TH, and connects D to the gates of an NMOS transistor 102' and a PMOS transistor 101', connects the source of the NMOS transistor 102' to V_DD, connects the source of the PMOS transistor 101' to GND, puts together the drains of the NMOS transistor 102' and the PMOS transistor 101' to connect the output thereof to the gate of the other PMOS transistor 202 and 201 of complementary biasing transistors including the two PMOS transistors and the gate of the other NMOS transistor 112 and 111 of complementary biasing transistors including the two NMOS transistors, thereby applying V_DD-V_TH.