CN102270985A

CN102270985A - Configurable differential delay unit circuit

Info

Publication number: CN102270985A
Application number: CN2010101930103A
Authority: CN
Inventors: 李少青; 段志奎; 赵振宇; 张民选; 郭阳; 陈吉华; 马卓; 张明; 郑涛; 孙岩; 何小威; 乐大珩; 谭晓强; 张均安
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2010-06-07
Filing date: 2010-06-07
Publication date: 2011-12-07
Anticipated expiration: 2030-06-07
Also published as: CN102270985B

Abstract

The invention discloses a differential delay unit circuit which has a configurable property and is applied to variable-loop voltage-controlled oscillators. Delay units can change signal propagation paths under the control of an input selecting circuit, and the mode based on multiplexing the delay units changes the stage number of the delay units in the loop, so as to form a configurable annular oscillator with the lowest expenditure, provide different types of gains to voltage-controlled oscillators and increase the range of adjustment. The configurable differential delay unit circuit disclosed by the invention comprises an input selecting circuit, an input circuit and a load circuit.

Description

A kind of configurable differential delay element circuit

Technical field

The invention belongs to the integrated circuit (IC) design field, be applied to the voltage controlled oscillator design, be specifically related to a kind of configurable differential delay element circuit structure.

Background technology

(Voltage-controlled Oscillator VCO), is widely used in the various integrated circuits voltage controlled oscillator.Annular voltage controlled oscillator is a kind of as voltage controlled oscillator, and it is simple in structure, area overhead is little, it is integrated to be easy to, by the designer is favored.In phase-locked loop circuit, normally regulate output frequency by changing control voltage Vc, the ratio of the scope of VCO output frequency and Vc adjustable range is referred to as the VCO gain.If the VCO gain is higher, then in phase-locked loop, introduce noise easily; Otherwise,, may reduce the phase-locked loop frequency scope and prolong locking time if the VCO gain is lower.Therefore, PLL noise, frequency range and locking time are relevant with the VCO gain.Fig. 4 variable circulation circuit voltage-controlled oscillator example that conventional differential delay unit (as shown in Figure 1) constitutes of promptly serving as reasons, this circuit has the following disadvantages:

1. conventional differential delay unit shown in Figure 1, the input signal port is fixed, no multiplexing capacity, the loop that constitutes lacks enough flexibilities thus;

2. the ring oscillator that is made of conventional differential delay unit, its delay cell progression are normally fixing, and when the gain of VCO is low, the adjustable range of output frequency is restricted;

3. the variable loop oscillator that constitutes by conventional differential delay unit, the delay cell number that needs is numerous, design overhead is bigger, with the structure among Fig. 4 is example, because conventional differential delay unit can't be multiplexing, realize that delay cell progression is 3,4,5,6,7,8,9 and 10 oscillator, need constitute 8 oscillating loops respectively, need 52 delay cells altogether.

Causing the basic reason of the problems referred to above to be to constitute the delay cell of loop can't be multiplexing.Expansion VCO realizes variable circulation circuit voltage-controlled oscillator, is the effective way that addresses the above problem.Therefore, realize the low variable circulation circuit voltage-controlled oscillator of expense, a kind of configurable delay cell need be provided, configurable with the supporting signal path.

Summary of the invention

Deficiency at conventional differential delay unit, the present invention has designed input selection circuit on the basis of conventional differential delay unit, improved input circuit, realized a kind of configurable differential delay unit with multiplexing capacity, its major technology starting point is:

1. the signal input port of the differential delay unit of routine is expanded, the differential input end mouth is replaced fixing differential input end mouths, realized the alternative of signal path with many;

2. the current path of the differential delay unit of routine is expanded, replaced single fixing tail current source, realize the alternative of operating current with configurable multiple current source.

Based on above-mentioned technological thought, the configurable differential delay unit after the improvement is compared with conventional differential delay unit as shown in Figure 2, and this delay cell has following advantage:

1. the input of delay cell can be selected, conventional differential delay unit as shown in Figure 1, after being applied to voltage controlled oscillator, its input can only be the output of previous stage delay cell, be input In+ and In-, and the input of the delay cell after improving can be selected according to control end C1 and C2, work as C1=1, during C2=0, then select In1+ and In1-as input, and work as C1=0, during C2=1, then select In2+ and In2-as input, and delay cell disclosed by the invention also has the ability that input port number and input selection circuit are expanded, can expand to a plurality of difference inputs to as input;

2. the variable circulation circuit voltage-controlled oscillator that constitutes of the delay unit circuit among use Fig. 2, has multiple gain, for example, realize that with this differential delay unit delay cell progression is 3,4,5,6,7,8,9,10 ring oscillator, its gain as shown in Figure 3, can be according to external control signal, between the VCO different gains of the curve representative of L=3, L=4, L=5, L=6, L=7, L=8, L=9, L=10, regulate, can realize quick frequency conversion by changing oscillator gain, its adjustable range also is expanded;

3. use variable circulation circuit voltage-controlled oscillator that delay unit circuit disclosed by the invention constitutes to compare with the voltage controlled oscillator that uses conventional delay cell and have an identical loop number, needed area significantly reduces, as shown in Figure 4, utilize 52 delay cells of 8 loops needs among conventional differential delay unit realization Fig. 4 among Fig. 1, i.e. 364 transistors, and as shown in Figure 5, use delay unit circuit disclosed by the invention and conventional differential delay unit to realize 8 loops jointly, only need 10 delay cells, totally 122 transistors, area overhead reduces significantly.

Description of drawings

The conventional differential delay cellular construction of Fig. 1;

Fig. 2 configurable differential delay cellular construction disclosed by the invention;

Fig. 3 gives an example based on the gain curve of the voltage controlled oscillator that configurable differential delay disclosed by the invention unit constitutes;

The variable circulation circuit voltage-controlled oscillator that Fig. 4 constitutes based on conventional differential delay unit;

The variable circulation circuit voltage-controlled oscillator structure that Fig. 5 constitutes based on configurable differential delay disclosed by the invention unit.

Embodiment

Describe the circuit structure and the course of work of configurable differential delay disclosed by the invention unit in detail below in conjunction with accompanying drawing.

Disclosed by the invention is a kind of configurable differential delay element circuit, it is characterized in that: comprise input selection circuit, input circuit and load circuit, specifically by PMOS pipe M1, M2, M3, M4, M9, M12, NOMS pipe M5, M6, M7, M8, M10, M11, M13, M14, M15, M16 and inverter INV1, INV2 form; Specifically be characterised in that: M5 and M8 form source-coupled to pipe, its grid connects difference input In1+ and In1-respectively, its drain electrode connects difference output Out-and Out+ respectively, its source electrode is connected to the drain electrode of M14, the source electrode of M14 is connected to ground, its grid is connected to the source electrode of M10, the drain electrode of M13 and the drain electrode of M9, the drain electrode of M10 connects bias voltage Vb, its grid connects control end C1, the source electrode of M9 connects bias voltage Vb, its grid connects the output of inverter INV1, the source ground of M13, its grid connects the output of INV1, the input of INV1 connects control end C1, M6 and M7 form source-coupled to pipe, its grid connects difference input In2+ and In2-respectively, its drain electrode connects difference output Out-and Out+ respectively, its source electrode is connected to the drain electrode of M15, the source ground of M15, its grid connects the source electrode of M11, the drain electrode of M16 and the drain electrode of M12, the drain electrode of M11 connects bias voltage Vb, its grid connects control end C2, the source electrode of M12 connects bias voltage Vb, and its grid connects the output of inverter INV2, the source ground of M16, its grid connects the output of INV2, the input of INV2 connects control end C2, and the source electrode of M1 connects power supply, and its grid connects control voltage Vc, its drain electrode connects difference output end Out-, the M2 source electrode connects power supply, and its grid connects control voltage Vc, and its drain electrode connects difference output end Out+, the grid of M3 is connected difference output end Out-with drain electrode, its source electrode connects power supply, and the grid of M4 is connected difference output end Out+ with drain electrode, and its source electrode connects power supply.

As shown in Figure 2, the present invention is a kind of configurable differential delay element circuit, when port C1=1, the C2=0 of module are selected in input, delay cell be input as In1+ and In1-, promptly M1, M2, M3, M4, M5, M8, M9, M10, M13, M14 and inverter INV1 constitute the differential delay unit and enter ring oscillator; When port C1=0, the C2=1 of module are selected in input, delay cell be input as In2+ and In2-, be that M1, M2, M3, M4, M6, M7, M15, M12, M11, M16 and inverter INV2 formation differential delay unit enter ring oscillator, promptly by whether conducting of C1 and C2 control tail current pipe M14 and M15, the input of selecting configurable delay cell is In1+/In1-or In2+/In2-, and the selection control of input can change delay cell progression in the ring oscillator.As shown in Figure 5, in oscillator, can realize that by control signal B1B2B3B4B5B6B7B8 delay cell progression is variable in the ring oscillator, as shown in table 1 below.When control signal was 10101001, ten delay cells all entered loop among Fig. 5, constituted ten grades of ring oscillators; When control signal was 10101010, the output that configurable delay cell 4 is selected delay cell 6 was as input, and

delay cell

1,2,3,4,6,7,8,9,10 constitutes nine grades of ring oscillators.According to foregoing description, control by C1 in the delay cell and C2, configurable

differential delay unit

4,7,8,9 can repeatedly circularize oscillator with other groups of delay cells, realizes that delay cell progression is variable in the ring oscillator, makes voltage controlled oscillator have multiple gain.Use the variable loop oscillator of configurable differential delay unit, can select gain that output frequency is carried out quick adjustment according to control signal.

Table 1

Control signal B1B2B3B4B5B6B7B8	The delay cell combination	The VCO loop structure
			10101001	1、2、3、4、5、6、7、8、9、10	10 delay cell loop structures
10101010	1、2、3、4、6、7、8、9、10	9 delay cell loop structures
			01101001	2、3、4、5、6、7、8、9	8 delay cell loop structures
01101010	2、3、4、6、7、8、9	7 delay cell loop structures
			xx011001	3、4、5、6、7、8	6 delay cell loop structures
xx011010	3、4、6、7、8	5 delay cell loop structures
			xxxx0101	4、5、6、7	4 delay cell loop structures
xxxx0110	4、6、7	3 delay cell loop structures

Many ring oscillators have used configurable

differential delay unit

4,7,8,9 and conventional

differential delay unit

1,2,3,5,6,10 among Fig. 5, can calculate this oscillator according to Fig. 1 and Fig. 2 and use 122 transistors.By having the oscillator that delay cell progression equates in identical loop number and the loop in the comparison diagram 4, use the voltage controlled oscillator of configurable differential delay unit to save 242 transistors as can be known.Promptly realized reducing 66.5% area overhead by multiplexing configurable

differential delay unit

4,7,8,9.

In sum, the voltage controlled oscillator of realizing based on configurable differential delay unit can obtain multiple gain, has wide tuning range, low locking time, characteristics such as low area expense with its phase-locked loop that serves as the basis is realized.

Claims

1. configurable differential delay element circuit is characterized in that:

Comprise input selection circuit, input circuit and load circuit, specifically by PMOS pipe (M1), (M2), (M3), (M4), (M9), (M12), NOMS pipe (M5), (M6), (M7), (M8), (M10), (M11), (M13), (M14), (M15), (M16) and inverter (INV1), (INV2) form; Specifically be characterised in that: (M5) and (M8) form source-coupled pipe, its grid connects difference input (In1+) and (In1-) respectively, its drain electrode connects difference output (Out-) and (Out+) respectively, its source electrode is connected to the drain electrode of (M14), (M14) source electrode is connected to ground, its grid is connected to the source electrode of (M10), (M13) drain electrode and drain electrode (M9), (M10) drain electrode connects bias voltage (Vb), its grid connects control end (C1), (M9) source electrode connects bias voltage (Vb), its grid connects the output of inverter (INV1), (M13) source ground, its grid connects the output of (INV1), (INV1) input connects control end (C1), (M6) and (M7) form source-coupled to pipe, its grid connects difference input (In2+) and (In2-) respectively, its drain electrode connects difference output (Out-) and (Out+) respectively, its source electrode is connected to the drain electrode of (M15), (M15) source ground, its grid connects the source electrode of (M11), (M16) drain electrode and drain electrode (M12), (M11) drain electrode connects bias voltage (Vb), its grid connects control end (C2), (M12) source electrode connects bias voltage (Vb), its grid connects the output of inverter (INV2), (M16) source ground, its grid connects the output of (INV2), (INV2) input connects control end (C2), (M1) source electrode connects power supply, its grid connects control voltage (Vc), its drain electrode connects difference output end (Out-), (M2) source electrode connects power supply, its grid connects control voltage (Vc), its drain electrode connects difference output end (Out+), (M3) grid is connected difference output end (Out-) with drain electrode, its source electrode connects power supply, (M4) grid is connected difference output end (Out+) with drain electrode, and its source electrode connects power supply.