WO2009134844A1 - Signalisation synchrone avec une source haute vitesse - Google Patents

Signalisation synchrone avec une source haute vitesse Download PDF

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Publication number
WO2009134844A1
WO2009134844A1 PCT/US2009/042044 US2009042044W WO2009134844A1 WO 2009134844 A1 WO2009134844 A1 WO 2009134844A1 US 2009042044 W US2009042044 W US 2009042044W WO 2009134844 A1 WO2009134844 A1 WO 2009134844A1
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WIPO (PCT)
Prior art keywords
transition
data
integrated circuit
circuit device
timing signal
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PCT/US2009/042044
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English (en)
Inventor
Jared Zerbe
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Rambus Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Rambus Inc. filed Critical Rambus Inc.
Publication of WO2009134844A1 publication Critical patent/WO2009134844A1/fr
Priority to US12/868,571 priority Critical patent/US8514952B2/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization

Definitions

  • the present embodiments generally relate to techniques for communicating between a transmitter and a receiver, for example, disposed on separate integrated circuit devices. More specifically, the present embodiments relate to a method and system for source-synchronous signaling across a communication channel.
  • FIG. 1 presents a block diagram illustrating a system which transmits data and an associated clock signal over a communication channel.
  • FIG. 2A illustrates the phase relationships between the received clock edges and the received data transitions at an integrating receiver.
  • FIG. 2B illustrates a technique for increasing the integration output during the data sampling process by using windowing-based integration.
  • FIG. 3A presents a block diagram illustrating a communication system using both transmitter-side and receiver-side delay elements.
  • FIG. 3B illustrates how a noise band in the delayed data is adjusted relative to the sense edge.
  • FIG. 3C illustrates how the precharge edge is adjusted relative to a noise band in the delayed data.
  • FIG. 3D presents a flowchart illustrating the process of calibrating the two predetermined delay times in the communication system.
  • FIG. 3E illustrates an embodiment of communication system 300 in order to accommodate double data rate (DDR) operation.
  • DDR double data rate
  • FIG. 3F presents a block diagram illustrating a communication system which is a simplified version of communication system 300.
  • FIG. 4 presents a block diagram illustrating an embodiment of a memory system, which includes at least one memory controller and one or more memory devices. DETAILED DESCRIPTION
  • Source synchronous signaling involves transmitting a timing reference, in the form of a strobe signal or clock signal, along with data such that the timing reference can then be used at the receiver for capturing the data.
  • clock edge transitions used to generate the beginning and ending of a particular unit bit time at the transmitter are then used to recover the same bit at the receiver. In some embodiments, this is achieved by using two delay elements, with one placed on the transmitter-side and the other on the receiver-side.
  • FIG. 1 presents a block diagram illustrating a system which transmits data 102/103 and an associated clock 104 over a communication channel.
  • data 102/103 and clock 104 are source-synchronized at the same device to reduce timing skews between the two signals.
  • clock 104 includes a pair of consecutive clock edges: a falling edge 106 followed by a rising edge 108, which are used to sample a corresponding pair of data transitions 110 and 112 using a pair of falling and rising-edge triggered flip-flops and interleaving even and odd data streams 102' and 103' by means of an output multiplexer into a single data stream which feeds into link 114.
  • data values resulting from data transitions 110 and 112 are output-timed via the output mux select input and clock edges 106 and 108 and then transmitted over a link 114.
  • the data is then received at the receiver to form received data 116, which includes data transitions 118 and 120 corresponding to the data resulting from transitions 110 and 112 but whose timing was set by the output mux and clock edges 106 and 108. Further data transitions and clock edges can be extrapolated beyond the simple pair shown. Note also that the received data transitions become "noisy" due to inter-symbol-interference (ISI), jitter, and other sources of noise in the transmission system.
  • ISI inter-symbol-interference
  • noisy data transitions 118 and 120 are characterized by a noise band which is significantly broader than the original clock edges 106 and 108. Note that this noise band is comprised of invalid data which does not provide the correct data value at a given sampling phase. As a result, the data eye 122 between the two noise bands, which defines a consistently valid data region for sampling, becomes narrower.
  • clock 104 is transmitted over a link 115 and is received at the receiver to form a received clock 124, which includes clock edges 126 and 128 corresponding to clock edges 106 and 108, respectively.
  • the same clock edge which generates the data transition on the transmitter is also used to recover the data associated with the data transition at the receiver.
  • clock edges 126 and 128 are used to recover the data in data eye 122 in FIG. 1.
  • recovering data at the receiver involves using a precharge-sense technique based on a pair of consecutive clock edges.
  • first clock edge 126 can be used as a precharge edge for starting an integration operation on the received data 116 while the second clock edge 128 can be used as a sense edge to trigger a sampling operation.
  • the time interval between the precharge edge and the sense edge defines a sampling window.
  • FIG. 2A illustrates phase relationships between the received clock edges and the received data transitions at the receiver.
  • the release of the precharge edge 202 controls the beginning of an integration window 204
  • the sense edge 206 activates a sense operation which samples data values from the integration output and thereby controls the end of integration window 204.
  • sense edge 206 releases a sense amplifier without stopping the integration.
  • the duration of integration time before sampling is set by integration window 204.
  • the clock edges are substantially aligned with the original data transitions in the transmitter (as shown in FIG. 1)
  • the precharge edge 202 and sense edge 206 fall in the middle of the noise bands 208 and 210 associated with the data transitions at the receiver. Consequently, integration window 204 is wider than the valid data eye 212 defined by the inner edges of the noise bands 208 and 210.
  • portions of the noise bands are integrated at both ends of the integration window 204, which can give rise to a significant drop in the integration output 214. As illustrated in FIG. 2A, this drop can affect the sense value at sense edge 206.
  • FIG. 2B illustrates a technique for increasing the integration output during the data sampling process by using windowing-based integration. Note that by delaying precharge edge 202 relative to the first noise band 208 and, while adjusting sense edge 206 to occur before the second noise band 210, the new integration window 216 avoids integration within the noise bands. Because the integration is performed only on the valid data within data eye 212, the integration output and thus the sampled voltage 218 can be significantly increased, and in fact maximized to the extent possible by the width of the valid data eye 212. Embodiments relating to windowing-based integration are described in more detail below.
  • the transmitter-side clock edges and the corresponding receiver-side clock edges are "colored.”
  • the individual clock edges which generate the beginning and ending of a particular bit cell at the transmitter are transmitted in a source-synchronous fashion to the receiver and then the same two edges are used to recover the same bit cell at the receiver.
  • this clock-edge "coloring" is achieved by using two delay elements, with one placed on the transmitter-side and the other on the receiver-side. As will be shown in more detail below, using these two delay elements facilitates performing arbitrary phase alignment between the clock and the corresponding data at the receiver. Consequently, if a sampled receiver is used, the edge used to sample the center of the data eye at the receiver may correspond to the edge which started the data transition at the beginning of the data eye or the edge that created the edge transition at the end of the data eye.
  • FIG. 3A presents a block diagram illustrating a communication system 300 using both transmitter-side and receiver-side delay elements.
  • system 300 includes a transmitter 304 that receives even data stream 306, odd data stream 307 and clock 308.
  • a first data transition 310 in odd data stream 307' is followed by a second data transition 312 in even data stream 306'
  • clock 308 includes a clock window formed by a falling clock edge 314 followed by a rising clock edge 316.
  • system 300 can include a single-data-rate (“SDR”)-base system, a quad-data-rate (“QDR”)-based system, an octal data rate (“ODR”), or systems based on other types of clocking modes.
  • SDR single-data-rate
  • QDR quad-data-rate
  • ODR octal data rate
  • system 300 is a source-synchronous signaling system wherein data 309 and clock 315 are source-synchronized signals.
  • clock edges 314 and 316 are used to time the transmission of data resulting from transitions 310 and 312, respectively.
  • Transmitter 304 transmits even data stream 306 and odd data stream 307, which are interleaved together, as well as clock 308 over channel 318 through a data link 320 and a clock link 322, respectively.
  • even data stream 306 and odd data stream 307 pass through a pair of odd/even flip-flops and then through an output multiplexer (omux) 305, which combines the two data streams, before passing through a data buffer 317 to reach a first output node 309, where the combined data is transmitted onto data link 320.
  • clock 308 passes through a 0/1 -tied output multiplexer (omux) 311 and a clock buffer 313 to reach a second output node 315, where clock 308 is transmitted onto clock link 322.
  • the combined data 306/307 and clock 308 are received at a receiver 324 as received data 326 and received clock 328, respectively.
  • the combined data 306/307 and clock 308 are transmitted over the same link between transmitter 304 and receiver 324. This can be accomplished by transmitting the data and clock signals over the same link in different modes.
  • the received data 326 includes a first noise band 330 corresponding to data resulting from transition 310 with timing from clock edge 314 which is followed by a second noise band 332 corresponding to data resulting from transition 312 with timing from clock edge 316.
  • received clock 328 includes a clock edge 334 associated with first noise band 330, followed by a clock edge 336 associated with second noise band 332.
  • Receiver 324 also includes the adjustable-sampling circuit 302, which comprises an integrator 338 coupled to a sense circuit 340. Integrator 338 receives data 326 as data input and a clock 342 that controls the start of the integration operation. The output of integrator 338 is coupled to the data input of sense circuit 340, which directly receives clock 328 to control the sense operation which effectively ends the integration operation. In some embodiments, sense circuit 340 is an edge-triggered sense circuit. [0023] Note that system 300 also includes a transmitter-side delay element 344 and a receiver-side delay element 346. Each of these delay elements can be implemented using a vernier delay element, a delay-line, a PLL, or other delay means.
  • the two different delay elements can use elements in-common, and in some cases, share some or all calibration codes in common.
  • the two delay elements generate two relative timing delays which can be used to adjust the phase relationships between received data 326 and received clock 328, so that adjustable-sampling circuit 302 operates with a window within the data eye 348 between noise bands 330 and 332.
  • the transmitter (such as transmitter 304) can use a phase mixer extracting arbitrary phase angles from a transmitter-side PLL in order to have low-jitter clocks with arbitrary phase position.
  • some embodiments may use one or the other of delay elements 344 and 346 and not both and thereby experience some but not all of the benefits of a window tuned to eliminate both noise bands.
  • transmitter-side delay element 344 delays the original clock 308 by a first predetermined delay time to generate a delayed clock 352. Delayed clock 352 is then used to clock even data stream 306 and odd data stream 307 through a pair of flip- flops, which delays the combined output data relative to the original transmitter clock 308 by the same predetermined delay time. Consequently, received clock 328 thus leads the received data 326 by the same amount because of delay element 344.
  • the second clock edge 336 of the transmitted clock 328 is a sense edge which is coupled to the clock of sense circuit 340. Because of the first predetermined delay time, the second clock edge 336 triggers sensing of the received data 326 earlier than it would in a traditional source-synchronous system, thus facilitating the movement of it 'inside' the noise band 332.
  • FIG. 3B illustrates how noise band 332 in the delayed data 326 is adjusted relative to sense edge 336. Note that without applying the delay to clock 308, sense edge 336 triggers the sense operation within the noise band 332.
  • a second noise band 332 associated with data transition 312 is delayed relative to sense edge 336, which causes sense edge 336 to shift relative to the data earlier toward the center of the data eye 348 defined by the inner edges of the noise bands 330 and 332.
  • the amount of delay is calibrated at the first delay element 344 so that sense edge 336 substantially aligns with the beginning (edge) of the second noise band 332 as shown in FIG. 3B.
  • the edge of noise band 332 can be defined based on where an acceptable bit- error-rate is achieved. In some embodiments, other techniques are used to define the edge of noise band 332. Consequently, the exactly location of the edge of noise band 332 may vary depending on the particular technique that is used.
  • the receiver-side delay element 346 delays clock 328 by a second predetermined delay time to produce the delayed clock 342, which thus contains within it a delayed version of clock edge 334.
  • the delayed version of clock edge 334 provides a precharge edge which determines the start of the integration operation on integrator 338.
  • FIG. 3C illustrates how the precharge edge (provided by the delayed version of clock edge 334) is adjusted relative to noise band 330 in delayed data 326. Note that without applying the delays to both clock 328 and data 326, the precharge edge is positioned relative to noise band 330 as shown in FIG. 3B. If a delay is applied to data 326 but no delay is applied to clock 328, in some embodiments the precharge edge is positioned relative to noise band 330 as shown in FIG. 3C which is to the left of noise band 330. Alternately with no delay applied to data 326 the precharge edge can be positioned in the center of noise band 330 similar to the sense case. In the embodiment illustrated in FIG.
  • the precharge edge is delayed by delay element 346 so that it moves toward data eye 348, which is defined by the inner edges of the noise bands.
  • the amount of delay is calibrated at second delay element 346 so that the precharge edge substantially aligns with the end of the first noise band 330 as shown in FIG. 3C.
  • the edge of noise band 330 can be defined based on where an acceptable bit-error-rate is achieved.
  • other techniques are used to define the edge of noise band 330. Consequently, the exactly location of the edge of noise band 330 may vary depending on the particular technique that is used.
  • a sense-edge delay at receiver 324 is achieved by delaying the input data from the transmitter side, while the precharge-edge delay is achieved by delaying the received clock 328 at the receiver side.
  • This facilitates maintaining the association between clock edges 314 and 316 and data transitions 310 and 312, thereby facilitating alignment of the precharge edge and sense edge with data eye 348. Further precision in the placement of the edges is allowed by use of two separate signals of the same (DDR) clock rate at the receiver.
  • this delay and alignment technique does not require adding substantial delay to the clock as a method of deskewing clock and data by creating a skew whose phase would appear to be zero but is in fact 'rounded up' to become substantially an integer multiple of 1 -unit-interval ("UI") as is commonly done.
  • Maintaining matching (or 'coloring') between clock and data edges in this example, better facilitates high-speed operation by facilitating keeping sources of jitter and distortion in-common between individual edges of clock and data.
  • adjustable-sampling circuit 302 can include a control mechanism configured to disable/bypass the integrator 338 so that data 326 passes through integrator 338 to the sense circuit 340 without a substantial integration. This configuration is useful during the process of calibrating the delay on delay element 344 for aligning the sense edge with the data eye. Adjustable-sampling circuit 302 is switched back to the regular integrating-sampling mode when this calibration is complete. Alternately the sense circuit may be use to directly sample data with the integrator bypassed if higher performance is achieved this way.
  • FIG. 3D presents a flowchart illustrating the process of calibrating the two predetermined delay times in communication system 300.
  • the system first calibrates the first predetermined delay time to align the sense edge with data by performing sampling operations on the second noise band 332 at receiver 324 (step 301). More specifically, integrator 338 is disabled/bypassed or its integration window substantially reduced so that delayed data 326 passes through the integrator circuit to the sense circuit 340 without a substantial integration.
  • sense circuit 340 includes a sense amplifier. Sense circuit 340 samples second noise band 332 while moving sense edge 336 toward the beginning of noise band 332 by adding additional delay at delay element 344.
  • the calibration is complete when the sense output voltage is maximized, or alternately when the bit-error-rate is reduced to an acceptable level, which is defined by the number of errors received at adjusted phase position relative to the errors received if the sampler is positioned at the center of the valid data eye.
  • the system calibrates the second predetermined delay time to align the precharge edge with the data by performing an integration operation between the precharge edge (in the first noise band 330) and the previously calibrated sense edge (step 303). More specifically, integrator 338 is enabled so that adjustable-sampling circuit 302 is in a full- integration mode. Integrator 338 then starts to integrate from the precharge edge until the sense edge is reached. By adding more delay at delay element 346, precharge edge 334 is moved toward the end of noise band 330 and the integration voltage at the sense edge is increased.
  • the calibration is completed when the integrator output voltage is maximized, or alternately when the bit-error-rate is reduced to an acceptable level, which is defined by the number of errors received at adjusted phase position relative to the errors received if the sampler is positioned at the center of the data eye.
  • the delay used for precharge calibration can be a direct copy of the sense calibration or twice that of the value of the sense calibration. This method has the advantage of being simpler to implement and can be very effective for systems which have noise bands which are substantially equal.
  • both calibration sequences can be completed with arbitrary or predetermined data patterns, with the desire to be to have data patterns with frequency content representative of the data that is to be transmitted during normal operation, and thus generating noise bands representative of normal operation. Additional margin may be employed by the addition of some incremental delay to elements 344 or 346 beyond the calibrated value to accommodate the potential of jitter or increased noise bands during normal operation that were not represented during calibration.
  • FIG. 3E illustrates further detail to the aspects of communication system 300 required in order to accommodate a double data rate (“DDR") operation.
  • DDR double data rate
  • two substantially identical adjustable-sampling circuits 302-0 and 302-1 are concurrently used as two parallel sampling streams.
  • both adjustable-sampling circuits receive the same input data 326.
  • the two adjustable-sampling circuits receive complimentary clock signals 328-0 and 328-1, respectively, wherein clock signals 328-0 and 328-1 are inverted versions of each other from the same clock source 328.
  • each clock cycle is divided into two precharge-sense cycles, which are interleaved and separated into on the two sampled streams.
  • each of the clock signals has a 50/50 duty cycle.
  • clock signal 328-0 illustrated in FIG. 3E comprises two calibration sequences 354 and 356, wherein each of the calibration sequences is comprised of multiple DDR clock cycles.
  • Each DDR clock cycle further comprises a first edge which correlates to the release of precharge (referred to as a "p-type-edge”) followed by a second edge which correlates to the release of sense (referred to as an "s-type-edge").
  • p-type-edge a first edge which correlates to the release of precharge
  • s-type-edge a second edge which correlates to the release of sense
  • each calibration sequence is used to calibrate at least one of the clock edges (i.e., the precharge edge and the sense edge).
  • each of the calibration sequences 354 and 356 is used to calibrate both the precharge edge and the sense edge for alignment with the data eye.
  • calibration sequence 354 is used to calibrate the sense edge while calibration sequence 356 is used to calibrate the precharge edge, respectively.
  • calibration sequences 354 and 356 are separated by a period of regular operation 358, which is also comprised of precharge- sense cycles. The length of regular operation 358 may be predetermined or dynamically determined during system operation. Note that although six (three even and three odd) precharge-sense cycles are shown for each calibration sequence, fewer or more precharge- sense cycles may be used. Furthermore, although two calibration sequences are shown, more calibration sequences may be used during system operation.
  • precharge edges for odd and even samplers 302-0 and 302-1 can be independently created by different delay elements as shown in FIG 3E, or in an alternate embodiment could be created by use of a single delay element and complementary outputs feeding even and odd samplers.
  • FIG. 3F presents a block diagram illustrating a communication system 360 which is a simplified version of system 300.
  • system 360 includes substantially the same components as system 300, such a transmitter 362, a receiver 364, a channel 366 which further includes a data link 368 and a clock link 370.
  • System 360 also includes both a transmitter-side delay element 372 and a receiver-side delay element 374.
  • system 360 uses simply a sampling circuit 376 that includes a sensing circuit but without an integrator as in system 300.
  • the received data at receiver 364 is directly sampled without integration, and a delayed clock from delay element 374 is used to directly control the timing of sampling circuit 376 instead of controlling the start of integration operation on the received data.
  • this simplified receiver 364 may achieve sufficient data-clock alignment by using the two delay elements.
  • an alternate calibration technique can be used to adjust the delay elements 372 and 374 to find the extents of the data eye and center the sampling point of sampling circuit 376 for the largest timing margin.
  • DRAM source-synchronous dynamic random access memory device
  • Such system can be, but is not limited to, a mobile system, desktop computer, server, and/or a graphics application.
  • the DRAM may be, e.g., graphics double data rate (GDDR, GDDR2, GDDR3, GDDR4, GDDR5, and future generations, and double data rate DDR2, DDR3 and future memory types.
  • the source synchronous techniques described may be applicable to other types of memory, for example, Flash and other types of non volatile memory and static random access memory (SRAM).
  • One or more of the techniques or apparatus described herein are applicable to front side bus, (i.e., processor to bridge chip, processor to processor, and/or other types of chip-to-chip interfaces).
  • the two communicating integrated circuit IC chips i.e., the transmitter and receiver
  • the transmitter, receiver and the channel can all be built on-die in a system-on- a-chip (SOC) configuration.
  • SOC system-on- a-chip
  • a clock signal is described and it should be understood that a clock signal in the context of the instant description may be embodied as a strobe signal or other signal that conveys a timing reference and is not limited to a signal that is strictly periodic.
  • the clock signal may be a strobe signal that is aperiodic in the sense that transitions only occur when data is being transmitted.
  • the clock signal may be any type of signal that conveys timing information (e.g., temporal information that indicates that data is valid).
  • FIG. 4 presents a block diagram illustrating an embodiment of a memory system 400, which includes at least one memory controller 410 and one or more memory devices 412. While FIG. 4 illustrates memory system 400 with one memory controller 410 and three memory devices 412, other embodiments may have additional memory controllers and fewer or more memory devices 412. Moreover, while memory system 400 illustrates memory controller 410 coupled to multiple memory devices 412, in other embodiments two or more memory controllers may be coupled to one another. Note that memory controller 410 and one or more of the memory devices 412 may be implemented on the same or different integrated circuits, and that the one or more integrated circuits may be included in a chip- package.
  • the memory controller 410 is a local memory controller (such as a DRAM memory controller) and/or is a system memory controller (which may be implemented in a microprocessor).
  • Memory controller 410 may include an I/O interface 418-1 and control logic 420-1. As discussed in FIGs. 3A-3D, control logic 420-1 may be used to calibrate the first and second predetermined delay times for delay elements 344 and 346.
  • one or more of memory devices 412 include control logic 420 and at least one of interfaces 418. However, in some embodiments some of the memory devices 412 may not have control logic 420. Moreover, memory controller 410 and/or one or more of memory devices 412 may include more than one of the interfaces 418, and these interfaces may share one or more control logic 420 circuits. Note that in some embodiments two or more of the memory devices 412, such as memory devices 412-1 and 412-2, may be configured as a memory bank 416.
  • Memory controller 410 and memory devices 412 are coupled by one or more links 414, such as multiple wires, in a channel 422. While memory system 400 is illustrated as having three links 414, other embodiments may have fewer or more links 414. Moreover, these links may provide: wired, wireless and/or optical communication. Furthermore, links 414 may be used for bi-directional and/or uni-directional communication between the memory controller 410 and one or more of the memory devices 412. For example, bi-directional communication between the memory controller 410 and a given memory device may be simultaneous (full-duplex communication).
  • the memory controller 410 may transmit information (such as a data packet which includes a command) to the given memory device, and the given memory device may subsequently provide requested data to the memory controller 410, e.g., a communication direction on one or more of the links 414 may alternate (half-duplex communication).
  • information such as a data packet which includes a command
  • the given memory device may subsequently provide requested data to the memory controller 410, e.g., a communication direction on one or more of the links 414 may alternate (half-duplex communication).
  • one or more of the links 414 and corresponding transmit circuits and/or receive circuits may be dynamically configured, for example, by one of the control logic 420 circuits, for bi-directional and/or unidirectional communication.
  • Signals corresponding to data and/or commands may be communicated on one or more of the links 414 using either or both edges in one or more timing signals.
  • These timing signals may be generated based on one or more clock signals, which may be generated on-chip (for example, using a phase-locked loop and one or more reference signals provided by a frequency reference) and/or off-chip.
  • operations involved in transmitting and receiving these signals may be synchronous and/or asynchronous.
  • modulation coding may include bit-to-symbol coding in which one or more data bits are mapped together to a data symbol, and symbol-to-bit coding in which one or more symbols are mapped to data bits. For example, a group of two data bits can be mapped to one of four different amplitudes of an encoded data signal.
  • the encoding can include pulse amplitude modulation (PAM).
  • PAM pulse amplitude modulation
  • the modulation coding may include: two-level pulse amplitude modulation (2-PAM), three-level pulse amplitude modulation (3-PAM), and/or four-level pulse amplitude modulation (A-PAM).
  • the modulation coding may be dynamically adjusted, for example, based on a performance metric associated with communication on one or more of the links 414.
  • This performance metric may include: a signal strength (such as a signal amplitude or a signal intensity), a mean square error (MSE) relative to a target (such as a detection threshold, a point in a constellation diagram, and/or a sequence of points in a constellation diagram), a signal-to-noise ratio (SNR), a bit-error rate (BER), a timing margin, and/or a voltage margin.
  • commands are communicated from the memory controller 410 to one or more of the memory devices 412 using a separate command link, i.e., using a subset of the links 414 which communicate commands.
  • This separate command link may be wireless, optical and/or wired.
  • commands are communicated using the same portion of the channel 422 (i.e., the same links 414) as data.
  • communication of commands may have a lower data rate than the data rates associated with communication of data between the memory controller 410 and one or more of the memory devices 412; may use different carrier frequencies than are used to communicate data; and/or may use a different modulation technique than is used to communicate data.
  • the memory controller 410 and/or one or more of the memory devices 412 may use additional techniques to recover or prevent the loss of data communicated between components in the memory system 400 and/or the loss of stored data.
  • the data communicated between the components and/or the stored data may include error-detection-code (EDO) information and/or error- correction-code (ECC) information.
  • EDC error-detection-code
  • ECC error- correction-code
  • the ECC information includes a Bose-Chaudhuri- Hocquenghem (BCH) code.
  • BCH Bose-Chaudhuri- Hocquenghem
  • 5CH codes are a sub-class of cyclic codes.
  • the ECC information includes: a cyclic redundancy code (CRC), a parity code, a Hamming code, a Reed-Solomon code, and/or another error checking and correction code.
  • CRC cyclic redundancy code
  • receive circuits implement error detection and/or correction.
  • errors associated with communication may be detected by performing a multi-bit XOR operation in conjunction with one or more parity bits in the signals.
  • Devices and circuits described herein may be implemented using computer- aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. These software descriptions may be: behavioral, register transfer, logic component, transistor and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.
  • Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSIl, GDSlIl, GDSP/, CIF, and MEBES), and other suitable formats and languages.
  • RTL register transfer level
  • formats supporting geometry description languages such as GDSIl, GDSlIl, GDSP/, CIF, and MEBES
  • data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.
  • physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1/2 inch floppy media, CDs, DVDs, and so on.
  • this disclosure has described example techniques for communicating data from a first integrated circuit device to a second integrated circuit device.
  • the first integrated circuit device transmits a timing signal to the second integrated circuit device, wherein the timing signal includes a first transition and a second transition.
  • the first integrated circuit device then delays the data, so that the data is delayed relative to the timing signal by a first predetermined delay time.
  • the first integrated circuit device transmits the delayed data to the second integrated circuit device.
  • the second integrated circuit device receives the timing signal and the delayed data.
  • the second integrated circuit device delays the first transition of the timing signal by a second predetermined delay time to generate a delayed version of the first transition.
  • the second integrated circuit device senses the data during a time interval between the delayed version of the first transition and the second transition.
  • the first transition is a rising edge transition and the second transition is a falling edge transition; or the first transition is a falling edge transition and the second transition is a rising edge transition.
  • the first and second data are consecutive data.
  • the first integrated circuit device delays the data by delaying the timing signal, thereby generating a delayed timing signal and then using the delayed timing signal to delay the data.
  • the first integrated circuit device delays the timing signal by using a first delay element on the first integrated circuit device to delay the timing signal.
  • the second integrated circuit device delays the first transition of the timing signal by using a second delay element on the second integrated circuit device to delay the timing signal.
  • the first integrated circuit device transmits the timing signal by transmitting the timing signal via a first communication channel coupled between the first integrated circuit device and the second integrated circuit device. Additionally, the first integrated circuit device transmits the delayed data by transmitting the delayed data via a second communication channel coupled between the first integrated circuit device and the second integrated circuit device.
  • the first integrated circuit device comprises at least one transmitter and the second integrated circuit device comprises at least one receiver.
  • the second integrated circuit device senses the data during the time interval between the delayed version of the first transition and the second transition by first using the delayed version of the first transition to start integration of the data, and then using the second transition as a sense edge to trigger sensing of the data.
  • the delayed data at the second integrated circuit device includes the delayed first and second data, which are associated with a first noise band and a second noise band, respectively. Moreover, a window between the end of the first noise band and the beginning of the second noise band defines a time interval for sensing the data.
  • the first integrated circuit device delays the data by calibrating the first predetermined delay time so that the second transition substantially aligns with the beginning of the second noise band at the second integrated circuit device.
  • the first integrated circuit device calibrates the first predetermined delay time by causing the second integrated circuit device to perform sampling operations on the second noise band while moving the second transition toward the beginning of the second noise band.
  • the second integrated circuit device delays the first transition by calibrating the second predetermined delay time so that the delayed version of the first transition substantially aligns with the end of the first noise band at the second integrated circuit device.
  • the second integrated circuit device calibrates the second predetermined delay time by integrating the delayed data to maximize the integrated voltage while moving the first transition toward the end of the first noise band.
  • the first integrated circuit device delays the data prior to the second integrated circuit device delaying the first transition of the timing signal.
  • the second integrated circuit device directly uses the delayed version of the first transition as a sense edge to trigger sensing of the data.
  • the first integrated circuit device includes a first transmitter for transmitting a timing signal to the second integrated circuit device, wherein the timing signal includes a first transition and a second transition.
  • the first integrated circuit device also includes a first delay element for delaying the data, so that the data is delayed relative to the timing signal by a first predetermined delay time.
  • the first integrated circuit device additionally includes a second transmitter for transmitting the delayed data to the second integrated circuit device.
  • the second integrated circuit device which is coupled to the first integrated circuit device, includes a receiving mechanism for receiving the timing signal and the delayed data from the first integrated circuit device.
  • the second integrated circuit device also includes a second delay element for delaying the first transition of the timing signal by a second predetermined delay time to generate a delayed version of the first transition.
  • the second integrated circuit device additionally includes a sense circuit configured to sense the data during a time interval between the delayed version of the first transition and the second transition.
  • the first transition is a rising edge transition and the second transition is a falling edge transition; or the first transition is a falling edge transition and the second transition is a rising edge transition.
  • the first and second data are consecutive data.
  • the first transmitter and the receiver are coupled through a first communication channel, and the second transmitter and the receiver are coupled through a second communication channel.
  • the first transmitter and the second transmitter are coupled to the receiver through a common communication channel.
  • the sensing circuit further includes a sense amplifier and an integrator circuit coupled to the sense amplifier.
  • the output of the second delay element is coupled to the integrator circuit, while the received timing signal is coupled to the clock input of the sense amplifier.
  • the delayed data at the second integrated circuit device includes the delayed first and second data, which are associated with a first noise band and a second noise band, respectively. Moreover, a window between the end of the first noise band and the beginning of the second noise band defines a time interval for sensing the data. [0076] In some embodiments, the first delay element is configured to calibrate the first predetermined delay time so that the second transition substantially aligns with the beginning of the second noise band at the second integrated circuit device.
  • the integrator circuit while calibrating the first predetermined delay time, the integrator circuit is disabled so that the delayed data passes through the integrator circuit to the sense amplifier without integration, and the sense amplifier samples the second noise band while moving the second transition toward the beginning of the second noise band.
  • the second delay element is configured to calibrate the second predetermined delay time so that the delayed version of the first transition substantially aligns with the end of the first noise band at the second integrated circuit device.
  • the integrator circuit while calibrating the second predetermined delay time, integrates the delay data to maximize the integrated voltage while moving the first transition toward the end of the first noise band.
  • the second integrated circuit device includes a windowed integrating sampler, and wherein the delayed version of the first transition and the second transition defines a sense window.
  • the delayed version of the first transition initiates a precharge operation on the integrator circuit and second transition triggers a sensing action on the sense amplifier.
  • the system is a source-synchronous signaling system.
  • the received delayed data is coupled to the data input of the sense amplifier, and the output of the second delay element is coupled to the clock input of the sense amplifier.
  • the integrated circuit device receives a timing signal which includes a first transition followed by a second transition.
  • the integrated circuit device also receives the data, wherein the data is phase-offset with respect to the first transition by a predetermined phase offset.
  • the integrated circuit device then delays the first transition of the timing signal by a predetermined delay time to generate a delayed version of the first transition.
  • the integrated circuit device senses the data at the second integrated circuit device during a time interval between the delayed version of the first transition and the second transition of the timing signal.
  • the receiver includes (1) a first circuit for receiving a timing signal that includes a first transition followed by a second transition; (2) a second circuit for receiving data that is delayed by a first predetermined delay time with respect to the timing signal; (3) a third circuit for delaying the first transition of the timing signal by a second predetermined delay time to generate a delayed version of the first transition; and (4) a fourth circuit for sensing the data during a time interval between the delayed version of the first transition and the second transition of the timing signal.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention porte sur un système pour communiquer des données entre un premier dispositif à circuit intégré et un second dispositif à circuit intégré. Le premier dispositif à circuit intégré transmet un signal de temporisation au second dispositif à circuit intégré, le signal de temporisation comprenant une première transition et une seconde transition. Le premier dispositif à circuit intégré retarde ensuite les données, de telle sorte que les données sont retardées d'un premier temps de retard prédéterminé par rapport au signal de temporisation. Ensuite, le premier dispositif à circuit intégré transmet les données retardées au second dispositif à circuit intégré, qui reçoit le signal de temporisation et les données retardées. Ensuite, le second dispositif à circuit intégré retarde la première transition du signal de temporisation d'un second temps de retard prédéterminé pour générer une version retardée de la première transition. Le second dispositif à circuit intégré détecte ensuite les données pendant un intervalle de temps entre la version retardée de la première transition et la seconde transition.
PCT/US2009/042044 2008-05-02 2009-04-29 Signalisation synchrone avec une source haute vitesse WO2009134844A1 (fr)

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US4985108P 2008-05-02 2008-05-02
US61/049,851 2008-05-02

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