WO2009127884A1

WO2009127884A1 - Memory devices using proton-conducting polymeric materials

Info

Publication number: WO2009127884A1
Application number: PCT/GR2009/000023
Authority: WO
Inventors: Pascal Normand; Panagiotis Argitis; Nikolaos Glezos; Eleftherios Kapetanakis; Antonios Douvas; Eleni Makarona; Dimitrios Velessiotis
Original assignee: National Center For Scientific Research ''demokritos''
Priority date: 2008-04-18
Filing date: 2009-04-14
Publication date: 2009-10-22
Also published as: EP2277202A1; GR20080100269A; GR1007121B

Abstract

This invention relates to non-volatile and volatile electronic memory devices in which the information carriers are in the form of protons. More particularly, a method of forming a proton memory component of a memory transistor is disclosed. More specifically, said proton memory component comprises a proton-conducting polymeric layer and additionally, may comprise one or two layers made of a material containing proton-trapping sites for the purpose of ensuring a non-volatile function to a memory device.

Description

MEMORY DEVICES USING PROTON-CONDUCTING POLYMERIC MATERIALS

TECHNICAL FIELD

STATE OF THE ART

A computer memory element is a device that can store information in the form of digital bits (¹O' or '1 ') in a structure that can be rapidly switched between two readily discernible states. Among the technologies that have been developed over the years in realizing data storage, the Metal-Oxide-Semiconductor (MOS) data storage elements exhibit superior characteristics in terms of cost and performance and for this reason they are used as best memory alternatives in today electronic systems. MOS memories are based on the presence or absence of electrical charge contained in a tiny confined region of a storage element; physical states that can be read electrically by addressing the storage element.

MOS memories can be classified as Random-Access-Memories (RAMs) and reprogrammable Read-Only-Memories (ROMs) depending both on their ability to retain data without external power (quality also known as non-volatility) and on their read and programming speeds. RAMs permit data to be stored and retrieved at comparable fast speeds but they are volatile. The two most common RAM types include dynamic RAM (DRAM) and static RAM (SRAM). DRAMs are used as a main memory for personal computers because of their low cost and high-density capability (i.e., 1 transistor-1 capacitor storage element), while SRAMs are mostly used as on-chip cache memory on microprocessors due to their faster access speed and larger storage cell size (6 transistors) compared to DRAMs.

On the other hand, a re-programmable ROM (also called non-volatile memory, NVM) is a device that can write data electrically and does not require any power for the maintenance of the data, but for which data re-writing (ie. data re-programming) is far more time-consuming than the reading. Hence, a NVM is used only when re-writing is rarely required. At present, the dominant technology for NVM implementation is based on the floating gate (FG) concept, where MOS Field-Effect-Transistors (MOSFETs) with an additional floating gate are used as storage elements. All FG NVM memory cells have the same generic cell structure and are roughly classified following their erasing mode, to ultra- violet light UV-erasable EPROM (Electrically Programmable Read Only Memory) and EEPROM (Electrically Erasable PROM) including the most recent and important version of Flash EEPROM where the complete memory array is erased "in a flash". Since its first appearance at 1984, Flash has quickly become the largest market in non-volatile technology, due to high competitive tradeoff between functionality and cost per bit. For example, years ago Flash BIOS chips replaced once-programmable ROM (i.e., mask-based ROM, PROM) BIOS chips in PCs so that the BIOS could be updated in place instead of having to be removed and replaced. Today, extremely durable Flash is widely used for storage modules such as USB drives and digital camera memory cards. For example, in a digital camera, a NOR-type Flash chip holds the software, while NAND-type Flash is the chip in the memory card for storing images.

Regardless of inherent functional and performance limitations (i.e., the relatively slow program speed and the limited number of re-programming operations), that preclude the usage of Flash as a RAM, the non-volatile property and low cost of Flash chips make them the optimum choice for mass storage in personal mobile systems. With the advent of mobile era Flash memory has become a growing engine within semiconductor memory business.

While there are undoubtedly many years of life left in the current DRAM and Flash technologies, the 1 transistor-1 capacitor structure of the DRAM cell as well as the FG structure of the Flash cell will face fundamental economic, technological, and physical scaling problems as the industry moves to ever smaller chip circuitry.

For DRAM technology, the urgent demand of increasing retention time for low power consumption causes DRAM development to face great challenges due to the inherent constrains of low leakage access transistors and the need of large storage capacitance. On the other hand, major scaling issues pertinent to Flash memory circuitry are ultimately related to the difficulties in scaling down the vertical dimensions of the FG transistor and therefore, in scaling of the operating voltages. It should be noticed that the high voltages needed for programming and erasing operations cause the Flash chip circuitry scaling to be even more difficult because of the cell-to-cell interference and the requirement of on-chip generation of these high voltages. In addition, high voltage operation severely limits the Flash applications in the embedded memory market, as it is very difficult to merge Flash with logic technologies.

With the increasing challenge of scaling memory devices beyond the 50 nm technology node, aggressive investigation of an alternate scalable memory structure offers the best hope for continuing the current performance scaling trends seen in the last 3 decades. In this direction, various innovative memory technologies are being investigated for non-volatile, ultra-high-density, low voltage, low power, and fast write/erase data storage. Memory alternatives can arise either from adding exotic materials to otherwise conventional cell structures and CMOS process flows, or by coming up with novel cell structures and physical storage principles.

Emerging non-volatile RAM technologies explore a range of next-generation memory devices. Some memory devices, such as the ferroelectric RAM (FRAM), the phase-change RAM (PCRAM), and the magnetic RAM (MRAM), exploit physical principles for data storage that have been around for years. Others devices, such as insulator resistance change memories, polymer memories, molecular memories, DNA memories, and carbon nanotube memories are constructed on new physical principles. All non-volatile RAM technologies exhibit attractive characteristics appealing universal memory applications and some of them appear to be nearer term than others. However, because these technologies are based on novel electronic materials, more research and development are required in order to favor one over the other and decide which of them (if any) will enter the memory mainstream.

Another promising alternative for low-cost ultra-dense low-voltage non-volatile data storage lies in the use of modified Flash memory structures. These transistor memory structures have the advantage of being compatible with conventional memory architectures and thereby, offer an attractive short-term option to memory scaling issues. Solutions attempted have fallen in two categories depending on the nature of the primary carriers of information. In one category these carriers are electrons and/or holes while in the other, they are in the form of ions containing a single proton (i.e. positive ions of any hydrogen isotope, hereinafter referred as hydrogen ions or protons).

In the first category, the storage of electric charges (electrons and/or holes) takes place in electrically isolated charge-trapping sites (also referred as storage nodes) in place of the conventional FG layer. In that case, excellent immunity to oxide defects is thus ensured since even if a pinhole exists in the tunneling oxide, leakage will only cause a few storage nodes to lose their charge. This allows the implementation of memory transistors with thinner tunneling oxides, operating at lower voltages and/or faster programming speeds. Storage nodes in charge trapping Flash memory technologies are typically either in the form of natural traps distributed in a nitride layer or isolated nanocrystals embedded in the gate dielectric. Nitride trap Flash memories such as the Silicon-Oxide-Nitride-Oxide- Silicon (SONOS) memory and its most recent version of Nitride Read-Only Memory (NROM) are potentially a near term solution, as silicon nitride is relatively a well-known material. Nanocrystal Flash memory will possibly follow the implementation of nitride trap Flash but still face the fabrication issue of producing high-density of uniformly distributed size-homogeneous nanocrystals and hence, cannot avoid fluctuations in device performance. In general, there is one big quandary in scaling high-density non-volatile charge-trapping-based memory devices. This is the finite capability in scaling the thickness of the dielectric layer in order to ensure the device non-volatility, i.e., to secure sufficient data retention periods. As a result, device operating voltage, and therefore, power consumption cannot be significantly reduced.

As mentioned above the second category relates to modified Flash memory structures that exploit protons instead of electrons and/or holes as the primary carriers of information. Such memory structures, commonly referred as proton memory devices, utilize the motion of protons within the gate dielectric of a MOS transistor. To date, demonstration of proton memory devices is limited to MOSFETs using SiO₂ material as the gate dielectric; said gate dielectric being sandwiched between two electrodes made of silicon material (referred hereinafter as Si-SiO₂-Si structure). Proton memory devices in the art require the gate dielectric to be loaded with protons. Introduction of protons inside a gate dielectric made of SiO₂ material is achieved either thermally by annealing the Si-SiO₂-Si structure in a hydrogen-containing atmosphere or by direct injection of hydrogen ions inside said gate dielectric using ion-implantation techniques. Programming of proton memory devices is done by applying a voltage (referred as programming voltage) across the Si-SiO₂-Si structure. This can move the mobile protons at either the lower or the upper edge of the SiO₂ layer so that the conduction state of the transistor channel can be switched 'on' or 'off¹. Since the protons do not move when no external field is applied to the Si-SiO₂-Si structure, the memory is non-volatile. A detailed description of proton memory devices can be found, for example, in U.S. Pat. Nos. 5,830,575, 6,140,157 and 6,159,829, and U.S. Pat. Appl. Pub. No. US 2006/0121661 A1.

In addition to the advantages of using a modified Flash memory architecture and of being radiation tolerant, proton memory devices also present over charge-trapping memory devices the advantage of being able to be programmed at much lower voltages, thus offering a better alternative for low-power consumption.

However, the conventional methods of forming proton memory devices still face critical issues regarding the development of commercial products. For example, all these conventional methods utilize proton generating techniques (high-temperature processing and ion implantation) that first, can seriously affect the logic structures on the chip and second, cannot control the number of generated protons thereby introducing large variations in device-to-device performance. Moreover, conventional proton memory devices exhibit long-programming times and are highly sensitive to the gate material as it has been demonstrated that a metal gate structure allows the protons to escape, which is an issue that limits the choice of gate materials to materials impervious to motion of protons. Finally, the methods of proton memory devices in the art cannot be applied to emerging memory technologies seeking the development of all-organic electronic devices.

Memory manufacturers are continuously seeking alternative memory technologies not only to overcome the fast-approaching scaling problems of conventional MOS memory devices and thereby, to enhance existing products, but also to expand existing memory markets, to create new products and to penetrate emerging memory markets. A low-cost and simple method able to produce memory components for the fabrication of high-density low-power memory devices whereby the scaling problems of conventional memory technologies could be eliminated is therefore desirable. In addition, memory components that could offer opportunities for the production of novel non-CMOS memory devices are also highly desired.

SUMMARY OF THE INVENTION The present invention discloses proton memory components comprised in memory devices and a method of producing such; said memory devices are herein referred to also as "memory transistors". Said proton memory components comprise at least a first layer made of proton-conducting polymeric material. Application of an electric field across said first layer produces anions and protons; said protons can be conducted at either side of said first layer depending on the direction of the electric field. The electrically induced temporary displacement of protons at either side of said first layer determines the memory state of memory devices constructed with a proton memory component made of said first layer; Such memory devices are useful for long-refresh volatile memory applications.

In addition to the said first layer, a proton memory component disclosed by the present invention may comprise one or two additional layers, which are referred to herein as "second-layers", whereas such second layers are made of a material containing proton- trapping sites. Said second layers may be formed either on the top or on the bottom or on both surfaces of the said first layer. Application of an electric field across a memory component comprising the said first layer and one or two said second layers allows separation of anions and protons, motion of protons across the proton memory component, trapping (ie storage) of all or part of the mobile protons, and de-trapping of all or part of the trapped protons. Trapping of protons in a proton memory component provides a non-volatile function to a memory device. The present invention further provides manufacturing routes of incorporating the aforementioned proton memory components onto a modified CMOS and a non-CMOS platform for forming Si/organic hybrid and all-organic field-effect-transistor proton memory devices, respectively.

The present invention relates to proton memory devices and to the production and use of new proton memory components. It is an object of the present invention to overcome the aforementioned problems and limitations associated with prior art proton memory devices. Compared to prior art techniques, the present invention provides proton memory components (referred hereinafter as PMCs) that do not require high-temperature annealing processes or ion implantation techniques for proton generation and presents advantages such as: (1 ) increased device-to-device uniformity in the number of protons and therefore, reduced variations in memory characteristics from device to device, (2) reduced sensitivity to metal gate materials, (3) enhanced capability to control critical device parameters like the density, the position, and the energy level of the proton trapping sites, a feature necessary for the modulation and optimization of device's overall memory performance, and (4) enhanced flexibility for targeting memory applications ranging from low-voltage and low- power Flash functions to medium-speed and long refresh cycle DRAM-like functions.

It is a further object of the present invention to provide low-cost polymer-based PMCs for producing proton memory devices (ie. proton memory transistors) with potential in high-density volatile and non-volatile memory applications.

It is yet a further object of the invention to provide polymer-based PMCs that can be merged into a modified CMOS platform technology.

Still, it is an object of the present invention to provide a polymer-based PMC that can be incorporated into a non-CMOS platform technology (e.g., in an organic field-effect- transistor process flow).

Other objects of the invention will become apparent as the description of the invention proceeds.

According to some specific embodiments of the present invention, a non-volatile

PMC (ie. a PMC ensuring a non-volatile function to a memory device) is provided having a tri-layer structure comprising a proton-conducting polymeric layer sandwiched between two layers made of a material which contains proton trapping sites (said two layers being hereinafter referred as proton-trapping layers).

In preferred embodiments of the invention, the said proton-conducting polymeric layer of the PMC is made of inorganic/organic hybrid proton-conducting polymeric material. In one example arrangement this layer comprises a strong Brόnsted acid in which protons are mobile carriers. In one arrangement of the embodiment the strong acid is selected from the classes of heteropolyacids of tungsten, sulfonic acids or fluorinated super acids or their derivatives. The proton-conducting polymeric layer may be formed from strong acid containing solutions using spin coating or dip coating techniques, or from techniques of evaporation or chemical vapour deposition of strong-acid containing materials. In one example arrangement the thickness of the proton-conducting polymeric layer may be in the range of about 5 to 300 nm, more preferably less than about 200 nm.

In preferred aspects of the embodiments of the present invention, the said proton- trapping layers of the PMC are made of material which contains basic sites. In one arrangement of the embodiments the basic sites may come from strong bases selected from primary, secondary or tertiary amine. In another example arrangement the basic sites may come from weak or medium bases selected from ether, ester, hydroxyls, or amides. In another example arrangement the basic sites are nitrogen-containing group attached to atoms other than carbon and hydrogen. The proton-trapping layer may be formed from base containing solutions using spin coating or dip coating techniques, or from techniques of evaporation or chemical vapour deposition of basic-site containing molecules. In one example arrangement the thickness of the proton-trapping layer may be in the range of about 5 to 300 nm, more preferably less than about 150 nm.

Preferably, the memory transistor disclosed in the present invention comprises a proton memory component, wherein said memory component comprises a first layer comprising a proton-conducting polymeric material. Advantageously, the said first layer comprised in a proton memory component comprised in a memory transistor disclosed in the present invention comprises strong acid.

Advantageously, the said strong acid is selected from the classes of hetero- polyacids of tungsten, sulfonic acids or fluorinated super acids or their derivatives.

Preferably, the said first layer comprised in a proton memory component comprised in a memory transistor disclosed in the present invention has a thickness in the range of 5 to 300nm.

Conveniently, the said first layer comprised in a proton memory component comprised in a memory transistor disclosed in the present invention has a thickness of less than 200nm. Advantageously, the proton memory component comprised in a memory transistor disclosed in the present invention further comprises electrodes arranged for applying an electric field across the first layer for the purpose of moving protons across the first layer.

Advantageously, the proton memory component disclosed in the present invention further comprises a second layer made of a material that contains proton trapping sites, located on a surface of the first layer.

Advantageously, the said proton memory component which further comprises a second layer further comprises a third layer made of a material that contains proton trapping sites, located on the opposite surface of the first layer in order to obtain a proton memory component comprising a stack of three layers where the first layer is located between the second and third layers.

Preferably, in the said proton memory component disclosed in the present invention which further comprises a second layer or also a third layer, the second layer comprises basic sites.

Advantageously, in the said proton memory component disclosed in the present invention which further comprises a third layer, the third layer comprises basic sites.

Conveniently, the said basic sites disclosed in the present invention come from strong bases selected from primary, secondary or tertiary amine. Advantageously, the said basic sites disclosed in the present invention come from weak or medium bases selected from ether, ester, hydroxyls, or amides.

Conveniently, the said basic sites disclosed in the present invention are nitrogen containing groups, where the nitrogen atoms are attached to atoms other than carbon and hydrogen. Preferably, in the proton memory component which further comprises a second layer or also a third layer, wherein said additional layers are made of a material that contains proton trapping sites as disclosed in the present invention, at least one said layer has a thickness in the range of 1 to 300nm.

Advantageously, said thickness is less than 150nm. Preferably, a memory transistor disclosed in the present invention comprises: a semiconductor substrate; drain and source regions in the semiconductor substrate; a proton memory component as described above provided on the substrate; and, a conductive gate layer provided on the surface of the proton memory component opposite to the substrate.

Advantageously, the said memory transistor further comprises a silicon oxide layer between the substrate and the proton memory component.

Conveniently, in the said memory transistor the conductive gate layer is a metallic layer or a stack of metallic layers. Advantageously, a memory transistor disclosed in the present invention comprises: a rigid or flexible substrate with a conductive gate layer thereon; a proton memory component as disclosed in the present invention provided on the conductive gate layer; a layer made of semiconducting organic material provided on the proton memory component; and, drain and source electrodes provided on the layer made of semiconducting organic material. Conveniently, in the said memory transistor the gate layer is made of a metallic material or a polymeric material or a combination of metallic and polymeric materials.

Preferably, in the said memory transistor the semiconducting organic material is made of polymeric or oligomeric organic material. Advantageously, in the said memory transistor the semiconducting organic material is selected from poly(3-substituted thiophene)s, pentacene, rubrene or phthalocyanines.

Advantageously, a memory transistor disclosed in the present invention comprises: a semiconductor substrate; drain and source regions in the semiconductor substrate; a proton memory component comprising a first layer, said first layer comprising a proton conducting material as disclosed in the present invention provided on the substrate; and, a conductive gate layer provided on the surface of the proton memory component opposite to the substrate. Conveniently, the said memory transistor further comprises a silicon oxide layer between the substrate and the proton memory component.

Advantageously, the said memory transistor further comprises a dielectric layer impervious to migration of protons provided between the proton memory component and the conductive gate layer. Preferably, in the said memory transistor the dielectric layer is made of a polymeric material.

Advantageously, the method of producing a memory transistor comprising a proton memory component disclosed in the present invention comprises forming a stack of layers consisting of a first layer of proton-conducting polymeric material. Conveniently, the method of producing a memory transistor comprising a proton memory component disclosed in the present invention further comprises providing a second layer, made of a material that contains proton trapping sites, on a surface of the first layer.

Preferably, according to the said method disclosed in the present invention, the first layer of the proton memory component is produced by spin-coating of a solution containing a proton-conducting polymeric material and subsequent baking at a temperature between 50 to 170 degrees C.

Preferably, the method of operating a memory transistor comprising a proton memory component disclosed in the present invention comprises applying an electric field across the layers for the purpose of moving protons across the first layer, and trapping in and/or de-trapping protons from a layer made of a material that contains proton trapping sites. BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1a-1e illustrate in a cross sectional view an embodiment of a non-volatile proton memory component between two electrodes in various operational states.

FIG. 2 is a graph of experimental C-V characteristics of an embodiment of a MIS- type non-volatile memory capacitor, with a cross section structure shown in the inset.

FIGS. 3a-3d illustrates in a cross sectional view an embodiment of a volatile proton memory component between two electrodes in various operational states.

FIG. 4 is a graph of experimental C-V characteristics of an embodiment of a MIS- type volatile memory capacitor, with a cross section structure shown in the inset. FIGS. 5a-5g illustrate in cross sectional views, a series of process steps according to an embodiment of the invention for producing a MISFET-type non-volatile memory device structure with a tri-layer proton memory component.

FIG 6 illustrates in a cross sectional view a MISFET-type non-volatile memory device structure with a bi-layer proton memory component in accordance with an embodiment of the present invention.

FIG 7 illustrates in a cross sectional view a MISFET-type non-volatile memory device structure with a bi-layer proton memory component in accordance with another embodiment of the present invention.

FIGS. 8a-8d illustrate in cross sectional views and in simplified I_DS-V_GS characteristics, two programming states of the non-volatile memory device shown in FIG

5g-

FIGS. 9a-9d illustrate in cross sectional views and in simplified I_DS-VG_S characteristics, two programming states of the non-volatile memory device shown in FIG 6.

FIGS. 10a-IOd illustrate in cross sectional views and in simplified I_DS-V_GS characteristics two programming states of the non-volatile memory device shown in FIG 7.

FIGS. 11a-11 b illustrate in a cross sectional view two further programming states of the non-volatile memory device shown in FIG 5g, according to another embodiment of the present invention.

FIGS. 12a-12b illustrate in a cross sectional view two operational states of a MISFET-type volatile memory device constructed in accordance with an embodiment of the present invention.

FIGS. 13a-13c illustrate in cross sectional views, a series of process steps according to an embodiment of the invention for producing an organic field-effect-transistor non-volatile memory device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION The non-volatile memory effect of the PMC having the tri-layer structure according to one embodiment of the invention is based on the storage (ie. trapping) of inner layer's protons in the outer layers (ie. in the said proton-trapping layers) and/or at their interfaces with the inner layer (ie. with the said proton-conducting polymeric layer). Storage of mobile protons can be electrically induced and might be mostly understood through the study of FIGS. 1a-1e that describe a capacitor-like structure made of a tri-layer PMC comprising a proton-conducting layer 211 sandwiched between two proton-trapping layers 213 and 214, a first electrode 210 and a second electrode 212 formed respectively onto the lower and upper surfaces of said tri-layer PMC, and two externally accessible terminal electrical contacts 231 and 232, referred respectively as bottom and top contacts, attached to the electrodes 210 and 212.

FIG 1a illustrates an unbiased virgin capacitor element. No spatial distribution of ionic charges occurs within the said tri-layer PMC as each proton contained in layer 211 stays close to its counter anion forming a neutral acid molecule 234. Application of a voltage across the tri-layer PMC may produce an electric field (E) allowing (1) dissociation of all or part of the molecule population 234 into anions and protons, (2) motion of protons in the electric field direction and (3) storage (ie. trapping) of all or part of the moved protons in layer 213 or layer 214 depending on electric field strength and direction. Such a voltage (referred herein as programming voltage) may lead to spatial distributions of ionic charges as described in FIGS. 1 b and 1c. A negative programming voltage supplied to the top contact 232 with bottom contact 231 connected to ground, as shown in FIG. 1 b, causes the mobile protons 235 to be trapped (ie. stored) in proton-trapping sites of layer 214, leaving the anions 236 in layer 211. In the case of a positive programming voltage supplied to the top contact 232 with bottom contact 231 connected to ground, as shown in FIG. 1c, the mobile protons 237 are trapped (ie. stored) in proton-trapping sites of layer 213 and the anions 238 are formed. Since the trapped protons do not move in the time that follows the application of the negative or positive programming voltage (ie. when the programming voltage is cut-off), as described in FIGS. 1d and 1e, their storage is non-volatile.

It is understood in the foregoing or following embodiments of the present invention that the proton-trapping sites of a layer made of a material containing proton-trapping sites (ie. a proton-trapping layer) refer to proton-trapping sites located either in the bulk of the said layer or at the interface between said layer and a layer made of a proton-conducting polymeric material, or both.

Embodiments of the present invention may be used for producing a novel nonvolatile memory device having a Metal-lnsulator-Semiconductor-type (MIS-type) capacitor structure. An example arrangement of a non-volatile memory MIS-type capacitor structure using the method of the present invention, as described in the inset of FIG. 2, comprises a gate oxide formed onto a silicon substrate, a tri-layer PMC made of a proton-conducting polymeric layer (referred in the inset of FIG. 2 as proton-conducting layer) sandwiched between two proton-trapping layers, said tri-layer PMC being formed onto the top surface of said gate oxide, and a metal gate electrode. The character I in acronym MIS refers to the composite dielectric stack comprising both the gate oxide and the tri-layer PMC.

Experimental data curves reported in FIG. 2 relate to a non-volatile memory MIS- type capacitor with a gate oxide layer of about 3.5 nm in thickness made of SiO₂ material thermally grown onto a n-type silicon substrate, a metal gate electrode made of Al material and a tri-layer PMC produced in accordance with the method of the present invention. The process conditions used for producing the tri-layer PMC include: (a) formation onto said gate oxide of a first proton-trapping layer having a physical thickness of about 300 nm by spin coating of polymethyl methacrylate (commonly referred as PMMA) solutions containing amines; (b) thermal treatment in a conventional atmospheric furnace at 12O⁰C for 60 min;

(C) formation onto said first proton-trapping layer of a proton-conducting polymeric layer having a physical thickness of about 300 nm by spin coating of PMMA solutions containing

H₃PWi₂O₄₀ acid molecules (commonly referred as POM material); (d) thermal treatment in an atmospheric furnace at 12O⁰C for 60 min; (e) formation onto said proton-conducting polymeric layer of a second proton-trapping layer having a physical thickness of about

300nm by spin coating of PMMA solutions containing amines; (f) thermal treatment in a conventional atmospheric furnace at 120⁰C for 60 min.

The non-volatile memory behaviour of the MIS-type capacitor produced in accordance with the method of the invention might be mostly understood through the study of the experimental high-frequency capacitance-voltage (C-V) characteristics of the device shown in FIG. 2. All C-V curves are measured by applying a forward voltage sweep to the metal gate electrode (i.e., by sweeping the gate voltage from left to right) with the silicon substrate connected to ground. The dotted C-V curve 1 in FIG. 2 depicts the capacitive behaviour of the MIS-type capacitor before application of any programming voltage and may be interpreted as the non-programming state of the device.

In a manner similar to that described in FIGS. 1a-1e, a negative programming voltage applied to the gate electrode of the MIS-type capacitor allows storage of protons in proton-trapping sites of the said second proton-trapping layer while a positive programming voltage allows storage of protons in proton-trapping sites of the said first proton-trapping layer. The transfer of protons to trapping sites of one or the other proton trapping layers produces two distinct spatial distributions of ionic charges across the tri-layer PMC so that the MIS-type capacitor switches between two well distinguishable capacitive states (referred herein as programming states) The C-V curves 2 and 4 shown in FIG 2 represent the two programming states of the device such as measured after application of a negative and positive programming voltage, respectively The dashed C-V curves 3 and 5 represent the above programming states measured after a time period of about 25 hours following application of the negative and positive programming voltage, respectively The very small C-V changes detected between either the C-V curves 2 and 3 or the C-V curves 4 and 5 shown in FIG 2 clearly indicate that proton storage in the tri-layer PMC is non-volatile

According to another aspect of an embodiment of the present invention, a nonvolatile PMC may be produced with a bi-layer structure comprising a proton-conducting polymeric layer and a proton-trapping layer Said proton-trapping layer may be located either under the bottom surface or onto the top surface of said proton-conducting polymeric layer Similar to the case of the tπ-layer PMC, the non-volatile memory function of the memory component having the said bi-layer structure is based on the storage (ιe trapping) of protons, released from the proton-conducting polymeric material, in proton-trapping sites of said proton-trapping layer

According to a further aspect of an embodiment of the present invention, a volatile

PMC made of a proton-conducting polymeric layer may be produced The volatile memory function of the PMC is based on the temporary transfer of protons to one or to the other edge of the proton-conducting polymeric layer This might be mostly understood through the study of FIGS 3a-3d that describe a capacitor-like structure comprising a PMC made of a proton-conducting polymeric layer 111 sandwiched between a bottom electrode 110 and a top electrode 1 12, and two externally accessible electrical contacts 132 and 131 , referred respectively as top and bottom contacts, attached to the electrodes 112 and 110

FIG 3a describes the unbiased capacitor-like structure in equilibrium state No spatial distribution of ionic charges occurs in layer 11 1 , as each proton stays close to its counter anion forming a neutral acid molecule 134 Application of a voltage across layer

111 may produce an electric field (E) allowing (1 ) dissociation of all or part of the molecule population 134 into anions and protons and (2) motion of protons in the electric field direction (ιe towards the negatively charged electrode) Such a voltage (referred herein as programming voltage) may lead to spatial distributions of ionic charges as described in

FIGS 3b and 3c A negative programming voltage supplied to the top contact 132 with bottom contact 131 connected to ground, as shown in FIG 3b, causes the mobile protons

135 to accumulate in a region close to the upper edge of layer 111 , the counter anions 136 staying in a region close to the lower edge of layer 111. In the case of a positive programming voltage supplied to the top contact 132 with bottom contact 131 connected to ground, as shown in FIG. 3c, the mobile protons 137 tend to accumulate in a region close to the lower edge of layer 1 11 ; the counter anions 138 staying in a region close to the upper edge of layer 111. In the time that follows the application of the programming positive or negative voltage (ie. when the programming voltage is cut-off), the mobile protons move toward anions in order to recover the unbiased equilibrium state of the device, as described in FIG. 3d. Such a return to equilibrium confers a volatile memory function to the device.

Embodiments of the present invention may be used for producing a novel volatile memory device having a MIS-type capacitor structure. An example arrangement of a volatile memory MIS-type capacitor structure using the method of the present invention, as described in the inset of FIG. 4, comprises a gate oxide formed onto a silicon substrate, a PMC made of a proton-conducting polymeric layer (referred in the inset of FIG. 4 as proton- conducting layer) sandwiched between said gate oxide and a metal gate electrode. The character I in acronym MIS refers to the composite dielectric stack comprising the gate oxide and the proton-conducting polymeric layer.

Experimental data curves reported in FIG. 4 relate to a volatile memory MIS-type capacitor structure with a gate oxide layer of about 3.5 nm in thickness made of SiO₂ material thermally grown onto a n-type silicon substrate, a metal gate electrode made of Al material and a PMC produced in accordance with the method of the present invention that includes: (a) formation onto said gate oxide of a proton-conducting polymeric layer having a physical thickness of about 300nm, by spin coating of PMMA solutions containing H₃PW₁₂O₄₀ acid molecules; (b) thermal treatment in an atmospheric furnace at 120⁰C for 60 min.

The volatile memory behaviour of the MIS-type capacitor produced in accordance with the method of the invention might be mostly understood through the study of the experimental high-frequency capacitance-voltage (C-V) characteristics of the device shown in FIG. 4. All C-V curves are measured by applying a forward voltage sweep to the metal gate electrode (ie. by sweeping the gate voltage from left to right) with the silicon substrate connected to ground. The dotted C-V curve 1 of FIG. 4 depicts the capacitive behaviour of the MIS-type capacitor before application of any programming voltage and may be interpreted as the non-programming state or equilibrium state of the device. In a manner similar to that described in FIGS. 3a-3d, a negative or positive programming voltage applied to the gate electrode of the MIS-type capacitor causes the mobile protons in the PMC made of the proton-conducting polymeric layer to accumulate in a region close to the upper or lower edge of said PMC, respectively. The transfer and further accumulation of protons to one or to the other region close to the upper or lower edge of the PMC, produces two distinct spatial distributions of ionic charges across the PMC so that the MIS-type capacitor switches between two well distinguishable capacitive states (referred herein as programming states). The C-V curves 2 and 4 shown in FIG. 4 represent the two programming states of the device such as measured after application of a negative and positive programming voltage, respectively. In the time that follows the application of the positive or negative programming voltage, the accumulated protons move back toward counter anions causing the programming states of the device to gradually drift to the equilibrium state. The dashed C-V curves 3 and 5 in FIG. 4 measured after a time period of about 100 s following the application of the negative and positive programming voltage, respectively, reveal a slow drift of the programming states. Such a drift indicates that a PMC made of a proton-conducting polymeric material cannot offer a true non-volatile memory function to a memory device but is appropriated for long-refresh volatile memory applications.

Embodiments of the present invention may be used for producing a MIS-type field- effect-transistor (FET) memory device.

Compared to the prior art of MOSFET proton memory device using a Si/SiO₂/Si structure as memory component, MISFET-type proton memory devices that may be produced using a PMC in accordance with the method of the present invention offer advantages such as:

(1) Use of low-cost and low-thermal budget PMC materials for creating a proton-based memory function. Production of a PMC in accordance with the method of the invention enables whole-wafer processing; a critical feature for practical device implementation.

(2) Use of protons as primary carriers of information that naturally exist in the proton- conducting polymeric material of the PMC and therefore, no fabrication process step for introducing protons inside the PMC is required; any additional processing step for generating protons having the disadvantage to increase complexity and cost in device fabrication and may introduce device-to-device variation in the number of introduced protons. (3) Use of proton-conducting polymeric material; an advantage that allows rapid proton motion within the PMC and thereby, fast programming speeds even for low programming voltages.

(4) Use of a layer or layers made of a material containing proton-trapping sites that can be formed at a controllable distance away from the device gate electrode and/or the device conduction channel. Such a control in proton-trapping layer positioning offers a device fabrication option to prevent possible escape of trapped protons to a metal gate electrode as well as possible degradation of a dielectric/semiconductor interface like but not limited to a SiO₂/Si interface. This provides both immunity to metal gate materials and maintenance of the transistor inherent properties (such as the transconductance of a MISFET-like proton memory device). The control of the proton trapping site's location from a metal gate electrode may be achieved by interposing an insulating layer between the metal gate electrode and a proton-trapping layer, while the distance between the proton-trapping sites and the transistor channel may be controlled through adjustments of the gate dielectric thickness (ie. the thickness of the dielectric layer sandwiched between a semiconductor surface and a proton- trapping layer).

(5) Use of controllable proton-trapping sites in terms of energy level and density; an important advantage for controlling the memory characteristics (such as programming speed, programming voltage and data retention time) of non-volatile MlSFET-type proton memory devices. The energy level of proton-trapping sites depends on the basicity (weak, medium, strong) of the material selected for forming a proton-trapping layer. The density of proton-trapping sites can be varied by changing the nature and amount of the material selected for forming a proton-trapping layer. The large choice in basic materials that can be used in accordance with the method of the invention allows: (a) selection of proton-trapping sites ranging from shallow to deep traps and thereby, control of the energy level of proton-trapping sites and, (b) control of the density of proton-trapping sites, a feature that affects the number of protons than can be stored in a PMC. Of course, particular choice in density and energy level of proton-trapping sites depends on the intended device memory characteristics.

Still, embodiments of the present invention may further be used for producing an organic-based field-effect-transistor (FET) proton memory device. This can be achieved by incorporating a PMC, in accordance with the method of the invention, into a non-CMOS FET technology. According to embodiments of the invention, the manufacturing steps of a PMC may be added to the fabrication process of an organic FET for the purpose of manufacturing a novel all-organic single-transistor proton-memory-device integrable on flexible (e.g., plastic) or rigid (e.g., glass) substrates.

FURTHER PREFERRED EMBODIMENTS OF THE INVENTION

Reference is made to FIGS. 5a-5g which illustrate a series of process steps according to an embodiment of the invention for fabricating an electronic memory device. The described processing steps in FIGS. 5a-5g and the related structures do not form a complete process for manufacturing a memory device, but they are necessary for an understanding of the application of embodiments of the present invention. FIGS. 5a-5g represent cross-sections of portions of a memory device structure and are not drawn to scale but instead are drawn so as to illustrate the important features of the invention.

FIG. 5a illustrates a portion of a memory device structure that includes a semiconductor substrate 310 with two doped regions 311. In one arrangement, the semiconductor substrate may be a silicon substrate. In another arrangement, the semiconductor substrate may be a mono-crystalline or a poly-crystalline silicon layer mounted on dielectric materials.

The two-doped regions 311 may be selectively formed into the semiconductor substrate by the conventional manner of photolithography, ion implantation and subsequent thermal treatment. In one arrangement the implanted ions are elements from group III of the periodic table, preferably boron, when the semiconductor substrate 310 is made of n-type silicon materials. In another arrangement the implanted ions are elements from group V of the periodic table, preferably phosphorus or arsenic, when the semiconductor substrate 310 is made of p-type silicon materials. The two-doped regions form the source and drain regions of a memory device.

In the next stage of the process according to one embodiment of the present invention, as shown in FIG. 5b, a dielectric layer 312 may be formed on the surface of 310 and 311. In one example arrangement, the dielectric layer 312 may be a silicon oxide layer of about 2 to 10 nm in thickness. The dielectric layer 312 may be formed by conventional techniques, such as thermal oxidation of silicon materials or low-pressure chemical vapour deposition of silicon oxide.

In the next processing stage, as shown in FIG. 5c, metallic pads 313 may be formed onto the two-doped regions 311. The metallic pads 313 are in contact with the two-doped regions and constitute the electrode means of the source and drain regions of a non-volatile memory device. Formation of the metallic pads may be realized by the conventional manner of photolithography-assisted patterning, dry or wet etching of the dielectric layer 312 in the regions not protected by the photo-resist, metal deposition and lift-off of the patterned photo-resist. Optionally, a thermal treatment may follow to insure a good electrical contact between the metallic pads 313 and the two-doped regions 31 1.

In the next stage of the process according to one embodiment of the present invention, as shown in FIG. 5d, a layer 314 may be formed on the top surface of the structure shown in Fig. 5c. Layer 314 is made of a material that contains proton-trapping sites. In one example arrangement, the layer 314 includes basic sites. In one arrangement of the embodiment, the basic sites may come from strong bases selected from primary, secondary or tertiary amine. In another example arrangement the basic sites may come from weak or medium bases selected from ether, ester, hydroxyls, or amides. In another example arrangement the basic sites are nitrogen-containing group attached to atoms other than carbon and hydrogen. Layer 314 may be formed from basic-sites containing solutions using spin coating or dip coating techniques, or from techniques of evaporation or chemical vapour deposition of basic-site containing molecules. In one example arrangement the thickness of the layer 314 may be in the range of about 1 to 300 nm, more preferably less than about 150 nm. Following formation of the layer 314, a thermal treatment may be applied to for the purpose of solvent evaporation and chemical stability improvement. In one example arrangement, the thermal treatment may be conducted under vacuum or atmospheric pressure in inert or room ambient at temperatures in the 40 to 200⁰C range, more preferably from about 5O⁰C to about 17O⁰C.

In the next stage of the process, as shown in FIG. 5d, a layer 315 may be formed on the top surface of the layer 314. Layer 315 is made of proton-conducting polymeric material. In one example arrangement, the layer 315 comprises a strong acid. In one arrangement of the embodiment, the strong acid is selected from the classes of hetero-polyacids of tungsten, sulfonic acids or fluorinated super acids or their derivatives. Layer 315 may be formed from strong acid containing solutions using spin coating or dip coating techniques, or from techniques of evaporation or chemical vapour deposition of strong acid containing materials. In one example arrangement the thickness of the layer 315 may be in the range of about 5 to 300 nm, more preferably less than about 200 nm. Following formation of the layer 315, a thermal treatment may be applied for the purpose of solvent evaporation and chemical stability improvement. In one example arrangement, the thermal treatment may be conducted under vacuum or atmospheric pressure in inert or room ambient at temperatures in the 40 to 200⁰C range, more preferably from about 5O⁰C to about 17O⁰C. In the next stage of the process according to one embodiment of the present invention, as shown in FIG. 5d, a layer 316 may be formed on the top surface of the layer 315. Layer 316 is made of a material that contains proton-trapping sites. In one example arrangement the layer 316 includes basic sites. In one arrangement of the embodiment the basic sites may come from strong bases selected from primary, secondary or tertiary amine. In another example arrangement the basic sites may come from weak or medium bases selected from ether, ester, hydroxyls, or amides. In another example arrangement the basic sites are nitrogen containing groups attached to atoms other than carbon and hydrogen. Layer 316 may be formed from basic-sites containing solutions using spin coating or dip coating techniques, or from techniques of evaporation or chemical vapour deposition of basic-site containing molecules. In one example arrangement the thickness of the layer 316 may be in the range of about 1 to 300 nm, more preferably less than about 150 nm. Following formation of the layer 316, a thermal treatment may be applied to for the purpose of solvent evaporation and chemical stability improvement. In one example arrangement, the thermal treatment may be conducted under vacuum or atmospheric pressure in inert or room ambient at temperatures in the 40 to 200⁰C range, more preferably from about 5O⁰C to about 17O⁰C.

The stack of the layers 314, 315 and 316, constitutes a Proton Memory Component (PMC) which forms part of a memory device structure. Layers 314 and 316 allow trapping of protons within the PMC and ensure the non-volatile memory function of an electronic memory device (also referred herein as a non-volatile memory device). The first surface of the layer 314 is in contact with the dielectric layer 312, the second surface of the layer 314 is in contact with a first surface of layer 315. A second surface of the layer 315 is in contact with a first surface of the top layer 316. Of course, the use to the term "surface" as used in relation to the first and second surfaces of all of the layers described herein is intended to make reference to a Generalised boundary line between layers for illustrative purposes only and need not be interpreted as an actual surface of the respective layer.

In an example arrangement of the embodiment, the process conditions for producing the stack of layers 314, 315 and 316 include: (a) formation of a 80 nm-thick PMMA-Amine layer by spin-coating; (b) thermal treatment in a conventional atmospheric furnace at 120⁰C for 60 min; (c) formation of a 100 nm-thick PMMA-POM layer over the said 80 nm-thick PMMA-Amine layer; (d) thermal treatment in an atmospheric furnace at 120⁰C for 60 min; (e) formation of a 80 nm-thick PMMA-Amine layer by spin-coating over the said PMMA-POM layer; (f) thermal treatment in a conventional atmospheric furnace at 120⁰C for 60 min. In a next stage of the process according to one embodiment of the present invention, as shown in FIG. 5e, an electrically conductive gate layer 317 is deposited on the top of the stack of layers 314, 315 and 316 (ie. on a second surface of the top layer 316).

The gate layer 317 is preferably a metallic layer or a stack of metallic layers obtained by deposition techniques of metals, like evaporation or sputtering.

In a next stage of the process, as shown in FIG. 5f, a photo-resist layer 318 is selectively formed by the conventional manner of photolithography on the top of the conductive gate layer 317 (ie. on a second surface of the conductive gate layer 317 - the first surface thereof being in contact with the top layer 316).

In the next stage of the process, as shown in FIG. 5g, the structure made of the conductive gate layer 317 and the stack of the three layers 314, 315 and 316, that is unmasked by the photo-resist layer 318, is etched until the dielectric layer 312 and the metallic pads 313 are exposed. Etching of the conductive gate layer 317 and the stack of layers 314, 315 and 316 unmasked by the photo-resist layer may be conducted using wet solutions or dry techniques like reactive ion etching or a combination of both. Finally, the remaining photo-resist is stripped away. The resulting memory device structure shown in FIG. 5g comprises a MISFET-type device with a PMC made of the stack of layers 314, 315 and 316 that is sandwiched between the dielectric layer 312 and the conductive gate layer 317. The symbols 323, 320, 321 and 322 denote externally accessible electrical contacts attached to the semiconductor substrate 310, the conductive gate layer 317, the source and drain electrode means 313 of the MISFET-type device, respectively.

According to the above embodiment of the present invention, the PMC is made of the stack of the layers 314, 315 and 316. The layers 314 and 316 are both produced for the purpose of trapping protons and of ensuring a non-volatile function to an electronic memory device. In other arrangements of the above embodiment of the present invention, PMCs may be formed in which only one of the two layers 314 and 316 is added to the layer 315. It is understood that in the case of PMCs made of either the stack of layers 314 and 315 or the stack of layers 315 and 316, the layers 314 and 316 are still produced for the purpose of trapping protons and of ensuring a non-volatile function to electronic memory devices using them.

In another arrangement of one embodiment of the present invention, the step of formation of the layer 314, as described in FIG. 5d, may be dropped and therefore, the PMC is made of the stack of layers 315 and 316 where: (a) the first surface (ie. the bottom surface) of the layer 315 is in contact with the second surface (ie. the top surface) of the dielectric layer 312; (b) the second surface of the layer 315 is in contact with the first surface of the layer 316; (c) the second surface of the layer 316 is in contact with the first surface of the conductive gate layer 317. The resulting memory device structure is shown in FIG. 6. It comprises a MISFET-type device with a PMC made of the stack of layers 315 and 316 that is sandwiched between the dielectric layer 312 and the conductive gate layer 317.

In another arrangement of one embodiment of the present invention, the step of formation of the layer 316, as described in FIG. 5d, may be dropped and therefore, the PMC is made of the stack of layers 314 and 315 where: (a) the first surface (ie. the bottom surface) of the layer 314 is in contact with the second surface (ie. the top surface) of the dielectric layer 312; (b) the second surface of the layer 314 is in contact with the first surface of the layer 315; (c) the second surface of the layer 315 is in contact with the first surface of the conductive gate layer 317. The resulting memory device structure is shown in FIG. 7. It comprises a MISFET-type device with a PMC made of the stack of layers 314 and 315 that is sandwiched between the dielectric layer 312 and the conductive gate layer 317.

The operation of a memory device using the PMCs, as shown in FIGS. 5g, 6, and 7 might be most readily understood by study of FIGS 8a-8d, 9a-9d, 10a-IOd, and 11a-b.

FIGS. 8a-d describe an embodiment of the invention with a memory device structure as illustrated in FIG. 5g (ie. a MISFET-type device with a PMC made of the stack of the layers 314, 315 and 316). In an arrangement of the embodiment, the semiconductor substrate 310 is made of p-type silicon material and the source and drain regions 311 are n+-doped regions of 310. According to one arrangement, as described in FIG. 8a, the proton-conducting polymeric material 315 comprises anions 336 and is depleted from the protons 335. The said protons 335 are trapped in proton-trapping sites of layer 316. According to another arrangement of the embodiment, as described in FIG. 8c, the proton- conducting polymeric material 315 comprises anions 337 and is depleted from the protons 338. The said protons 338 are traoped in proton-trapping sites of layer 314.

It is understood in the foregoing or following embodiments of the present invention that the proton-trapping sites of a layer made of a material containing proton-trapping sites refer to proton-trapping sites located either in the bulk of the said layer or at the interface between said layer and a layer made of a proton-conducting polymeric material, or both.

The spatial distributions of ionic charges within the PMC made of the stack of the layers 314, 315 and 316, as shown in FIGS. 8a and 8c, may be achieved by producing an electric field normal to the said PMC (ie. normal to the surfaces of the PMC) starting from initial conditions where no ionic charge distribution occurs across the PMC (referred herein as equilibrium state of the device) Such an electric field may be produced by applying a programming voltage to the gate electrical contact 320 attached to the conductive gate layer 317, with the substrate 323, source 321 , and drain 322 electrical contacts connected to ground The electric field produced within the PMC allows dissociation of all or part of the acid molecule population of layer 315 into protons and anions

In one arrangement of the embodiment the programming voltage is negative and the produced electric field moves protons towards the too surface of layer 315, leaves the anions 336 in layer 315, and allows tapping of moved protons 335 in proton-trapping sites of layer 316 The resulting spatial distribution of ionic charges within the said PMC, as shown in FIG 8a, may be interpreted as the logic state O' of the memory device The source-drain current (I_DS) versus the gate-source voltage (V_GS) characteristics of the memory device with such a spatial distribution of ionic charges within the PMC, is shown in FIG 8b

In another arrangement of the embodiment, the spatial distribution of ionic charges within the PMC, as described in FIG 8a, may be modified by supplying a programming positive voltage to 320 The programming positive voltage produces an electric field that (1) de-traps (ιe releases) the protons 335 from the proton-trapping sites of layer 316, (2) moves protons towards the bottom surface of layer 315, (3) forms the anions 337 and, (4) allows trapping of the moved protons 338 in proton-trapping sites of layer 314 The resulting spatial distribution of ionic charges within the said PMC, as shown in FIG 8c, may be interpreted as the logic state '1 ' of the memory device The source-drain current (l_Ds) versus the gate-source voltage (V_Gs) characteristics of the memory device in the logic state '1' are described in FIG 8d Compared to FIGS 8a-b, the spatial distribution of ionic charges, as shown in FIG 8c, induces a shift in the !_DS ^Λ/ _CS characteristics of the memory device towards the negative direction of V_Gs-axιs (ιe decreases the threshold voltage of the MISFET memory device) To sense the logic state of the memory device, the source-drain current is measured at a gate-source voltage, V_read The measured low current I₀ of FIG 8b and high current I₁ of FIG 8d correspond to the logic states '0' and '1' of the memory device, respectively

In the foregoing or following embodiments, the magnitude of the gate-source voltage V_read supplied to 320 is selected preferably in such a way that the read operation does not destroy the information in the addressed PMC (commonly referred as non-destructive readout) In another arrangement of the embodiment, a logic state '0' of the memory device, as described in FIGS. 8a-b, may be obtained starting from a logic state T, as described in FIGS. 8c-d. In this case, the spatial distribution of ionic charges within the PMC, as shown in FIG. 8c, may be modified by supplying a programming negative voltage to 320. The programming negative voltage produces an electric field that: (1) de-traps (ie. releases) the protons 338 from the proton-trapping sites of layer 314, (2) moves protons towards the top surface of layer 315, (3) forms the anions 336 and, (4) allows trapping of the moved protons 335 in proton-trapping sites of layer 316.

It is understood that in the foregoing or following embodiments, the threshold voltage of the memory device corresponding to a programming state depends on the magnitude of the programming negative or positive voltage supplied to 320.

In the foregoing or following embodiments, the memory device could be fabricated with a semiconductor substrate 310 made of n-type silicon material and p+-doped regions of 310 as the source and drain regions 311.

FIGS. 9a-d describe an embodiment of the invention with a memory device structure as shown in FIG. 6 (ie. a MISFET-type device with a PMC made of the stack of the layers 315 and 316). In an arrangement of the embodiment, the semiconductor substrate 310 is made of p-type silicon material and the source and drain regions 31 1 are n+-doped regions of 310. According to one arrangement of the embodiment, as described in FIG. 9a, the layer 315 comprises the anions 336 and is depleted from the protons 335. The said protons 335 are located in proton-trapping sites of layer 316. The spatial distribution of ionic charges within the PMC made of the stack of the layers 315 and 316, as described in FIG. 9a, may be obtained by supplying a programming negative voltage to the gate electrical contact 320 with the substrate 323, source 321 , and drain 322 electrical contacts connected to ground. Such a spatial distribution of ionic charges within the said PMC may be interpreted as the logic state O' of the memory device. The source-drain current (l_Ds) versus the gate-source voltage (V_GS) characteristics of the memory device in the logic state O' are shown in FIG. 9b.

In another arrangement of the embodiment, the spatial distribution of ionic charges within the PMC made of the stack of the layers 315 and 316, as shown in FIG. 9a, may be modified by supplying a programming positive voltage to 320. The programming positive voltage produces an electric field that de-traps (ie. releases) the protons 335 from the proton-trapping sites of layer 316 and moves said protons 335 to layer 315. The resulting ionic charge neutralization in layer 315 arising from the association of protons and anions, as shown in FIG. 9c, may be interpreted as the logic state '1 ' of the memory device. The source-drain current (I_DS) versus the gate-source voltage (V_Gs) characteristics of the memory device in the logic state T are shown in FIG. 9d. To sense the logic state of the memory device, the source-drain current is measured at a gate-source voltage, V_read- The measured low current I₀ of FIG. 9b and high current I₁ of FIG. 9d correspond to the logic states '0' and T of the memory device, respectively.

FIGS. 10a-d describe an embodiment of the invention with a memory device structure as shown in FIG. 7 (ie. a MISFET-type device with a PMC made of the stack of the layers 315 and 314). In an arrangement of the embodiment, the semiconductor substrate 310 is made of p-type silicon material and the source and drain regions 31 1 are n+-doped regions of 310. According to one arrangement, as described in FIG. 10a, the layer 315 comprises anions 337 and is depleted from the protons 338. The said protons 338 are located in proton-trapping sites of layer 314. The spatial distribution of ionic charges within the PMC made of the stack of the layers 315 and 314, as described in FIG. 10a, may be obtained by supplying a programming positive voltage to the gate electrical contact 320 with the substrate 323, source 321 , and drain 322 electrical contacts connected to ground. Such a spatial distribution of ionic charges within the said PMC may be interpreted as the logic state '1' of the memory device. The source-drain current (l_Ds) versus the gate-source voltage (V_GS) characteristics of the memory device in the logic state '1' are shown in FlG. 10b.

In another arrangement of the embodiment, the spatial distribution of ionic charges within the PMC made of the stack of the layers 315 and 314, as shown in FIG. 10a, may be modified by supplying a programming negative voltage to 320. The programming negative voltage produces an electric field that de-traps the protons 338 from the proton-trapping sites of layer 314 and moves the protons 338 to layer 315. The resulting charge neutralization in layer 315, as shown in FIG. 10c, may be interpreted as the logic state '0' of the memory device. The source-drain current (l_Ds) versus the gate-source voltage (V_Gs) characteristics of the memory device in the logic state '0' are shown in FIG. 10d. To sense the logic state of the memory device, the source-drain current is measured at a gate-source voltage, V_read- The measured low current I₀ of FIG. 10d and high current I₁ of FIG. 10b correspond to the logic states '0' end '1' of the memory device, respectively.

In the above described electronic memory devices, the spatial distributions of ionic charges within the PMCs are achieved by producing an uniform electric field normal to the

PMCs (i e normal to the bottom and top surfaces of the PMCs). Such an electric field may be produced by supplying a programming voltage to the gate electrical contact 320 attached to the conductive gate layer 317, with the substrate 323, source 321 , and drain 322 electrical contacts connected to ground. In other embodiments of the invention, an electric field within a PMC may be produced for the purpose of creating a spatial distribution of ionic charges that is locally confined to a region of the PMC; the latter region being situated near either one of the two doped regions 311 or both the two doped regions 31 1 (ie. near the source or/and drain regions of the memory device), as shown in FIGS. 11a and 11 b.

FIGS. 11a-b describe embodiments of the invention with a memory device structure as shown in FIG. 7 (ie. a MISFET-type device with a PMC made of the stack of the layers 315 and 314). According to one embodiment, as described in FIG. 11a, the layer 315 comprises anions 340 and is depleted from the protons 341. The said protons 341 are located in proton-trapping sites of layer 314. The spatial distribution of ionic charges locally confined within the PMC made of the stack of the layers 315 and 314, as described in FIG. 1 1a, may be obtained by supplying a programming negative voltage to the source electrical contact 321 with the substrate 323, gate 320, and drain 322 electrical contacts connected to ground. According to another embodiment, as described in FIG. 11 b, the layer 315 comprises anions 342 and is depleted from the protons 343. The said protons 343 are located in proton-trapping sites of 314. The spatial distribution of ionic charges locally confined within the PMC made of the stack of the layers 315 and 314. as described in FIG. 1 1b, may be obtained by supplying a programming negative voltage to the drain electrical contact 322 with the substrate 323, gate 320, and source 321 electrical contacts connected to ground.

It is understood that spatial distributions of ionic charge locally confined within a PMC made of the stack of the layers 315 and 314 may be also produced for proton memory elements either made of the stack of the layers 315, 316 and 314, as shown in FIG. 5g, or made of the stack of the layers 315 and 316 as shown in FIG. 6.

In the foregoing embodiments of the present invention, a PMC may comprise, in addition to layer 315 (ie. a layer made of a proton-conducting polymeric material), either the layer 314 or the layer 316, or both layers 314 and 316. The layers 314 and 316 are made of a material that contain proton-trapping sites and are produced for the purpose of ensuring a non-volatile memory function to an electronic memory device (referred herein as a nonvolatile memory device). In other embodiments of the present invention, a PMC may be formed using only a layer made of a proton-conducting polymeric material. In that case, an electronic memory device with a volatile memory function (referred herein as a volatile memory device) may be produced, as it will become apparent through the description which follows with respect to the accompanying drawings that illustrate, by way of example, embodiments of the present invention.

Reference is made to FIGS. 12a and 12b that illustrate portions of a memory device structure according to an embodiment of the invention for fabricating a volatile memory device. The memory device structure, as described in FIGS. 12a-b, comprises a semiconductor substrate 310 with two-doped regions 31 1 that form the source and drain regions of the memory device, two source and drain electrode means 313 attached to the doped regions 311 , a dielectric layer 312 formed onto the semiconductor substrate 310 and the doped-regions 311 , a PMC made of a proton-conducting polymeric material layer 315 that is formed onto the top surface of the dielectric layer 312, a layer 350 formed onto the top surface of said layer 315 and a electrically conductive gate layer 317 formed onto the top surface of layer 350. The symbols 323, 320, 321 and 322 denote electrical contacts attached to the semiconductor substrate 310, the conductive gate layer 317 and the source and drain electrode means 313, respectively. In an arrangement of the embodiment, the semiconductor substrate 310 is made of p-type silicon material and the source and drain regions 31 1 are n+-doped regions of 310. Layer 350 is formed for the purpose of preventing possible escape of protons from layer 315 towards the conductive gate layer 317. Layer 350 may be made of an organic or inorganic dielectric material such as but not limited to silicon oxide or PMMA. Layer 350 may also be made of a metallic material if said metallic material is substantially impervious to migration of protons. In an arrangement of the embodiment, a conductive gate layer made of a material that is substantially impervious to migration of protons may be formed onto the top surface of the PMC (ie. onto the second surface of the layer 315).

In an arrangement of the embodiment, as illustrated in FIG. 12a, no spatial gradient of ionic charges occurs across the layer 315. This may be interpreted as the equilibrium state of the memorv device. In another arrangement of the embodiment, a spatial distribution of ionic charges, as shown in FIG. 12b, may be produced within the PMC made of the layer 315. Such a charge distribution may be obtained by applying a programming positive voltage to the gate electrical contact 320 with the substrate 323, source 321 , and drain 322 electrical contacts connected to ground. A programming positive voltage produces an electric field that dissociates all or part of the acid molecule population of layer 315 into protons and anions, and moves protons towards the bottom surface (ie. the first surface) of 315. This may result in a charge distribution across the PMC, as described in FIG. 12b. due to anions 352 and mobile protons 351. Such a spatial distribution of ionic charges may be interpreted as the programming state of the memory device. In the time that follows the application of the programming voltage, the mobile protons 351 move back to anions and progressively associate with anions, while the anions 352 recombine with mobile protons. This may be interpreted, as a relaxation process of the spatial charge distribution within the layer 315 or return to the equilibrium state of the memory device; a feature of a volatile memory device. To sense the state of the memory device, the source- drain current is measured at a gate-source voltage, V_read- During the said return to the equilibrium state, the source-drain current (l_Ds) versus the gate-source voltage (V_Gs) characteristics of the memory device moves towards the positive direction of the V_GS axis and as a result, the magnitude of the source-drain current at V_read decreases. To maintain, after application of the programming voltage, a source-drain current at V_read which can be differentiated from that of the equilibrium state, a programming voltage must again be applied to the gate electrical contact 320; the latter is commonly referred as a memory refresh process.

Of course, in other arrangements of the above embodiment, a volatile memory device may be programmed by producing an electric field across the memory element that releases protons from the counter anions, moves protons towards the top surface (ie. the second surface) of layer 315, and forms anions. Such an electric field may be produced by applying a programming negative voltage to the gate electrical contact 320 with the substrate 323, source 321 , and drain 322 electrical contacts connected to ground. This results in a spatial distribution of ionic charges across the PMC due to anions and protons; the said protons having the tendency to accumulate in a region of layer 315 underneath the top surface of layer 315.

Reference is now made to FIGS. 13a-13c that 'llustrate a series of process steps according to an embodiment of the invention for fabricating a non-volatile memory device using a organic FET (ie. a field-effect-transistor with a channel made of a semiconducting organic material). The described processing steps in FIGS. 13a-13c and the related structures do not form a complete process for manufacturing such a non-volatile memory device, but they are necessary for an understanding of the application of embodiments of the present invention. FIGS. 13a-13c represent cross-sections of portions of a non-volatile memory device structure and are not drawn to scale but instead are drawn so as to illustrate the important features of the invention.

FIG. 13a illustrates a portion of a non-volatile memory device structure that includes an electrically conductive gate layer 810 with a PMC made of the stack of layers 811 , 812 and 813 thereon. In one arrangement, the gate layer 810 may be made of a metallic material, like but not limited to gold or aluminium, or a combination of metallic materials that may be produced on rigid or flexible substrates by deposition techniques known in the art, such as electron-beam-evaporation or sputtering, in another arrangement, the gate layer 810 may be made of a polymeric material or a metal-containing-polymeric material (ie. a material comprising metallic and polymeric components), like but not limited to graphite- based-polymer paste, that may be produced on rigid or flexible substrates by deposition techniques known in the art, such as chemical vapour deposition or spin-coating. In another arrangement, the gate layer 810 may be made of a doped semiconducting material, like a layer of boron or phosphorus doped mono-crystalline or poly-crystalline silicon, produced on rigid or flexible substrates by deposition techniques known in the art, such as low-pressure chemical vapour deposition or wafer bonding.

The PMC formed onto the top surface of the conductive gate layer 810 is made of the stack of the successively formed layers 811 , 812 and 813. The layers 811 and 813 are made of a material that contains proton-trapping sites. In one example arrangement, the layer 811 or the layer 813 or both of them include basic sites. In one arrangement of the embodiment, the basic sites may be strong basic sites selected from primary, secondary or tertiary amine. In another example arrangement the basic sites are weak or medium basic sites selected from ether, ester, hydroxyls, or amides. In another example arrangement the basic sites are nitrogen-containing groups attached to atoms other than carbon and hydrogen. Layers 811 and 813 may be formed from basic-sites containing solutions using spin coating or dip coating techniques, or from techniques of evaporation or chemical vapour deposition of basic-site containing molecules. In one example arrangement the thickness of layers 811 and 813 may be in the range of about 1 to 300 nm, more preferably less than about 150 nm. Laver 812 that is sandwiched between the top surface (ie. the second surface) of layer 811 and the bottom surface (ie. the first surface) of layer 813, as described in FIG. 13a, is made of proton-conducting polymeric material. In one example arrangement, the layer 812 comprises strong acid. In one arrangement of the embodiment, the strong acid is selected from the classes of hetero-polyacids of tungsten, sul^fonic acids or fluorinated super acids or their derivatives. Layer 812 may be formed from strong acid containing solutions using spin coating or dip coating techniques, or from techniques of evaporation or cherrvcal vapour deposition of strong acid containing materials. In one example arrangement the thickness of layer 812 may be in the range of about 5 to 300 nm, more preferably less than about 200 nm. Following each of the three process steps consisting of. (1) formation of layer 811 onto the top surface of the conductive gate layer 810, (2) formation of layer 812 onto the top surface of layer 81 1 , and (3) formation of layer 813 onto the top surface of layer 812. a thermal treatment may be applied to for the purpose of solvent evaporation and chemical stability improvement. In one example arrangement, the thermal treatment may be conducted under vacuum or atmospheric pressure in inert or room ambient at temperatures in the 40 to 200 ⁰C range, more preferably from about 50 ⁰C to about 170 ⁰C

In a next stage of ihe process according to one embodiment of the present invention, as shown in FIG 13b, a layer 814 made of a semiconducting polymeric or oligomeric organic material, like but not limited to poly(3-substιtuted thιophene)s or pentacene or rubrene or phthalocyanines is formed on the top of the PMC made of the stack of layers 811 , 812 and 813 (ιe on a second surface of the top layer 813) The semiconducting organic material 814 may be obtained from aqueous or organic solutions using spin coating, spraying or dip coating techniques, or by vacuum evaporation

In a next stage of the process according to one embodiment of the present invention as shown in FIG 13c, the source and drain electrode means of the memory device are formed onto the top surface (ιe the second surface) of the semiconducting organic layer 814 Formation of the source and drain electrode means may be achieved by selective deposition through a shadow mask of an electπcally conductive 'ayer 815 In one example arrangement, layer 815 may be made of a metallic material, like but not limited to gold or aluminium, or a combination of metallic materials that may be produced by deposition techniques known in the art, such as electron-beam-evaporation or sputtering In another arrangement, layer 815 may be made of a polymeric materia! or a metai-containing- polymeπc material (ιe a material comprising metallic and polymeric components), like but not limited to graphite-based-polymer paste, that may be produced by deposi^tion techniques known in the art, such as chemical vapour deposition

The memory device structure shown in FIG 13c comprises an organic FET-type device with a PMC made of the stack of layers 811 , 812 and 813 that is sandwiched between the conductive gate layer 810 and the semiconducting organic layer 814 The symbols 816, 817 and 818 denote electrical contacts, attached to the source and drain electrode means 815 and the conductive gate layer 810 of the organic FET-type device, respectively According to one arrangement of the embodiment, a memory device, as shown in FlG 13c may be conducted in different logic states by producing an electric field within the PMC Such an electric field mav be produced by supplying a negative or positive programming voltage to the gate electrical contact 8 I 8 attached to the conductive gate layer 810 with the source 816 and dram 817 electrical contacts connected to ground A negative programming voltage allows traooing of proton? in proton-trapping sites of layer 811 , while a positive programming voltage allows trapping of protons in proton-trapping sites of layer 813 To sense the logic state of the memorv device the source-drain current is measured at a gate-source voltage, V_read According to the above embodiment of the present invention, the PMC is made of the stack of the layers 81 1 , 812 and 813. The layers 811 and 813 are both produced for the purpose of trapping protons and of ensuring a non-volatile function to an electronic memory device. In other arrangements of the above embodiment of the present invention, PMCs may be formed in which only one of the two layers 811 and 813 is added to the layer 812. It is understood that in the case of PMCs made of either the stack of layers 811 and 812 or the stack of layers 812 and 813, the layers 811 and 813 are still produced for the purpose of trapping protons and of ensuring a non-volatile function to electronic memory devices using them.

When used in this specification the term "preferably" (and any other similar term) is not necessarily intended to indicate features that must form part of the invention. The term

"about" is intended to incorporate values of approximately the same stated value, wherein that the effect of the approximate value is substantially unchanged (in terms of the advantages achieved) when compared with that of the stated value.

When used in their specification and claims, the terms "comprises" and "comprising" and variations thereof mean that the specified features, steps or integers are included. The terms are not to be interpreted to exclude the presence of other features, steps or components.

The features disclosed in the foregoing description of the invention, or the following claims, or the accompanying drawings, expressed in their specific forms or in terms of a means for performing the disclosed function, or a method or process for attaining the disclosed result, as appropriate, may, separately, or in any combination of such features, be utilised for realising the inventicn in diverse forms thereof

It is understood that while the present invention has been described in details, with reference to preferred embodiments, other modifications, substitutions, alterations or changes of this invention beyond the embodiments may be made without departing from the spirit of the invention. Accordingly, the present invention is intended to be limited only as defined by the appended claims.

Claims

I . A memory transistor comprising a proton memory component, said memory component comprising a first layer comprising a proton-conducting polymeric material. 2. A memory transistor comprising a proton memory component according to claim 1 , wherein the first layer comprises strong acid.

3. A memory transistor comprising a proton memory component according to claim 2, wherein the strong acid is selected from the classes of hetero-polyacids of tungsten, sulfonic acids or fluorinated super acids or their derivatives. 4. A memory transistor comprising a proton memory component according to any preceding claim, wherein the first layer has a thickness in the range of 5 to 300nm.

5. A memory transistor comprising a proton memory component according to any preceding claim, wherein the first layer of the proton memory component has a thickness less than 200nm. 6. A memory transistor comprising a proton memory component according to any preceding claim, further comprising electrodes arranged for applying an electric field across the first layer for the purpose of moving protons across the first layer.

7. A memory transistor comprising a proton memory component according to any preceding claim, said memory component further comprising a second layer, made of a material that contains proton trapping sites, located on a surface of the first layer.

8. A₁ proton memory component according to claim 7, further comprising a third layer, made of a material that contains proton trapping sites, located on the opposite surface of the first layer in order to obtain a proton memory component comprising a stack of three layers where the first layer is located between the second and third layers. 9. A proton memory component according to claim 7 or 8, wherein the second layer comprises basic sites.

10. A proton memory component according to claim 8. wherein the third layer comprises basic sites.

I I . A proton memory component according to claim 9 or 10, wherein the basic sites come from strong bases selected from primary, secondary or tertiary amine.

12. £. proton memory component according to claim 9 or 10, wherein the basic sites come from weak or medium bases selected from ether, ester, hydroxyls, or amides.

13. A proton memory component according to claim 9 or 10, wherein the basic sites are nitrogen containing groups, where the nitrogen atoms are attached to atoms other than carbon and hydrogen.

14. A proton memory component according to any one of claims 7 to 13, wherein at least one said layer made of a material that contains proton trapping sites has a thickness in the range of 1 to 300nm. 15 A proton memory component according to claim 14, wherein said thickness is less than 150nm

16 A memory transistor comprising a semiconductor substrate, drain and source regions in the semiconductor substrate, a proton memory component according to any of claims 1 to 15 provided on the substrate, and, a conductive gate layer provided on the surface of the proton memory component opposite to the substrate

17 A memory transistor according to claim 16, further comprising a silicon oxide layer between the substrate and the proton memory component

18 A memory transistor according to claim 16 or 17, wherein the conductive gate layer is a metallic layer or a stack of metallic layers

19 A memory transistor comprising a rigid or flexible substrate with a conductive gate layer thereon, a proton memory component according to any of claims 1 to 15 provided on the conductive gate layer, a layer made of semiconducting organic material provided on the proton memory component, and, drain and source electrodes provided on the layer made of semiconducting organic material

20 A memory transistor according to claim 19 wherein the gate layer is made of a metallic material or a polymeric material or a combination of metallic and polymeric materials

21 A memory transistor according to claim 19 or 20 wherein the semiconducting organic material is made of polymeric or oiigomeric organic material

22 A memory transistor according to claim 21 wherein the semiconducting organic material is selected from poly(3-substιtuted thιoohene)s, pentacene, rubrene or phthalocyanines

23 A memory transistor comprising a semiconductor substrate, drain and source regions in the semiconductor substrate, a proton memory component according to any one of claims 1 to 6 provided on the substrate, and, a conductive gate layer provided on the surface of the proton memory comoonent opposite to the substrate

24 A memory transistor according to claim 23, further comp^rιsιng a silicon oxide layer between the substrate and the proton memory componeπi 25 A memory transistor according to claim 23 or 24, further comprising a dielectric layer impervious to migration of protons provided between the proton memory component and the conductive gate layer

26 A memory transistor according to claim 25, wherein *ne die'ectric layer is made of a polymeπc material 27 A method of producing a memory transistor comoπsmg a proton memory component by forming a stack of layers consisting of a first layer of proton-conducting polymeric material

28. A method according to claim 27, further comprising a second layer, made of a material that contains proton trapping sites, positioned on a surface of the first layer.

29. A method according to claim 27 or 28, wherein the first layer of the proton memory component is produced by spin-coating of a solution containing a proton-conducting polymeric material and subsequent baking at a temperature between 50 to 170 degrees C.

30. A method of operating a memory transistor comprising a proton memory component according to any one of claims 7 to 15, comprising applying an electric field across the layers for the purpose of moving protons across the first layer, and trapping in and/or de- trapping protons from a layer made of a material that contains proton trapping sites.