CN101162738B - Non-volatility memory and manufacturing method thereof - Google Patents
Non-volatility memory and manufacturing method thereof Download PDFInfo
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- CN101162738B CN101162738B CN2006101318661A CN200610131866A CN101162738B CN 101162738 B CN101162738 B CN 101162738B CN 2006101318661 A CN2006101318661 A CN 2006101318661A CN 200610131866 A CN200610131866 A CN 200610131866A CN 101162738 B CN101162738 B CN 101162738B
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Abstract
The invention provides a nonvolatile memorizer and a method of manufacturing the same. The nonvolatile memorizer comprises a base material and a stack architecture, wherein, the stack architecture is arranged on the base material and is positioned between a source region and a drain electrode area of the base material, the stack architecture at least comprises a tunneling oxide layer, a charge sinking layer and a dielectric layer, the charge sinking layer is arranged on the tunneling oxide layer, the dielectric layer is arranged on the charge sinking layer, the dielectric layer is a material with a specific inductive capacity and is converted from a first solid phase into a second solid phase by a technology, wherein the first solid phase is non-crystalline solid state, and the second solid phase is crystalline solid state.
Description
Technical field
The present invention relates to a kind of memory and manufacture method thereof, and particularly relate to a kind of non-volatility memorizer and manufacture method thereof.
Background technology
Non-volatility memorizer (Non-Volatile Memory, even NVM) when referring to stop the supply of electric power, but the memory of storage data still.According to the action whether data that store in the non-volatility memorizer can be changed, can be divided into read-only memory (Read-Only Memory, ROM) and two types of flash memories (flash memory).Read-only memory in the manufacture process of memory, just with the data burning in the circuit of memory.In case after the memory manufacturing is finished, only can read data wherein, can't carry out the renewal or the deletion of data.And the flash memory utilization provides the mode of voltage to programme (programming), erase (erasing) or reads actions such as (reading), that is to say that flash memory can carry out the renewal of data at any time according to user's demand.More because the volume of flash memory is little, in light weight and to have a low consumption electrical, many consumption electronic products all adopt flash memory to be used as the solution of storage problem in addition.
Yet in recent years along with the lightweight of consumption electronic products and the trend of multifunction, except the requirement for the volume of electronic product and weight, more the usefulness for electronic product has more and more high standard on the market.And utilize the electronic product of flash memory as storing media, its operational paradigm can be subjected to the influence of memory program/(program/erase) speed of erasing.
In the stack architecture of the silica nitrogen-oxygen-silicon (SONOS) of general flash memory, with the first silicon dioxide (SiO
2) layer, silicon nitride (SiN) layer, the second silicon dioxide (SiO
2) layer and a polysilicon (poly-Si) layer in regular turn storehouse to the semiconductor silicon substrate.Be stored in data in the memory and depend on electronics in the silicon nitride layer, by between control grid (gate), drain electrode (drain), source electrode (source) and silicon substrate, applying voltage, remove or accumulate electronics in the silicon nitride layer to produce strong electric field, changed data stored in the memory.Under (erase) operation of erasing, the electronics that is stored in the silicon nitride layer is removed; Under programming (program) operation, electronics accumulates in the silicon nitride layer.And in the stack architecture of silica nitrogen-oxygen-silicon, for keeping FN erasing speed (Fowler-Nordheim erase rate), the thickness of first silicon dioxide layer needs less than 3 nanometers (nanometer).And thin first silicon dioxide layer (as 2 nanometer to 3 nanometers) helps carrying out for example erase operation for use of passage hole injection (channel hole injection).Yet, the first thin silicon dioxide layer causes still having the phenomenon that electronics or hole are injected by passage when low electric field, or quicken to be stored in the possibility that runs off in electronics in the silicon nitride or hole, so deterioration memory preserve the characteristic of data (data retention).
In the stack architecture of above-mentioned silica nitrogen-oxygen-silicon, because the erasing speed (erase rate) of data influences the operational paradigm of memory significantly, therefore how to promote the data erasing speed of memory effectively, to promote the operational paradigm of flash memory integral body, simultaneously can keep memory good data keeping quality, real in demanding one of important topic of studying at present urgently.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of non-volatility memorizer and manufacture method thereof exactly, utilizes the material of the aluminium oxide of crystallization as dielectric layer, has the operating voltage of reduction, improves erasing speed and good advantages such as electric charge holding capacity.
According to purpose of the present invention, a kind of non-volatility memorizer is proposed, comprise a base material and a stack architecture.Base material has an one source pole district and a drain region.Stack architecture is arranged on the base material and between source area and drain region.Stack architecture comprises a tunnel oxide, a charge immersing layer and a dielectric layer at least.Charge immersing layer is arranged on the tunnel oxide, and dielectric layer is arranged on the charge immersing layer.Dielectric layer is the material with a dielectric constant, and by carrying out a technology, by the one first solid-state one second solid-state phase that changes into mutually, wherein this first solid-state be amorphous solid-state mutually, this second solid-state solid-state for crystallization mutually.
According to purpose of the present invention, other proposes a kind of manufacture method of non-volatility memorizer, may further comprise the steps.At first, provide a base material.Secondly, form a tunnel oxide on base material.Then, form a charge immersing layer on tunnel oxide.Then, form a dielectric layer on charge immersing layer, dielectric layer is the material with a dielectric constant, and by carrying out a technology, by the one first solid-state one second solid-state phase that changes into mutually, wherein this first solid-state be amorphous solid-state mutually, this second solid-state solid-state for crystallization mutually.Then, form a conductor layer on dielectric layer.Come again, define word line.At last, in an other one source pole district and the drain region of forming of stack architecture.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 illustrates the flow chart according to the manufacture method of non-volatility memorizer of the present invention;
Fig. 2 A illustrates the schematic diagram of the step 11 of Fig. 1;
Fig. 2 B illustrates the schematic diagram of the step 12 of Fig. 1;
Fig. 2 C illustrates the schematic diagram of the step 13 of Fig. 1;
Fig. 2 D illustrates the schematic diagram of the step 14 of Fig. 1;
Fig. 2 E illustrates the schematic diagram of the step 15 of Fig. 1;
Fig. 2 F illustrates the schematic diagram of the step 16 of Fig. 1;
Fig. 2 G illustrates the schematic diagram of the step 17 of Fig. 1; And
The performance diagram of erasing of non-volatility memorizer when the dielectric layer that Fig. 3 illustrates Fig. 2 G is annealed under different temperatures.
The simple symbol explanation
20: non-volatility memorizer
21: base material
22: tunnel oxide
23: charge immersing layer
24: dielectric layer
25: conductor layer
26: stack architecture
31,32,33,34: curve
D: drain region S: source area
Embodiment
Please be simultaneously with reference to Fig. 1 and Fig. 2 A～2G, Fig. 1 illustrates the flow chart according to the manufacture method of non-volatility memorizer of the present invention; Fig. 2 A～2G illustrates the schematic diagram of step 11～step 17 of Fig. 1 respectively.At first shown in step 11 and Fig. 2 A, provide a base material 21.Base material 21 for example is a P type doped substrate (P-type substrate) or a N type doped substrate.
Secondly, shown in step 12, form a tunnel oxide (tunneling oxide) 22 on base material 21.The material of tunnel oxide 22 is preferably silicon dioxide (silicon dioxide), and its thickness is greater than about 3 nanometers (nanometer).
Come again, carry out step 13, shown in Fig. 2 C, form a charge immersing layer 23 on tunnel oxide 22, for example be to utilize low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, mode LPCVD) forms charge immersing layer 23 herein.The material of charge immersing layer 23 is silicon nitride (silicon nitride) preferably, and its thickness is approximately between 3 nanometer to 10 nanometers.
Then, carry out step 14, and shown in Fig. 2 D, form a dielectric layer 24 on charge immersing layer 23, for example be to utilize ald (Atomic Layer Deposition, mode ALD) forms dielectric layer 24 herein.Dielectric layer 24 preferably has aluminium oxide (aluminum oxide) layer of the crystalloid (crystalline) of a dielectric constant, and its dielectric constant is preferably more than 6, and its thickness is approximately between 7 nanometer to 20 nanometers.
Then, carry out step 15, shown in Fig. 2 E, form a conductor layer 25 on dielectric layer 24.The material of conductor layer 25 is platinum (platinum) preferably.Because platinum has high work function (workfunction), therefore when carry out-during the FN erase operation for use, can reduce the phenomenon of gate electron injection (gate-injectedelectrons).Yet the material of conductor layer 25 is not limited thereto, and it also can be iridium (iridium), ruthenium (ruthenium), other metal (metal) or polysilicon (poly-silicon).
And then, carry out step 16,, define word line (Word line), shown in Fig. 2 F by for example being lithography corrosion process.
At last, carry out step 17, form an one source pole district S and a drain region D in base material 21.Tunnel oxide 22, charge immersing layer 23, dielectric layer 24 and conductor layer 25 are the stack architecture 26 in the non-volatility memorizer 20.Shown in Fig. 2 G, source area S and drain region D are positioned at the both sides of this stack architecture 26.
In the step 14 of above-mentioned Fig. 1, form the mode of the alumina layer of this crystallization, for example be the deposition of aluminium oxide material on charge immersing layer 23 after, with aluminium oxide at about 800 ℃ anneal to about 1200 ℃ temperature (annealing).More clearly be about 850 ℃ to about 950 ℃ temperature range and in nitrogen, through 60 seconds deposition after annealings (post deposition annealing), make the one first solid-state one second solid-state phase that mutually change crystalloid (crystalline) of alumina material by noncrystalline shape (amorphous).Right those skilled in the art's technology of the present invention as can be known under the present invention is not limited thereto, and anyly makes the alumina material crystallization and is formed at method on the charge immersing layer 23, all can be applicable to herein.
When dielectric layer 24 by the first solid-state second solid-state phase time that changes into mutually, the erasing speed of non-volatility memorizer 20 (erase rate) is changed into one second speed by a first rate, and second speed is greater than first rate.Please be simultaneously with reference to Fig. 3, the performance diagram of erasing of non-volatility memorizer when its dielectric layer that illustrates Fig. 2 G is annealed under different temperatures.Put on the grid voltage (V of conductor layer 25
G) be-20 volts (volt).In addition, learn that aluminium oxide starts and gives birth to the significantly phenomenon of crystallization under about 850 ℃ temperature conditions via experimental result.Therefore, curve 31 is annealed under 800 ℃ temperature for dielectric layer 24 in the stack architecture, and the characteristic curve of erasing of still uncrystallized amorphous aluminium oxide.Curve 32, curve 33 and curve 34 be for annealing under the temperature of dielectric layer 24 respectively at 850 ℃, 900 ℃ and 950 ℃, and produce the characteristic curve of erasing of the aluminium oxide of crystallization.As shown in Figure 3, at identical flat band voltage (flat band voltage, V
FB) condition under, the aluminum oxide dielectric layer 24 of under high-temperature more, annealing, it is shorter to get back to the required time of flat rubber belting state.That is to say, when high temperature, anneal, make non-volatility memorizer have higher erasing speed (erase rate) so that aluminum oxide dielectric layer 24 has good crystalline state.
Above-mentioned according to non-volatility memorizer of the present invention and manufacture method thereof, utilizing for example is the material of the aluminium oxide of crystallization as dielectric layer, and is formed on the charge immersing layer.Because the alumina layer of crystallization has improved the erasing speed of non-volatility memorizer, promptly promoted the efficient of non-volatility memorizer integral body.Similarly, also promoted the usefulness of the electronic installation of using non-volatility memorizer of the present invention.Secondly, in general non-volatility memorizer, do not increase any structure or material, so can not increase production cost according to non-volatility memorizer of the present invention.Moreover, only need increase the action that the dielectric layer that makes alumina material carries out crystallization according to non-volatility memorizer of the present invention, can be compatible with the manufacture method of original silica nitrogen-oxygen-silicon stack architecture, and can be applicable in the General N AND flash memory.In addition, owing to can shorten the time of erase operation for use according to non-volatility memorizer of the present invention, therefore under the condition of the identical time of erasing, compared to traditional non-volatility memorizer, the tunnel oxide that can have thicker (greater than about 3 nanometers) according to non-volatility memorizer of the present invention, and lower critical voltage (threshold voltage).Thus, can keep preferred data and preserve (data retention) characteristic.
In sum; though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (21)
1. non-volatility memorizer comprises:
Base material has source area and drain region; And
Stack architecture is arranged on this base material and between this source area and this drain region, this stack architecture comprises at least:
Tunnel oxide;
Charge immersing layer is arranged on this tunnel oxide; And
Dielectric layer, be arranged on this charge immersing layer, this dielectric layer is the material with dielectric constant, this dielectric layer by carry out technology by first solid-state change the second solid-state phase mutually into so that the erasing speed of this non-volatility memorizer when having this dielectric layer of this second solid-state phase greater than the erasing speed when having this dielectric layer of this first solid-state phase
Wherein this first solid-state be amorphous solid-state mutually, this second solid-state solid-state for crystallization mutually.
2. non-volatility memorizer as claimed in claim 1, the wherein step of this technology under 800 ℃ to 1200 ℃ temperature, annealing.
3. non-volatility memorizer as claimed in claim 2, the wherein step of this technology under 850 ℃ to 950 ℃ temperature, annealing.
4. non-volatility memorizer as claimed in claim 1, wherein this material is crystalloid aluminium oxide.
5. non-volatility memorizer as claimed in claim 1, wherein this dielectric constant of this material is greater than 3.9.
6. non-volatility memorizer as claimed in claim 1, wherein this stack architecture also comprises conductor layer, is arranged on this dielectric layer, in order to the control grid as this non-volatility memorizer.
7. non-volatility memorizer as claimed in claim 6, when wherein this non-volatile memory structure was erased action, the voltage of this conductor layer that puts on was negative voltage.
8. non-volatility memorizer as claimed in claim 6, wherein the material of this conductor layer is a metal.
9. non-volatility memorizer as claimed in claim 8, wherein the material of this conductor layer is platinum, iridium or ruthenium.
10. non-volatility memorizer as claimed in claim 1, wherein the thickness of this tunneling oxide layer is greater than 3 nanometers.
11. non-volatility memorizer as claimed in claim 1, wherein the thickness of this charge immersing layer is greater than 3 nanometers and less than 10 nanometers.
12. non-volatility memorizer as claimed in claim 1, wherein the thickness of this dielectric layer is greater than 7 nanometers and less than 20 nanometers.
13. non-volatility memorizer as claimed in claim 1, wherein this base material is P type doped substrate or N type doped substrate.
14. the manufacture method of a non-volatility memorizer comprises:
Base material is provided;
Form tunnel oxide on this base material;
Form charge immersing layer on this tunnel oxide; And
Form dielectric layer on this charge immersing layer, this dielectric layer is the material with dielectric constant, and by carry out technology with this dielectric layer by first solid-state change the second solid-state phase mutually into so that the erasing speed of this non-volatility memorizer when having this dielectric layer of this second solid-state phase greater than the erasing speed when having this dielectric layer of this first solid-state phase
Wherein this first solid-state be amorphous solid-state mutually, this second solid-state solid-state for crystallization mutually.
15. manufacture method as claimed in claim 14, the wherein step of this technology under 800 ℃ to 1200 ℃ temperature, annealing.
16. manufacture method as claimed in claim 15, the wherein step of this technology under 850 ℃ to 950 ℃ temperature, annealing.
17. manufacture method as claimed in claim 14, wherein this dielectric layer is crystalloid aluminium oxide.
18. manufacture method as claimed in claim 14, wherein this dielectric constant of this material is greater than 3.9.
19. manufacture method as claimed in claim 14 also comprises:
Form conductor layer on this dielectric layer;
Define word line; And
Form source area and drain region in this base material, and this source area and this drain region are positioned at by the stack architecture that this tunnel oxide, charge immersing layer, dielectric layer and conductor layer form.
20. manufacture method as claimed in claim 14, wherein this charge immersing layer utilizes the mode of low-pressure chemical vapor deposition to be formed on this tunnel oxide.
21. manufacture method as claimed in claim 14, wherein this dielectric layer utilizes the mode of ald to be formed on this charge immersing layer.
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| CN1755915A (en) * | 2004-09-27 | 2006-04-05 | 旺宏电子股份有限公司 | Charge-trapping memory devices and its programming and erasing method |
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| CN1755915A (en) * | 2004-09-27 | 2006-04-05 | 旺宏电子股份有限公司 | Charge-trapping memory devices and its programming and erasing method |
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