WO2009125932A2

WO2009125932A2 - Electrostatic capacitance detecting device, and an electrostatic capacitance sensor comprising the same

Info

Publication number: WO2009125932A2
Application number: PCT/KR2009/001492
Authority: WO
Inventors: 김수환; 박영준; 정인영; 이현중
Original assignee: 서울대학교산학협력단
Priority date: 2008-04-07
Filing date: 2009-03-24
Publication date: 2009-10-15
Also published as: KR100974637B1; WO2009125932A3; KR20090106849A

Abstract

An electrostatic capacitance detecting device comprises a control unit for integrating the charge difference between a first capacitor (which has a reference electrostatic capacitance) and a second capacitor in a first time interval (this process being referred to hereinbelow as the "integration process"), and for storing the integrated charge in a second time interval (this process being referred to hereinbelow as the "storage process"). Consequently, the electrostatic capacitance detecting device can detect electrostatic capacitance on the basis of the charge difference from the capacitor having the reference electrostatic capacitance.

Description

Capacitive detection device and capacitive sensor comprising the same

Embodiments of the present invention relate to a capacitive detection device and a capacitive sensor including the same.

Capacitive sensors can be used for human interface and machine control. Since capacitive sensors are in common use today, efficient capacitive sensors are required.

An object of the present invention is to provide a capacitance detection device.

Another object of the present invention to provide a capacitive sensor comprising the same.

According to an embodiment of the present invention, the capacitance detecting device integrates a difference in charge amount between a first capacitor (the first capacitor has a reference capacitance) and a second capacitor in a first time interval (hereinafter, referred to as an "integration process"). The second time period includes a controller for preserving the integrated charge amount (hereinafter, referred to as a "preservation process").

The first and second capacitors may respectively receive a first clock signal and a second clock signal having a complementary relationship with the first clock signal. For example, the first time period may correspond to a first transition time of the first and second clock signals, and the second time period may correspond to a second transition time of the first and second clock signals. Can be.

The controller may repeat the integration process and the preservation process for a predetermined time, a predetermined number of times, or until the integrated charge is greater than or equal to a predetermined reference.

The controller may include an integrator capable of integrating the difference in charge amount. According to one embodiment, the integrator is an integrating capacitor and the first time interval, an input terminal is connected to the first stage of each of the first capacitor, the second capacitor and the integrating capacitor, the output terminal is a second of the integrating capacitor It may include an operational amplifier connected to the stage. The output terminal may be connected to the first terminal in the second time interval.

For example, the capacitive detection device may be used for a capacitive sensor.

According to another embodiment of the present invention, a capacitive sensor includes a reference capacitor having a reference capacitance, a capacitor array including at least one capacitor connected to a first stage, and the at least one based on a capacitor address. The selector for selecting one of the capacitors and the first time period is integrated (hereinafter referred to as "integration process") the difference in the amount of charge between the selected one capacitor and the reference capacitor, the second time period is integrated It includes a control unit for preserving (hereinafter referred to as "preservation process").

The reference capacitor and the selected one capacitor may receive a first clock signal and a second clock signal having a complementary relationship with the first clock signal. For example, the first time period may correspond to a first transition time of the first and second clock signals, and the second time period may correspond to a second transition time of the first and second clock signals. .

According to another embodiment of the present invention, the capacitive sensor integrates the difference in the amount of charge between the first and second capacitors in the first capacitor, the second capacitor, and the first time interval. "Integral process", and the second time interval includes a control unit for preserving the integrated charge amount (hereinafter referred to as "conservation process").

The first and second capacitors may respectively receive a first clock signal and a second clock signal having a complementary relationship with the first clock signal. For example, the first time period may correspond to a first transition time of the first and second clock signals, and wherein the second time period is the first of the first and second clock signals. May correspond to two transition times.

1 and 2 are diagrams for describing a capacitive sensor according to an embodiment of the present invention.

3 to 8 are diagrams for describing an operation process of the capacitive sensor.

9 is a graph illustrating a simulation result of the capacitive sensor of FIG. 1.

10 and 11 are diagrams for describing a capacitive sensor according to another embodiment of the present invention.

Since descriptions of embodiments of the present invention are merely illustrated for structural to functional descriptions of the present invention, the scope of the present invention should not be construed as limited by the embodiments described in the present invention. That is, the embodiments of the present invention may be variously modified and may have various forms, and thus, it should be understood that the present invention includes equivalents capable of realizing the technical idea of the present invention.

On the other hand, the meaning of the terms described in the present invention will be understood as follows.

Terms such as “first” and “second” are used to distinguish one component from other components, and the scope of the present invention should not be limited by these terms. For example, the first component may be named a second component, and similarly, the second component may also be named a first component.

The term “and / or” should be understood to include all combinations that can be presented from one or more related items. For example, "first item, second item, and / or third item" means "at least one or more of the first item, second item, and third item", and means first, second, or third item. A combination of all items that can be presented from two or more of the first, second and third items as well as the third item.

When a component is referred to as being "connected" to another component, it should be understood that there may be other components in between, although it may be directly connected to the other component. On the other hand, when a component is said to be "directly connected" to another component, it should be understood that there is no other component in between. On the other hand, other expressions describing the relationship between the components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to", should be interpreted as well.

Singular expressions described herein are to be understood to include plural expressions unless the context clearly indicates otherwise, and the terms "comprise" or "having" include elements, features, numbers, steps, operations, and elements described. It is to be understood that the present invention is intended to designate that there is a part or a combination thereof, and does not exclude in advance the possibility of the presence or addition of one or more other features or numbers, steps, actions, components, parts or combinations thereof. .

Each step described in the present invention may occur out of the stated order unless the context clearly dictates the specific order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall be interpreted as having ideal or overly formal meanings unless expressly defined in this application. Can't be.

Referring to FIG. 1, the capacitive sensor 1000 includes a first capacitor (hereinafter referred to as a “reference capacitor”) 1100, a second capacitor (hereinafter referred to as a “sensing capacitor”) 1200, and a capacitance correction. It includes a control unit 1300 for. The controller 1300 may include an operational amplifier 1310, an integration capacitor 1320, and a switch 1330.

The reference capacitor 1100 may have a reference capacitance, and the sensing capacitor 1200 may vary in capacitance according to a change in sensing target.

The controller 130 integrates the difference in the amount of charge between the reference capacitor and the sensing capacitor in the first time interval (hereinafter referred to as an "integration process"), and preserves the charged amount in the second time interval (hereinafter, referred to as "preservation process"). "."

In FIG. 2, the capacitive sensor 1000 may be operated according to an operation clock signal 1400 indicating an operation timing, and the operation clock signal 1400 may be a reset clock signal RST for controlling the switch unit 1330. ), A first switch control signal PHI1 and a second switch control signal PHI2, and a first clock signal CLK and a second clock signal CLKB. The second clock signal CLKB has a complementary relationship with the first clock signal CLK.

3 and 4 illustrate a process of initializing the capacitive sensor.

3 and 4, the capacitive sensor 1000 initializes the integrating capacitor 1320 according to the operation clock signal 1500 for the reset timing.

The reference capacitor 1100 receives the second clock signal CLKB, which transitions from the first logic level (eg, logic low) to the second logic level (eg, logic high), and senses the sensing capacitor 1200. Receives a first clock signal CLK having a complementary relationship with the second clock signal CLKB.

The controller 1300 has a reset clock signal RST having a second logic level (eg, logic high), a first switch control signal PHI1, and a first logic level (eg, logic low). The second switch control signal PHI2 is received. As a result, the first input terminal (−) and the output terminal of the operational amplifier 1310 are connected to the first terminals of the reference capacitor 1100, the sensing capacitor 1200, and the integrating capacitor 1320, respectively, and the first terminal of the operational amplifier 1310. The second input terminal (+) is connected to the common voltage COM, the second terminal of the integration capacitor 1320 and the output terminal of the controller 1300. Here, the common voltage COM may mean a predetermined voltage. For example, the common voltage COM may correspond to the ground voltage GND or half of the power supply voltage VDD.

Accordingly, the controller 1300 may initialize the integral capacitor 1320 at the reset timing.

5 and 6 illustrate a process of integrating the difference in charge amount between the reference capacitor and the sensing capacitor in the capacitive sensor.

5 and 6, the capacitive sensor 1000 integrates charge to the integrating capacitor 1320 according to the operation clock signal 1600 for integration timing.

The reference capacitor 1100 receives the second clock signal CLKB that transitions from the second logic level (eg, logic high) to the first logic level (eg, logic low), and senses the sensing capacitor 1200. Receives a first clock signal CLK having a complementary relationship with the second clock signal CLKB.

The controller 1300 has a reset clock signal RST having a first logic level (eg, logic low), a first switch control signal PHI1, and a second logic level (eg, logic high). The second switch control signal PHI2 is received. As a result, the first input terminal (−) of the operational amplifier 1310 is connected to the first terminals of each of the reference capacitor 1100, the sensing capacitor 1200, and the integrating capacitor 1320, and the second input terminal of the operational amplifier 1310. (+) Is connected to the common voltage COM, and the output terminal of the operational amplifier 1310 is connected to the second terminal of the integration capacitor 1320 and the output terminal of the controller 1300.

Accordingly, the controller 1300 may integrate the difference in the amount of charge between the reference capacitor 1100 and the sensing capacitor 1200 into the integration capacitor 1320 at the integration timing.

7 and 8 illustrate a process of preserving the integrated charge amount in the capacitive sensor.

7 and 8, the capacitive sensor 1000 preserves the charge integrated in the integrating capacitor 1320 in accordance with the operating clock signal 1700 for the preservation timing.

The controller 1300 has a reset clock signal RST having a first logic level (eg, logic low), a second switch control signal PHI1, and a second logic level (eg, logic high). The first switch control signal PHI2 is received. As a result, the first input terminal (−) and the output terminal of the operational amplifier 1310 are connected to the first terminals of the reference capacitor 1100, the sensing capacitor 1200, and the integrating capacitor 1320, respectively, and the first terminal of the operational amplifier 1310. 2 The input terminal (+) is connected to the common voltage COM.

Therefore, the controller 1300 may preserve the amount of charge integrated in the integrating capacitor 1320 at the storage timing.

According to an embodiment, the capacitive sensor 1000 may repeat the integration process of FIG. 3 and the preservation process of FIG. 4. When the amount of charge integrated in the integrating capacitor 1320 is smaller than a predetermined reference, the capacitive sensor 1000 may not properly determine a signal (ie, voltage or current) output to the output terminal of the controller 1300. to be.

For example, the capacitive sensor 1000 may determine the signal output to the output terminal of the controller 1300 by repeating the integration process and the preservation process a predetermined number of times. For another example, the capacitive sensor 1000 may determine the signal output to the output terminal of the controller 1300 by repeating the integration process and the storage process for a predetermined time. As another example, the capacitive sensor 1000 obtains the number of repetitions by repeating the integration process and the preservation process until the predetermined threshold is exceeded, and outputs a signal output to the output terminal of the controller 1300 based on the repetition number. You can decide.

9 assumes that the charge amount difference corresponds to 5fF and the period of the operation clock signal 1400 corresponds to 2MHz.

In FIG. 9, the first graph 510 represents the reset clock signal RST, the second graph 520 represents the first and second switch clock signals PHI1 and PHI2, and the third graph 530. Denotes the first and second clock signals CLK and CLKB.

The fourth and

fifth graphs

540 and 550 may correspond to the reset clock signal RST, the first and second switch clock signals PHI1 and PHI2, and the first and second clock signals CLK and CLKB. The output signals of the integrating capacitor 1320 and the control unit 1300 are respectively shown. Fluctuation of the fourth graph 540 may occur because timings of the first and second clock signals CLK and CLKB do not coincide exactly.

Referring to FIG. 10, the capacitive sensor 6000 includes a reference capacitor 6100, a capacitor array 6200, a selector 6300, and a controller 6400. Since the capacitive sensor 6000 of FIG. 6 is substantially similar to the capacitive sensor 1000 of FIG. 1, the description will be mainly focused on a different part from FIG. 1.

The capacitor array 6200 includes at least one capacitor 6210 connected to each first end. The selector 6300 selects one of the at least one capacitor 6210 based on the capacitor address.

According to an embodiment, when the number of the at least one capacitor 6210 corresponds to 2 ⁿ , the selector 6300 may select one of 2 ⁿ capacitors by receiving a capacitor address having n bits. .

In FIG. 11, the capacitive sensor 6000 may be operated according to an operation clock signal 6500 indicating an operation timing, and the operation clock signal 6500 may be a reset clock signal RST for controlling the switch unit 6630. ), A first switch control signal PHI1 and a second switch control signal PHI2, a first clock signal CLK _k , a second clock signal CLK _{! K} , and a third clock signal CLKB. . The first clock signal CLK _k is input to a selected one of the at least one capacitor 6210, and the second clock signal CLK _{! K} is input to an unselected one of the at least one capacitor 6210. The three clock signals CLKB have a complementary relationship with the first clock signal CLK.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Embodiments of the present invention presented above may have an effect including the following advantages. However, all embodiments of the present invention should not be understood that the scope of the present invention is not limited by this, because it does not mean that all embodiments or specific embodiments of the present invention should include only the following advantages.

According to an embodiment of the present invention, the capacitance may be detected based on a difference in charge amount from a capacitor having a reference capacitance.

In addition, in one embodiment of the present invention it is possible to more accurately detect the capacitance by integrating the charge amount difference repeatedly. That is, one embodiment of the present invention can accurately detect the capacitance at low power using the charge conservation law.

Claims

Integrating the difference in charge amount between the first capacitor (the first capacitor has a reference capacitance) and the second capacitor (hereinafter referred to as an "integration process") in a first time interval, and the integrated charge amount in a second time interval Capacitive detection device comprising a control unit for storing (hereinafter referred to as "preservation process").
The method of claim 1, wherein the first and second capacitors

And a first clock signal and a second clock signal having a complementary relationship with the first clock signal, respectively.
3. The method of claim 2, wherein the first time period corresponds to a first transition time of the first and second clock signals, and the second time period corresponds to a second transition time of the first and second clock signals. Capacitive detection device, characterized in that.
The method of claim 1, wherein the control unit

And the integration process and the storage process are repeated for a predetermined time, a predetermined number of times or until the integrated charge is equal to or greater than a predetermined reference.
The method of claim 1, wherein the control unit

And an integrator capable of integrating the difference in charge amount.
The method of claim 5, wherein the integrator is

Integral capacitors; And

In the first time interval, an input terminal is connected to a first end of each of the first capacitor, the second capacitor and the integrating capacitor, and the output terminal comprises an operational amplifier connected to the second end of the integrating capacitor. Capacitive detection device.
The method of claim 6, wherein the output terminal

Capacitive detection device characterized in that connected to the first end in the second time interval.
The capacitive detection device of claim 1, wherein the capacitive detection device is used in a capacitive sensor.
A reference capacitor having a reference capacitance;

A capacitor array comprising at least one capacitor each having a first end connected thereto;

A selector for selecting one of the at least one capacitor based on a capacitor address; And

In the first time interval, the difference in charge amount between the selected one capacitor and the reference capacitor is integrated (hereinafter referred to as "integration process"), and in the second time interval, the integrated charge amount is preserved (hereinafter referred to as "preservation process"). Capacitive sensor comprising a control unit.
The method of claim 9, wherein the reference capacitor and the selected one capacitor

And a first clock signal and a second clock signal having a complementary relationship with the first clock signal.
11. The method of claim 10, wherein the first time period corresponds to a first transition time of the first and second clock signals, and the second time period corresponds to a second transition time of the first and second clock signals. Capacitive sensor, characterized in that.
The method of claim 9, wherein the control unit

And the integration process and the preservation process are repeated for a predetermined time, a predetermined number of times or until the integrated charge is equal to or greater than a predetermined reference.
The method of claim 9, wherein the control unit

And an integrator capable of integrating the difference in charge amount.
The method of claim 13, wherein the integrator is

Integral capacitors; And

In the first time interval, an input terminal is connected to the first end of each of the first capacitor, the second capacitor and the integration capacitor, the output terminal comprises an operational amplifier connected to the second end of the integration capacitor Capacitive sensor.
The method of claim 14, wherein the output terminal

And a capacitive sensor connected to the first end in the second time interval.
A first capacitor having a reference capacitance, and a second capacitor; And

In the first time interval, the difference in charge amount between the first and second capacitors is integrated (hereinafter referred to as "integration process"), and in the second time interval, the integrated charge amount is preserved (hereinafter referred to as "conservation process"). Capacitive sensor comprising a control unit.
The method of claim 16, wherein the first and second capacitors are

And a first clock signal and a second clock signal having a complementary relationship with the first clock signal.
18. The method of claim 17, wherein the first time period corresponds to a first transition time of the first and second clock signals, and the second time period corresponds to a second transition time of the first and second clock signals. Capacitive sensor, characterized in that.
The method of claim 16, wherein the control unit

And the integration process and the preservation process are repeated for a predetermined time, a predetermined number of times or until the integrated charge is greater than or equal to a predetermined reference.