WO2012036495A2 - Sampling circuit having enhanced noise feature and image sensor using same - Google Patents

Sampling circuit having enhanced noise feature and image sensor using same Download PDF

Info

Publication number
WO2012036495A2
WO2012036495A2 PCT/KR2011/006835 KR2011006835W WO2012036495A2 WO 2012036495 A2 WO2012036495 A2 WO 2012036495A2 KR 2011006835 W KR2011006835 W KR 2011006835W WO 2012036495 A2 WO2012036495 A2 WO 2012036495A2
Authority
WO
WIPO (PCT)
Prior art keywords
signal
voltage
output
switching signal
capacitor
Prior art date
Application number
PCT/KR2011/006835
Other languages
French (fr)
Korean (ko)
Other versions
WO2012036495A3 (en
Inventor
소명진
정진웅
Original Assignee
주식회사 룩센테크놀러지
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 룩센테크놀러지 filed Critical 주식회사 룩센테크놀러지
Publication of WO2012036495A2 publication Critical patent/WO2012036495A2/en
Publication of WO2012036495A3 publication Critical patent/WO2012036495A3/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to an image sensor, and more particularly, to a sampling circuit used in an image sensor.
  • the sampling circuit for an image sensor is a circuit that senses a signal (charge) generated in the photodiode of each pixel in the pixel array of the image sensor and converts and amplifies it into a voltage signal proportional to its magnitude.
  • a typical image sensor has a pixel array composed of a number of pixels arranged in rows and columns.
  • the amount of charge generated in the photodiode of the pixel is sequentially input to the amplifier through the data line for each row by the control gate.
  • the amplifier unit converts and amplifies the input charge amount into a voltage, and then samples and outputs a reset voltage and a signal voltage in a correlated double sampling circuit (hereinafter referred to as a CDS circuit).
  • the video signal is extracted as the difference between the reset voltage and the signal voltage.
  • the video signal output from the pixel is a very fine signal, which can be transformed and lost even with small noise. Therefore, the noise generated during the sampling process and the noise coming from outside should be reduced or eliminated as much as possible.
  • the CDS circuitry itself lowers the noise in the low frequency band, it must also reduce or eliminate high frequency noise above the desired signal band. Otherwise, there will be an error in the voltage being sampled, and when this voltage is converted to an image and displayed on the screen, it will adversely affect the image.
  • the problem to be solved by the present invention is a sampling circuit for an image sensor that can improve the noise appearing in the output voltage by eliminating or lowering the noise of the low frequency and high frequency band except the desired signal band while minimizing the circuit deformation for the CDS circuit To provide.
  • a first sample and hold circuit for sampling the voltage output signal converted and output from the amplifier by the amplifying unit according to the first switching signal to charge the first capacitor and output the reset voltage according to the output switching signal as a reset voltage;
  • a second sample and hold circuit for sampling the voltage output signal according to a second switching signal which is not activated simultaneously with the first switching signal, charging the second capacitor and outputting the voltage output signal as a signal voltage according to the output switching signal;
  • It may include a low pass resistance connected between the amplifier and the common node of the first capacitor and the second capacitor.
  • an image sensor includes an image sensor including a sensor unit, an amplifier, and a sampling circuit.
  • the sampling circuit The sampling circuit, ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇
  • a first sample that charges the first capacitor by sampling the voltage output signal converted and output from the photodiode in the sensor unit according to the first switching signal and outputs it as a reset voltage according to the output switching signal.
  • And hold circuit
  • a second sample and hold circuit for sampling the voltage output signal according to a second switching signal which is not activated simultaneously with the first switching signal, charging the second capacitor and outputting the voltage output signal as a signal voltage according to the output switching signal;
  • It may include a low pass resistance connected between the amplifier and the common node of the first capacitor and the second capacitor.
  • sampling circuit for an image sensor of the present invention accurate sampling can be achieved by improving the noise characteristics as compared to the conventional sampling circuit to reduce the effect of noise on the signal, and thus a clearer image can be obtained.
  • FIG. 1 is a circuit diagram illustrating a sampling circuit in an image sensor according to an embodiment of the present invention.
  • FIGS. 2 and 3 are circuit diagrams for conceptually describing an operation of a sampling circuit according to an embodiment of the present invention.
  • 4 and 5 are waveform diagrams comparing a control signal and a voltage signal waveform of a sampling circuit according to an embodiment of the present invention with a voltage signal waveform of the related art.
  • FIG. 1 is a circuit diagram illustrating a sampling circuit in an image sensor according to an embodiment of the present invention.
  • the flow of charge generated in the photodiode D Photo of the unit pixel sensor unit 11 into which light is incident passes through a control gate controlled by a gate control signal.
  • the amplifier 12 is input.
  • the amplifier 12 converts the amount of charge applied to a voltage output of an appropriate magnitude.
  • the voltage output output from the amplifier 12 passes through the low pass resistance R LPF and branches to the sampling circuit 13 including the first and second sample-and-hold circuits, respectively. .
  • Each of the first and second sample and hold circuits in the sampling circuit 13 includes first and second switches S1 and S2 and first and second switches switched by the first and second switching signals SH1 and SH2, respectively.
  • Second capacitors C SH1 and C SH2 are signals that do not overlap each other, that is, are not activated at the same time.
  • One end of the first and second capacitors C SH1 and C SH2 is connected to the first and second switches S1 and S2, respectively, and the other end is grounded.
  • the sampled and held reset voltages and signal voltages have high input impedances and low output impedances, respectively, through a unity-gain buffer that can forward the signal in the forward direction while suppressing signal propagation in the reverse direction. It is output from the two output terminals OUT1 and OUT2 through the first and second output switches S3 and S4.
  • the first and second output switches S3 and S4 are switched by a common output switching signal SOn.
  • the output reset voltage and signal voltage are digitally converted, and the difference between the reset voltage and the signal voltage is determined as an image value by incident light of the corresponding pixel.
  • FIGS. 2 and 3 are circuit diagrams for conceptually describing an operation of a sampling circuit according to an embodiment of the present invention.
  • the first sample and hold circuit operates to sample the reset voltage as a reference of the voltage level.
  • the first switching signal SH1 is activated and applied to the first switch S1, and the current output from the output terminal of the amplifier 12 is charged in the first capacitor C SH1 .
  • the voltage charged in the first capacitor C SH1 until the moment when the first switching signal SH1 is deactivated is reset by the current output from the amplifier 12 without the charge generated by the incident light from the pixel. to be.
  • the second switching signal SH2 is inactive.
  • the gate control signal is applied to sample the voltage level of the incident light incident on the pixel to conduct the control gate, the amount of charge generated in the pixel is applied to the amplifier 12, and the second sample and hold circuit is operated. .
  • the first switching signal SH1 is deactivated, and the second switching signal SH2 is activated and applied to the second switch S2.
  • the voltage output output in proportion to the amount of charge generated by the incident light at the output terminal of the amplifier 12 is charged in the second capacitor C SH2 via the low pass resistor R LPF .
  • the voltage charged in the second capacitor C SH2 until the second switching signal SH2 is deactivated is a signal voltage due to the current output from the amplifier 12 when charge flow is generated by incident light from the pixel. .
  • resistor R LPF and capacitor C SH1 and resistor R LPF and capacitor C SH2 form a first order low pass filter to limit the high frequency band.
  • the equation of the low pass filter is as follows.
  • ⁇ R LPF ⁇ C SH1,2 is the time constant.
  • the cutoff frequency of the filter is determined by the time constant.
  • the low pass resistor R LPF may be implemented as a gate-drain connected MOS transistor.
  • 4 and 5 are waveform diagrams comparing a control signal and a voltage signal waveform of a sampling circuit according to an embodiment of the present invention with a voltage signal waveform of the related art.
  • (a) shows a sampling period of the reset voltage and the signal voltage by the signals of the switching signals SH1 and SH2.
  • (b) and (c) show an operating voltage waveform including noise in a sampling circuit in a conventional image sensor and an operating voltage waveform including noise in a sampling circuit of the present invention, respectively. Since there are many switches in the sampling circuit, high frequency noise components may occur strongly at high speed switching.
  • FIG. 4C shows a reset voltage waveform and a signal voltage waveform when sampling an amplifier output including a noise component in the sampling circuit of the image sensor of the present invention. Also in (c), the output of the amplifier is mixed with high frequency noise components and input to the CDS circuit. However, due to the action of the low pass resistance R LPF and the sampling capacitors C SH1 and C SH2 added in the present invention, the high frequency noise component is removed or reduced.
  • FIG. 5 is an enlarged graph of a portion of the signal voltage sampled in the second switching signal SH2 section in FIG. 4 to more clearly understand that the high frequency noise component is reduced in the sampled signal voltage.
  • the conventional sampling circuit reacts sensitively to the error caused by the amplitude of the high frequency noise and outputs a wrong value affected by the high frequency noise component at the time of sampling as a signal voltage.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The sampling circuit for an image sensor of the present invention comprises: a first sample-and-hold circuit for converting at amplifying unit an electric charge generated from a photodiode, and sampling an outputted voltage output signal according to a first switching signal, charging same to a first capacitor, and outputting same as a reset voltage according to an output switching signal; a second sample-and-hold circuit for sampling the voltage output signal according to a second switching signal that is not activated at the same time as the first switching signal, charging same to a second capacitor, and outputting same as a signal voltage according to the output switching signal; and a low-pass resistor connected between common nodes of the amplifying unit, the first capacitor, and the second capacitor.

Description

개선된 잡음 특성을 가지는 샘플링 회로 및 이를 이용한 이미지 센서Sampling Circuit with Improved Noise Characteristics and Image Sensor Using the Same
본 발명은 이미지 센서에 관한 것으로, 더욱 상세하게는, 이미지 센서에 이용되는 샘플링 회로에 관한 것이다.The present invention relates to an image sensor, and more particularly, to a sampling circuit used in an image sensor.
이미지 센서용 샘플링 회로는 이미지 센서의 픽셀 어레이 내의 각 픽셀들의 포토다이오드에서 발생한 신호(전하)를 감지하여 그 크기에 비례하는 전압 신호로 변환 및 증폭하는 회로이다.The sampling circuit for an image sensor is a circuit that senses a signal (charge) generated in the photodiode of each pixel in the pixel array of the image sensor and converts and amplifies it into a voltage signal proportional to its magnitude.
일반적인 이미지 센서는 행과 열로 배치된 다수의 픽셀들로 구성된 픽셀 어레이를 갖는다. 픽셀의 포토다이오드에서 발생하는 전하량은, 제어 게이트에 의해 하나의 행마다 순차적으로, 데이터라인을 통해 증폭부로 입력된다. 증폭부는 입력된 전하량을 전압으로 변환 및 증폭하고, 이어서 상관 이중 샘플링 회로(Correlated Double Sampling, 이하 CDS 회로라 칭함)에서 리셋 전압과 신호 전압을 각각 샘플링하여 출력한다. 다음 단에서 리셋 전압과 신호 전압 사이의 차이로서 영상 신호를 추출한다.A typical image sensor has a pixel array composed of a number of pixels arranged in rows and columns. The amount of charge generated in the photodiode of the pixel is sequentially input to the amplifier through the data line for each row by the control gate. The amplifier unit converts and amplifies the input charge amount into a voltage, and then samples and outputs a reset voltage and a signal voltage in a correlated double sampling circuit (hereinafter referred to as a CDS circuit). In the next stage, the video signal is extracted as the difference between the reset voltage and the signal voltage.
*픽셀로부터 출력되는 영상 신호는 매우 미세한 신호로 작은 잡음에도 변형 및 손실될 수 있다. 따라서 샘플링 과정 중에 생성되는 잡음 및 외부로부터 유입되는 잡음을 최대한 낮추거나 또는 제거하여야 한다. CDS 회로가 그 자체로 저주파 대역의 잡음을 낮추는 기능을 하지만, 원하는 신호 대역 이상의 고주파 잡음도 낮추거나 제거하여야 한다. 그렇지 않으면 샘플링되는 전압에 오차가 생기고, 이 전압이 영상으로 변환되어 화면에 나타날 때, 영상에 나쁜 영향을 끼치게 된다.* The video signal output from the pixel is a very fine signal, which can be transformed and lost even with small noise. Therefore, the noise generated during the sampling process and the noise coming from outside should be reduced or eliminated as much as possible. Although the CDS circuitry itself lowers the noise in the low frequency band, it must also reduce or eliminate high frequency noise above the desired signal band. Otherwise, there will be an error in the voltage being sampled, and when this voltage is converted to an image and displayed on the screen, it will adversely affect the image.
본 발명이 해결하고자 하는 과제는 CDS 회로에 대해 회로의 변형을 최소화하면서 원하는 신호 대역을 제외한 저주파 및 고주파 대역의 잡음을 제거하거나 낮춤으로서 출력 전압에 나타나는 잡음을 개선시킬 수 있는 이미지 센서용 샘플링 회로를 제공하는 데에 있다.The problem to be solved by the present invention is a sampling circuit for an image sensor that can improve the noise appearing in the output voltage by eliminating or lowering the noise of the low frequency and high frequency band except the desired signal band while minimizing the circuit deformation for the CDS circuit To provide.
본 발명의 일 측면에 따른 샘플링 회로는,Sampling circuit according to an aspect of the present invention,
포토다이오드에서 발생된 전하량을 증폭부에서 변환 및 출력한 전압 출력 신호를 제1 스위칭 신호에 따라 샘플링하여 제1 커패시터에 충전하고 출력 스위칭 신호에 따라 리셋 전압으로서 출력하는 제1 샘플 앤드 홀드 회로; A first sample and hold circuit for sampling the voltage output signal converted and output from the amplifier by the amplifying unit according to the first switching signal to charge the first capacitor and output the reset voltage according to the output switching signal as a reset voltage;
상기 제1 스위칭 신호와 동시에 활성화되지 않는 제2 스위칭 신호에 따라 상기 전압 출력 신호를 샘플링하여 제2 커패시터에 충전하고 상기 출력 스위칭 신호에 따라 신호 전압으로서 출력하는 제2 샘플 앤드 홀드 회로; 및A second sample and hold circuit for sampling the voltage output signal according to a second switching signal which is not activated simultaneously with the first switching signal, charging the second capacitor and outputting the voltage output signal as a signal voltage according to the output switching signal; And
상기 증폭부와 상기 제1 커패시터 및 제2 커패시터의 공통 노드 사이에 연결된 저역 통과 저항을 포함할 수 있다.It may include a low pass resistance connected between the amplifier and the common node of the first capacitor and the second capacitor.
본 발명의 다른 측면에 따른 이미지 센서는 센서부, 증폭부 및 샘플링 회로를 포함하는 이미지 센서로서,According to another aspect of the present invention, an image sensor includes an image sensor including a sensor unit, an amplifier, and a sampling circuit.
상기 샘플링 회로는,The sampling circuit,
상기 센서부 내의 포토다이오드에서 발생된 전하량을 상기 증폭부에서 변환 및 출력한 전압 출력 신호를 제1 스위칭 신호에 따라 샘플링하여 제1 커패시터에 충전하고 출력 스위칭 신호에 따라 리셋 전압으로서 출력하는 제1 샘플 앤드 홀드 회로; A first sample that charges the first capacitor by sampling the voltage output signal converted and output from the photodiode in the sensor unit according to the first switching signal and outputs it as a reset voltage according to the output switching signal. And hold circuit;
상기 제1 스위칭 신호와 동시에 활성화되지 않는 제2 스위칭 신호에 따라 상기 전압 출력 신호를 샘플링하여 제2 커패시터에 충전하고 상기 출력 스위칭 신호에 따라 신호 전압으로서 출력하는 제2 샘플 앤드 홀드 회로; 및A second sample and hold circuit for sampling the voltage output signal according to a second switching signal which is not activated simultaneously with the first switching signal, charging the second capacitor and outputting the voltage output signal as a signal voltage according to the output switching signal; And
상기 증폭부와 상기 제1 커패시터 및 제2 커패시터의 공통 노드 사이에 연결된 저역 통과 저항을 포함할 수 있다.It may include a low pass resistance connected between the amplifier and the common node of the first capacitor and the second capacitor.
본 발명의 이미지 센서용 샘플링 회로에 따르면, 종래의 샘플링 회로에 비해 잡음 특성을 개선하여 잡음이 신호에 미치는 영향을 줄임으로써 정확한 샘플링이 이루어질 수 있고, 따라서 더욱 선명한 영상을 얻을 수 있다.According to the sampling circuit for an image sensor of the present invention, accurate sampling can be achieved by improving the noise characteristics as compared to the conventional sampling circuit to reduce the effect of noise on the signal, and thus a clearer image can be obtained.
도 1은 본 발명의 일 실시예에 따른 이미지 센서 중의 샘플링 회로를 예시한 회로도이다.1 is a circuit diagram illustrating a sampling circuit in an image sensor according to an embodiment of the present invention.
도 2 및 도 3은 본 발명의 일 실시예에 따른 샘플링 회로의 동작을 개념적으로 설명하기 위한 회로도이다.2 and 3 are circuit diagrams for conceptually describing an operation of a sampling circuit according to an embodiment of the present invention.
도 4 및 도 5는 본 발명의 일 실시예에 따른 샘플링 회로의 제어 신호와 전압 신호 파형을 종래 기술의 전압 신호 파형과 비교한 파형도이다.4 and 5 are waveform diagrams comparing a control signal and a voltage signal waveform of a sampling circuit according to an embodiment of the present invention with a voltage signal waveform of the related art.
본문에 개시되어 있는 본 발명의 실시예들에 대해서, 특정한 구조적 내지 기능적 설명들은 단지 본 발명의 실시예를 설명하기 위한 목적으로 예시된 것으로, 본 발명의 실시예들은 다양한 형태로 실시될 수 있으며 본문에 설명된 실시예들에 한정되는 것으로 해석되어서는 아니 된다. With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.
이하, 첨부한 도면들을 참조하여, 본 발명의 바람직한 실시예를 보다 상세하게 설명하고자 한다. 도면상의 동일한 구성요소에 대해서는 동일한 참조부호를 사용하고 동일한 구성요소에 대해서 중복된 설명은 생략한다. Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.
도 1은 본 발명의 일 실시예에 따른 이미지 센서 중의 샘플링 회로를 예시한 회로도이다.1 is a circuit diagram illustrating a sampling circuit in an image sensor according to an embodiment of the present invention.
도 1을 참조하면, 광이 입사된 단위 픽셀(Sensor Pixel) 센서부(11)의 포토다이오드(DPhoto)에서 발생한 전하의 흐름은 게이트 제어(Gate Control) 신호로 제어되는 제어 게이트를 통과하여, 증폭부(12)에 입력된다. 증폭부(12)는 인가되는 전하량을 적절한 크기의 전압 출력으로 변환한다.Referring to FIG. 1, the flow of charge generated in the photodiode D Photo of the unit pixel sensor unit 11 into which light is incident passes through a control gate controlled by a gate control signal. The amplifier 12 is input. The amplifier 12 converts the amount of charge applied to a voltage output of an appropriate magnitude.
증폭부(12)에서 출력된 전압 출력은 저역 통과 저항(RLPF)을 거친 후에 분기되어 각각 제1 및 제2 샘플 앤드 홀드(sample-and-hold) 회로를 포함한 샘플링 회로(13)에 인가된다.The voltage output output from the amplifier 12 passes through the low pass resistance R LPF and branches to the sampling circuit 13 including the first and second sample-and-hold circuits, respectively. .
샘플링 회로(13) 내의 각각의 제1 및 제2 샘플 앤드 홀드 회로는 제1 및 제2 스위칭 신호(SH1, SH2)에 의해 각각 스위칭되는 제1 및 제2 스위치(S1, S2)와 제1 및 제2 커패시터들(CSH1, CSH2)을 포함한다. 제1 및 제2 스위칭 신호(SH1, SH2)는 서로 중첩되지 않으며, 다시 말해 동시에 활성화되지 않는 신호들이다. 제1 및 제2 커패시터들(CSH1, CSH2)의 일단은 제1 및 제2 스위치(S1, S2)에 각각 연결되고, 타단은 접지된다.Each of the first and second sample and hold circuits in the sampling circuit 13 includes first and second switches S1 and S2 and first and second switches switched by the first and second switching signals SH1 and SH2, respectively. Second capacitors C SH1 and C SH2 . The first and second switching signals SH1 and SH2 are signals that do not overlap each other, that is, are not activated at the same time. One end of the first and second capacitors C SH1 and C SH2 is connected to the first and second switches S1 and S2, respectively, and the other end is grounded.
샘플링 및 홀딩된 리셋 전압 및 신호 전압은 높은 입력 임피던스와 낮은 출력 임피던스를 가지고 신호를 순방향으로는 원형 그대로 전달하면서 역방향으로는 신호 전달을 억제할 수 있는 단위 이득 버퍼(unity-gain buffer)를 통해 각각 제1 및 제2 출력 스위치들(S3, S4)을 통해 외부로 두 개의 출력 단자(OUT1, OUT2)에서 출력된다. 제1 및 제2 출력 스위치들(S3, S4)은 공통된 출력 스위칭 신호(SOn)에 의해 스위칭된다.The sampled and held reset voltages and signal voltages have high input impedances and low output impedances, respectively, through a unity-gain buffer that can forward the signal in the forward direction while suppressing signal propagation in the reverse direction. It is output from the two output terminals OUT1 and OUT2 through the first and second output switches S3 and S4. The first and second output switches S3 and S4 are switched by a common output switching signal SOn.
출력된 리셋 전압과 신호 전압은 디지털 변환되고, 리셋 전압과 신호 전압의 차이가 해당 픽셀의 입사광에 의한 영상 값으로서 결정된다.The output reset voltage and signal voltage are digitally converted, and the difference between the reset voltage and the signal voltage is determined as an image value by incident light of the corresponding pixel.
도 2 및 도 3은 본 발명의 일 실시예에 따른 샘플링 회로의 동작을 개념적으로 설명하기 위한 회로도이다.2 and 3 are circuit diagrams for conceptually describing an operation of a sampling circuit according to an embodiment of the present invention.
먼저, 픽셀에 입사된 광량을 측정하기 전에, 전압 레벨의 기준으로서 리셋 전압을 샘플링하기 위해 제1 샘플 앤드 홀드 회로가 동작한다. 제1 스위칭 신호(SH1)가 활성화되어 제1 스위치(S1)에 인가되며, 증폭부(12)의 출력 단자에서 출력되는 전류가 제1 커패시터(CSH1)에 충전된다. 제1 스위칭 신호(SH1)가 비활성화되는 순간까지 제1 커패시터(CSH1)에 충전된 전압은 픽셀로부터 입사광에 의해 발생한 전하가 인가되지 않은 상태에서 증폭부(12)에서 출력되는 전류에 의한 리셋 전압이다. 이 동안 제2 스위칭 신호(SH2)는 비활성화되어 있다.First, before measuring the amount of light incident on the pixel, the first sample and hold circuit operates to sample the reset voltage as a reference of the voltage level. The first switching signal SH1 is activated and applied to the first switch S1, and the current output from the output terminal of the amplifier 12 is charged in the first capacitor C SH1 . The voltage charged in the first capacitor C SH1 until the moment when the first switching signal SH1 is deactivated is reset by the current output from the amplifier 12 without the charge generated by the incident light from the pixel. to be. During this time, the second switching signal SH2 is inactive.
이어서, 픽셀에 입사된 입사광에 의한 전압 레벨을 샘플링하기 위해 게이트 제어 신호가 인가되어 제어 게이트가 도통되고, 픽셀에서 발생한 전하량이 증폭부(12)에 인가되며, 제2 샘플 앤드 홀드 회로가 동작한다. 제1 스위칭 신호(SH1)는 비활성화되고, 제2 스위칭 신호(SH2)가 활성화되어 제2 스위치(S2)에 인가된다. 증폭부(12)의 출력 단자에서 입사광에 의해 발생한 전하량에 비례하여 출력되는 전압 출력이 저역 통과 저항(RLPF)을 거쳐 제2 커패시터(CSH2)에 충전된다. 제2 스위칭 신호(SH2)가 비활성화될 때까지 제2 커패시터(CSH2)에 충전된 전압은 픽셀로부터 입사광에 의해 전하흐름이 발생하였을 때의 증폭부(12)에서 출력되는 전류에 의한 신호 전압이다.Subsequently, the gate control signal is applied to sample the voltage level of the incident light incident on the pixel to conduct the control gate, the amount of charge generated in the pixel is applied to the amplifier 12, and the second sample and hold circuit is operated. . The first switching signal SH1 is deactivated, and the second switching signal SH2 is activated and applied to the second switch S2. The voltage output output in proportion to the amount of charge generated by the incident light at the output terminal of the amplifier 12 is charged in the second capacitor C SH2 via the low pass resistor R LPF . The voltage charged in the second capacitor C SH2 until the second switching signal SH2 is deactivated is a signal voltage due to the current output from the amplifier 12 when charge flow is generated by incident light from the pixel. .
이어서, 출력 스위칭 신호(SOn)가 활성화되어 제1 및 제2 출력 스위치들(S3, S4)이 도통될 때에, 리셋 전압과 신호 전압은 단위 이득 버퍼를 거쳐 각각 출력 단자(OUT1, OUT2)에서 출력된다.Subsequently, when the output switching signal SOn is activated and the first and second output switches S3 and S4 are conducted, the reset voltage and the signal voltage are output at the output terminals OUT1 and OUT2 through the unit gain buffer, respectively. do.
이 과정에서, 저항 RLPF와 캐패시터 CSH1, 그리고 저항 RLPF와 캐패시터 CSH2는 1차 저역 통과 필터를 이루어 고주파 대역을 제한하게 된다. 저역 통과 필터의 수학식은 다음과 같다.In this process, resistor R LPF and capacitor C SH1 and resistor R LPF and capacitor C SH2 form a first order low pass filter to limit the high frequency band. The equation of the low pass filter is as follows.
수학식 1
Figure PCTKR2011006835-appb-M000001
 Equation 1
Figure PCTKR2011006835-appb-M000001
여기서, τ=RLPF × CSH1,2는 시정수이다. 수학식 1이 보여주듯이, 시정수에 의해 필터의 차단 주파수가 결정된다.Where τ = R LPF × C SH1,2 is the time constant. As Equation 1 shows, the cutoff frequency of the filter is determined by the time constant.
따라서, 따로 필터를 추가하지 않고도, 증폭부(12)의 출력 단자와 샘플 앤드 홀드 회로들 사이에 직렬로 적절한 저항 값을 가진 저주파 통과 저항(RLPF)을 연결하여 줌으로써 마치 저역 통과 필터를 추가한 효과를 얻을 수 있다.Therefore, by adding a low pass resistor R LPF having an appropriate resistance value in series between the output terminal of the amplifier 12 and the sample and hold circuits without adding a filter, a low pass filter is added. The effect can be obtained.
상기 저역 통과 저항(RLPF)은 게이트-드레인 연결 MOS 트랜지스터 등으로 구현될 수 있다.The low pass resistor R LPF may be implemented as a gate-drain connected MOS transistor.
도 4 및 도 5는 본 발명의 일 실시예에 따른 샘플링 회로의 제어 신호와 전압 신호 파형을 종래 기술의 전압 신호 파형과 비교한 파형도이다.4 and 5 are waveform diagrams comparing a control signal and a voltage signal waveform of a sampling circuit according to an embodiment of the present invention with a voltage signal waveform of the related art.
도 4를 참조하면, (a)는 스위칭 신호들 SH1과 SH2의 신호에 의한 리셋 전압과 신호 전압의 샘플링 구간을 나타낸다. (b)와 (c)는 종래의 이미지 센서 내 샘플링 회로에서 잡음이 포함된 동작 전압 파형과 본 발명의 샘플링 회로에서 잡음을 포함한 동작 전압 파형을 각각 나타낸다. 샘플링 회로 내에는 다수의 스위치들이 있기 때문에 고속 스위칭 시 고주파 잡음 성분이 강하게 발생할 수 있다.Referring to FIG. 4, (a) shows a sampling period of the reset voltage and the signal voltage by the signals of the switching signals SH1 and SH2. (b) and (c) show an operating voltage waveform including noise in a sampling circuit in a conventional image sensor and an operating voltage waveform including noise in a sampling circuit of the present invention, respectively. Since there are many switches in the sampling circuit, high frequency noise components may occur strongly at high speed switching.
도 4의 (b)에서 보는 바와 같이, 기존의 이미지 센서의 샘플링 회로에서는 증폭부의 출력에 잡음 성분이 섞인 전압이 그대로 CDS 회로의 입력되며, SH1 구간에 고주파 잡음 성분이 섞인 리셋 전압을 샘플링하고, SH2 구간에서도 마찬가지로 고주파 잡음 성분이 섞인 신호 전압을 샘플링한다. 이때, 고주파 잡음 성분이 섞인 전압을 CDS 회로에서 샘플링하게 되면, 고주파 잡음의 진폭에 의한 오차가 그대로 샘플링 커패시터에 저장되어 최종적인 영상 이미지에 영향을 미친다. As shown in (b) of FIG. 4, in the sampling circuit of the conventional image sensor, a voltage mixed with noise components is input to the output of the amplifier as it is, and a reset voltage mixed with high frequency noise components is sampled in the SH1 section. Similarly, in the SH2 section, a signal voltage mixed with high frequency noise components is sampled. At this time, when the voltage mixed with the high frequency noise component is sampled in the CDS circuit, the error due to the amplitude of the high frequency noise is stored in the sampling capacitor as it is and affects the final video image.
도 4의 (c)는 본 발명의 이미지 센서의 샘플링 회로에서 잡음 성분을 포함한 증폭부 출력을 샘플링할 경우의 리셋 전압 파형과 신호 전압 파형을 나타낸다. (c)에서도 증폭부의 출력에는 고주파 잡음 성분이 섞여 있고, CDS 회로에 입력된다. 하지만 본 발명에서 추가된 저주파 통과 저항(RLPF)과 샘플링 캐패시터(CSH1, CSH2)의 작용으로 인해, 고주파 잡음 성분은 제거되거나 또는 줄어든다.FIG. 4C shows a reset voltage waveform and a signal voltage waveform when sampling an amplifier output including a noise component in the sampling circuit of the image sensor of the present invention. Also in (c), the output of the amplifier is mixed with high frequency noise components and input to the CDS circuit. However, due to the action of the low pass resistance R LPF and the sampling capacitors C SH1 and C SH2 added in the present invention, the high frequency noise component is removed or reduced.
도 5는 샘플링된 신호 전압에서 고주파 잡음 성분이 줄어든 것을 좀더 명확하게 알 수 있도록 도 4에서 제2 스위칭 신호(SH2) 구간의 샘플링되는 신호 전압 부분을 확대한 그래프이다. FIG. 5 is an enlarged graph of a portion of the signal voltage sampled in the second switching signal SH2 section in FIG. 4 to more clearly understand that the high frequency noise component is reduced in the sampled signal voltage.
도 5의 (b)에 보인 바와 같이, 기존의 샘플링 회로에서는 고주파 잡음의 진폭에 의한 오차에도 민감하게 반응하다가 샘플링되는 시점에서 고주파 잡음 성분에 영향받은 잘못된 값을 신호 전압으로서 출력한다.As shown in (b) of FIG. 5, the conventional sampling circuit reacts sensitively to the error caused by the amplitude of the high frequency noise and outputs a wrong value affected by the high frequency noise component at the time of sampling as a signal voltage.
반면에, 도 5의 (c)에 보인 바와 같이, 본 발명의 샘플링 회로에서는 고주파 잡음이 훨씬 줄어들어 샘플링되는 시점에서 고주파 잡음 성분의 영향이 줄어들고 좀더 정확한 전압 레벨을 신호 전압으로 출력하는 것을 알 수 있다. On the other hand, as shown in (c) of Figure 5, in the sampling circuit of the present invention it can be seen that the high frequency noise is much reduced, the effect of the high frequency noise component is reduced at the time of sampling and outputs a more accurate voltage level as the signal voltage. .
이상과 같이 본 발명은 비록 한정된 실시예와 도면에 의해 설명되었으나, 본 발명이 상기의 실시예에 한정되는 것은 아니며, 이는 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면 이러한 기재로부터 다양한 수정 및 변형이 가능하다. 따라서, 본 발명의 사상은 아래에 기재된 특허청구범위에 의해서만 파악되어야 하고, 이와 균등하거나 또는 등가적인 변형 모두는 본 발명 사상의 범주에 속한다 할 것이다.As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited to the above-described embodiments, which can be variously modified and modified by those skilled in the art to which the present invention pertains. Modifications are possible. Accordingly, the spirit of the invention should be understood only by the claims set forth below, and all equivalent or equivalent modifications will fall within the scope of the invention.

Claims (2)

  1. 포토다이오드에서 발생된 전하량을 증폭부에서 변환 및 출력한 전압 출력 신호를 제1 스위칭 신호에 따라 샘플링하여 제1 커패시터에 충전하고 출력 스위칭 신호에 따라 리셋 전압으로서 출력하는 제1 샘플 앤드 홀드 회로; A first sample and hold circuit for sampling the voltage output signal converted and output from the amplifier by the amplifying unit according to the first switching signal to charge the first capacitor and output the reset voltage according to the output switching signal as a reset voltage;
    상기 제1 스위칭 신호와 동시에 활성화되지 않는 제2 스위칭 신호에 따라 상기 전압 출력 신호를 샘플링하여 제2 커패시터에 충전하고 상기 출력 스위칭 신호에 따라 신호 전압으로서 출력하는 제2 샘플 앤드 홀드 회로; 및A second sample and hold circuit for sampling the voltage output signal according to a second switching signal which is not activated simultaneously with the first switching signal, charging the second capacitor and outputting the voltage output signal as a signal voltage according to the output switching signal; And
    상기 증폭부와 상기 제1 커패시터 및 제2 커패시터의 공통 노드 사이에 연결된 저역 통과 저항을 포함하는 샘플링 회로.And a low pass resistor coupled between the amplifier and a common node of the first capacitor and the second capacitor.
  2. 센서부, 증폭부 및 샘플링 회로를 포함하는 이미지 센서로서,An image sensor comprising a sensor unit, an amplifier unit, and a sampling circuit,
    상기 샘플링 회로는,The sampling circuit,
    상기 센서부 내의 포토다이오드에서 발생된 전하량을 상기 증폭부에서 변환 및 출력한 전압 출력 신호를 제1 스위칭 신호에 따라 샘플링하여 제1 커패시터에 충전하고 출력 스위칭 신호에 따라 리셋 전압으로서 출력하는 제1 샘플 앤드 홀드 회로; A first sample that charges the first capacitor by sampling the voltage output signal converted and output from the photodiode in the sensor unit according to the first switching signal and outputs it as a reset voltage according to the output switching signal. And hold circuit;
    상기 제1 스위칭 신호와 동시에 활성화되지 않는 제2 스위칭 신호에 따라 상기 전압 출력 신호를 샘플링하여 제2 커패시터에 충전하고 상기 출력 스위칭 신호에 따라 신호 전압으로서 출력하는 제2 샘플 앤드 홀드 회로; 및A second sample and hold circuit for sampling the voltage output signal according to a second switching signal which is not activated simultaneously with the first switching signal, charging the second capacitor and outputting the voltage output signal as a signal voltage according to the output switching signal; And
    상기 증폭부와 상기 제1 커패시터 및 제2 커패시터의 공통 노드 사이에 연결된 저역 통과 저항을 포함하는 것을 특징으로 하는 이미지 센서.And a low pass resistor coupled between the amplifier and a common node of the first and second capacitors.
PCT/KR2011/006835 2010-09-17 2011-09-16 Sampling circuit having enhanced noise feature and image sensor using same WO2012036495A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020100091738A KR101019159B1 (en) 2010-09-17 2010-09-17 Signal sampling circuit having improved noise characteristics and image sensor using the same
KR10-2010-0091738 2010-09-17

Publications (2)

Publication Number Publication Date
WO2012036495A2 true WO2012036495A2 (en) 2012-03-22
WO2012036495A3 WO2012036495A3 (en) 2012-05-31

Family

ID=43938358

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2011/006835 WO2012036495A2 (en) 2010-09-17 2011-09-16 Sampling circuit having enhanced noise feature and image sensor using same

Country Status (2)

Country Link
KR (1) KR101019159B1 (en)
WO (1) WO2012036495A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2698990A1 (en) * 2012-08-14 2014-02-19 Luxen Technologies, Inc. Digital image processing readout integrated circuit (roic) having multiple sampling circuits
CN113395466A (en) * 2020-03-12 2021-09-14 格科微电子（上海）有限公司 Method for reducing multi-column crosstalk of image sensor

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101948057B1 (en) 2012-04-13 2019-02-14 삼성전자주식회사 Correlated double sampling circuit and image sensor including the same
KR20140024707A (en) 2012-08-21 2014-03-03 삼성전자주식회사 Image sensor and electronic device including the same
KR101734006B1 (en) 2015-05-19 2017-05-25 주식회사 센소니아 Data readout circuit with low power consumption

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990005437A (en) * 1997-06-30 1999-01-25 김영환 Dual Sampling Analog Lowpass Filter
KR100644129B1 (en) * 2005-08-22 2006-11-10 (주) 픽셀플러스 Reset signal compensator circuit and cmos image sensor with the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990005437A (en) * 1997-06-30 1999-01-25 김영환 Dual Sampling Analog Lowpass Filter
KR100644129B1 (en) * 2005-08-22 2006-11-10 (주) 픽셀플러스 Reset signal compensator circuit and cmos image sensor with the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2698990A1 (en) * 2012-08-14 2014-02-19 Luxen Technologies, Inc. Digital image processing readout integrated circuit (roic) having multiple sampling circuits
US9137470B2 (en) 2012-08-14 2015-09-15 Luxen Technologies, Inc. Digital image processing readout integrated circuit (ROIC) having multiple sampling circuits
CN113395466A (en) * 2020-03-12 2021-09-14 格科微电子（上海）有限公司 Method for reducing multi-column crosstalk of image sensor
CN113395466B (en) * 2020-03-12 2023-08-11 格科微电子（上海）有限公司 Method for reducing multi-column crosstalk of image sensor

Also Published As

Publication number Publication date
KR101019159B1 (en) 2011-03-03
WO2012036495A3 (en) 2012-05-31

Similar Documents

Publication Publication Date Title
JP5893573B2 (en) Solid-state imaging device
US10348986B2 (en) Solid-state image sensor, electronic apparatus, and control method of solid-state image sensor
JP4677310B2 (en) Image sensor detection circuit
US10419702B2 (en) Imaging apparatus, imaging system, and method of driving an imaging system
US7242428B2 (en) Image sensor using multiple array readout lines
WO2012036495A2 (en) Sampling circuit having enhanced noise feature and image sensor using same
US20030010896A1 (en) Image sensing apparatus capable of outputting image by converting resolution by adding and reading out a plurality of pixels, its control method, and image sensing system
US7068312B2 (en) Solid-state image-sensing device
JP4532676B2 (en) Pixel signal gain amplification circuit
US20090278575A1 (en) Charge recycling amplifier for a high dynamic range cmos imager
US6031399A (en) Selectively configurable analog signal sampler
US20110096186A1 (en) Fully-differential amplifier, photoelectric conversion apparatus including fully-differential amplifier, and image-pickup system
WO2021035605A1 (en) Dark current correlated double sampler, image sensor, and dark current compensation method
US8094218B2 (en) Image sensor circuit having differential signal path, differential analog-to-digital converter and differential signal offsetting means
EP3598739B1 (en) Image sensing circuit and control method thereof
KR101648715B1 (en) Sample and hold circuit and fingerprint detecting apparatus comprising the same
WO2016140382A1 (en) Noise reduction unit included in sensor array of multi aperture camera, and operation method therefor
US7956917B2 (en) Sensor apparatus
KR20230107789A (en) Electronic Integrating Circuits with Offset and Collect Charge Reduction Circuits and Related Methods
JP2012015919A (en) Solid-state image sensing device and imaging apparatus using the same
KR20110079016A (en) Cmos image sensor
JP2003169257A (en) Solid-state image pickup device and imaging unit provided with the same
JPH04126445A (en) Image sensor
JP2001285718A (en) Solid-state image pickup device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11825455

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11825455

Country of ref document: EP

Kind code of ref document: A2