WO2009122405A2 - Novel ultra low power ofdm receiver components - Google Patents

Abstract

The theme of our patent is an ultra low power components for Orthogonal Frequency Division Multiplexing (OFDM) based receiver. A new and innovationist OFDM receiver components ("our OFDM receiver components"), based on discrete time analog signal processing, are described in this patent application. OFDM receiver circuit is usually related to a communication field, where it is used to receive and decode a transmitted data. OFDM receiver circuit gets at its input OFDM modulated signals, and performs all necessary tasks, in order to decode the received data. OFDM signal comprised of multiple orthogonal carrier (103a- 105a), in which each one carries different data symbol. The summation of all carrier symbols comprises the data. To perform the receiving operation, an OFDM receiver must first perform detection, synchronization, parameter and channel estimation, then, a Fast Fourier Transform (FFT) is applied, and then, equalization is performed, and the last stage, is the de-interleaving and the error correction. All tasks above require complicated computational operations, such as additions, multiplications. Therefore, if implemented in a digital way, as it is with the current known technology, a significant high power is consumed by the receiver. Our OFDM receiver components are built and designed to work with discrete time analog signals, based on extremely low power additions, multiplications operations, and therefore achieves significant power reduction, compared to its digital counter implementation.

Description

Novel ultra low power OFDM receiver Components.

We will present in this application our ultra low power OFDM receiver components. Our OFDM receiver components are base on current mode signal processing, working in the sub-threshold region of transistor operation.

Technical field of the invention - general

Our OFDM receiver circuit components, relates to the field of communication using discrete time analog signal processing, where discrete analog signals are used instead of their counter digital samples.

Our OFDM receiver circuit can be used in receiver implementation and applications such as: WiMax, Mobile TV (DVBH- TDMB), Ultra Wide Band receiver (ECMA-368,

802.15.3a, 802.15.3c { "ECMA" - European Computer Manufacturers Association. }), etc.

Background Art

Today's most known communication standards use the OFDM modulation scheme, to send and receive information over the communication channel. OFDM method is well understood and suitable for many applications, wired and wireless. ADSL for example, uses an OFDM to transmit internet information to the end user. OFDM, is also used for many Mobile TV standards, such as DVBH, T-DMB. Also, OFDM is penetrating to almost all standards for wireless application, such as WiMax, WiFi , home network, Utra Wide Band, etc.

In Figure Ia, OFDM signal (100a), for one OFDM symbol, is described. It is comprised of two parts - the cyclic prefix (101a), and the OFDM cycles (102a). As shown, the OFDM signal, is a summation of many sinusoidal waveforms, each one carries, in this example, one bit. The first sinusoidal carries +1(103a). The second carries -1 when it is 180 degrees inverted (104a). The third, also carries +l(105a). In figure Ib, Another method for OFDM signal is described, in which the OFDM symbol, is comprised of zero prefix (101b) and OFDM cycles (102b). As before the OFDM signal of figure Ib, carries the same information bits.

In figure 2, general DSP system is depicted, in which the analog signal source (200- 201), is first filtered by anti-aliasing filter (202), the signal is sampled and hold (203), and passed to the Analog to Digital converter (ADC) (204). The ADC quantize the analog signal S(n) (204), and passes the stream of digitized samples Sq(n) (206) into the digital processing unit (207), which could be implemented by Instruction Set Architecture (ISA)

DSP, or, by Application Specific Integrated Circuit (ASIC) DSP.

The ISA DSP gives flexibility but charges high power, on the other hand, ASIC DSP gives lower power but no flexibility.

In figure 3, DSP implementation of a receiver is shown. The first stage is a tuner (301) connected to antenna (300). The tuner translates the high frequency signal to some base band signal, and performs some pre-processing filtering.

The complex signal (I&Q)(302) is then, "sampled & hold" (S/H) (303-304). The output from S/H is digitized by ADC's (306-307) and sent to the base band receiver (308), for decoding the received signal data.

The base band receiver needs to perform many computational operations, such as detection, synchronization, parameter estimation etc, to reliably decode the received data.

In figure 4, an OFDM receiver, based on DSP method, is described. Similar to figure

3, the first stages in the chain are, the antenna (400), tuner (401) for converting the Radio

Frequency (RF) signal to base band, S/H units (402-403), and ADC's (404-405). The base band processing is described in more details, to show the complexity involved with

OFDM reception (see US 7075949 Bl).

The first block, OFDM symbol synchronization (410), is responsible of detecting the

OFDM packet and finding the starting point, in time, of the OFDM symbol at the end of the cyclic/zero prefix (101a, 101b). The synch block sends a mark to a memory buffer

(41 1), which stores the OFDM symbol (100a, 100b), the OFDM symbol is then processed by the Fast Fourier Transform (FFT) (413), which extracts the amplitudes values from the different OFDM carriers. The FFT is a complex operation that involves many additions/multiplications memory and control operations.

Carrier frequency correction (407, 409) and timing correction (406,408) are operated in parallel which involves too many mathematical operations per second, and hence power consumption is increased.

The next block in the receive chain, is the equalizer (EQU)(420), which responsible on the amplitude and phase correction, of the OFDM carriers. Equalization, as well, requires many multiplications/addition per second. Equalizer output is further corrected for residual phase (422), if required (depended on the standard).

The OFDM corrected phase carriers, are then processed by the de-mapping (423), for converting the carriers symbol data into bits, and also processed by de-interleaving (424) and error correction (425).

In high rate communication, the above requires too many mathematical operations per second and hence power consumption is increased.

In parallel to the receive chain, which process the samples sequentially, parameter estimation blocks perform, carrier frequency/sampling timing (412), phase, channel and noise estimation (415-417), and equalization coefficients calculation (416-418) .

To implement the above using the current known technology large area and high power is required.

It is therefore, the purpose of this invention to describe a new and extremely low power consumption OFDM receiver circuit Components.

All the ahead circuits are novel components to be implemented in the ULP receiver.

Detailed description of our Invention

Important comment: the length of this application forced us to formulate it, under six subchapters, based on the six components circuits which are the building breaks of this international application.

1. General.

2. Novel Ultra low Power Viterbi Decoder.

3. Ultra Low Power Fully Differential current mode Viterbi decoder sub-system.

4. Complete Current Mode Micro Power Multiplier with Floating gate offset Cancellation.

5. Complete Current Mode Micro Power Divider Circuit with Floating gate offset Cancellation

6. Ultra Low power (ULP) Carrier Frequency Correction for OFDM Receivers.

7. Ultra Low Power (ULP) timing synchronization method for wired and wireless Receivers.

General In this section, we will cover the principals of our new OFDM circuit.

Our OFDM receiver circuit works in the discrete time analog signal processing, in which, rather than working on digitized samples, work is done on analog samples.

By doing that:

• The need for ADC is eliminated.

• The amount of gates is reduced and hence power.

• The signal voltage swing is reduced by 10 and therefore the power by 100. Figure 5, shows a possible implementation of the invention. The identical parts to the prior art are the antenna (500), tuner (501) and the S/H units (502,503).

However, we see a huge difference compared to the prior art shown in figure 4.

Our OFDM receiver, processes the analog samples at the output of the S/H units in an analog way, by representing the input samples at the output of the S/H units (502-503), using some physical parameter, such as current or voltage.

All processing blocks, are implemented using analog circuit implementation of the required function.

Our signal chain, shown in figure 5, is innovationist. And in relation to the chain, shown in figure 4, these changes are demonstrated :

Work is done on analog samples - no ADC's are required.

Sampling timing correction, in figure 4, is done by using digital re-sampling, here it is done by generating sampling clock (504) which is connected to the S/H units.

Other signal chain elements are, in terms of functionally, the same. The input buffer that collects the samples, which represents, at least, one OFDM symbol, is stored in a dual buffer analog memory (509), while one buffer is connected to the input samples stream, the other feeds the Fast Fourier Transform (FFT) (510), which is also implemented using the discrete time analog signal processing - our patent application No. 187073. FFT output is then passed to the EQU (519), phase correction (520) and de-mapping (521). All are implemented using analog multipliers and addition circuits in our patent application No. 187075.

The de-mapping (521) output, is then passed to the de-interleaver (522) and to the Forward Error Correction block(FEC) (523). The de-interlever is implemented using analog memory in case of soft outputs, at the de-mapper (521), or, digitally for hard decision case. In parallel to the above signal chain, there are some blocks responsible of parameter estimation and EQU coefficients calculation.

Usually the parameter estimation process, is based on the FFT output pilot data (511), but in some standards (DVBH, T-DMB), some of the parameters are estimated using the time domain signal (51 Ia).

We'll now cover the method of implementing each of the algorithms shown in this figure.

This circuit provides the values of cos{ φ(i) } and sin{ φ(i) } for the multipliers (507).

In this invention we describe our modules (502, 503, 507, 508).

The Timing/Carrier Estimation (512), is the block responsible of estimating "Δω * T" and supplies it to the carrier NCO (508).

The algorithm which continuously evaluates Δω is called "Phase Locked Loop" (PLL) and it is implemented in the Timing/Carrier estimation module (512).

In figure 6, we see a functional block diagram of eight points FFT algorithm (we used eight points for simplicity). The input (601) is fed into three stages of butterflies (603-

605), as the FFT compute the frequency content of the input (601), and the FFT output is presented (606).

As shown, one butterfly (602) includes one complex multiplication and two additions.

Figure 7, shows an example of implementation extremely low power multiplier and addition circuits, in which currents are used to represent the samples values.

The multiplier shown in this figure is implemented using Floating Gate Metal Oxide

Semi-conductor (FG-MOS) for offset compensation, and hence, higher multiplier accuracy.

This multiplier is fully described in our "Current Mode Micro Power Multiplier with floating gate offset cancellation" - Our patent application No. 187075 .

The summation circuit, in cases of currents, is simply implemented using current junction as shown in figure 7d, where negative currents are connected to the negative node of differential current representation, and positive currents to the positive node.

Figure 8, describes our OFDM receiver, where all blocks responsible for parameter estimation - such as sampling timing deviation, carrier offset deviation, channel estimation, and residual phase estimation - operate using discrete time analog signal processing, in one parameter block estimation (813).

In figure 9, we see our OFDM receiver circuit, in which the parameter estimation block (913) is implemented using the traditional signal processing method. The input is taken form the time domain samples (910) or frequency domain samples (912). "Novel ultra low power Viterbi Decoder circuit" :

Today's known communication standards receivers use a Viterbi encoder/decoder in the signal chain for the purpose of error detection and error correction. The Viterbi decoder gets data with overhead, when some of the data is corrupted by additive noise, and can not be retrieved by using "hard decision". The Viterbi decoder then, compute the most likelihood sequence, and can either detect and/or correct the errors.

In order to present our innovationist Viterbi decoder, we will cover the Viterbi encoding and decoding process. We continue with practical implementation of Viterbi decoder and demonstrate the complexity of it.

Figure 10 describes an example of rate ¹A Viterbi encoder. An input stream (1000), x₀, x I .X_N-_I, N input bits, is entered into the Viterbi encoder, which is built of two delay elements (1001,1002), XOR gate (1003) and an output switch (1004).

The Viterbi encoder, in this example, generates two output bits for every input bit

(1000,1005). The generated bits are then transmitted.

Having a redundancy at the receiver input will help the receiver to correct errors using the Viterbi decoder.

Figure 11 shows a state machine description of the Viterbi encoder circuit shown in figure 1, in this example, the Viterbi encoder has four states (200-203), this is due to the two delay elements (1001,1002) - which define 2²=4 states. The states are marked as

"00" (200), "01" (1101), "10" (1102) & "11" (1103).

Figure^" 12, describes the channel model, which includes the input stream of N bits

(1200) and Viterbi encoder (1201). The mapper (1203) translates binary digits to analog numbers (+/-l).The channel is represented by additive noise source (1205). The Viterbi decoder represents the error correction at the receiver.

Figure 13 describes the trellis of the Viterbi encoder.

Figure 14 describes the basic, two inputs of the ACS operation. Two branches are coming in (1403a, 1403b, 1404a, 1404b) into one state (1405).

Figure 15 describes a Viterbi decoder block diagram, built of four basic units: • Branch Metric Unit (BMU) (1501), responsible of computing the branch metrics at every stage, in case of basic rate of m/n there will be 2" branch metrics to compute.

In the above demonstration n=2 (two output bits), there are four branch metrics to compute, used for all state metric computation.

• State Metric Unit (SMU) (1502), which is responsible of computation the state metrics. This is an iterative computation based on previous state metrics, new branch metrics and ACS operation.

• Memory unit (1503), to hold the surviving paths data.

• Path Metric Unit (PMU) (1504) keeps track on the surviving paths, allowing re- decoding of the best path.

Figure 16 describes our "voltage to current converter" (V2I).

Our V2I is built of couple of "Operational Trans Conductance Amplifiers" (OTA) (1601,

1602), driving an N-channel transistors (1603, 1604). As a result, the voltage across resistor (1607) is equal to the differential voltage at the inputs (VINN, VINP).

Figure 17 represents our I2V embodiment, which include Sample and Hold (S&H).

Switches (1702, 1703, 1708 and 1709) are designed to support the function of S&H.

During sampling, when S&H input is "High", the differential current ΔI is flowing through the resistors (1709, 1710). Capacitors (1712, 1713), are limiting the signal bandwidth.

Figure 18 represents our "enhanced two couple amplifiers I2V" embodiment, which include Sample and Hold (S&H).

The 12 V function is supported by the two amplifiers (1801, 1802).The S&H function is supported by amplifiers (1803 1804).

Resistors (1805,1806), together with amplifiers (1801 and 1802), support the continues time I2V converter function.

Additional embodiment to the cells in figures 8, 9:

In figure 8 there is one couple of differential, single ended amplifiers. And in figure 9 there are two couples like this.

Wherever a couple of single ended amplifiers is implemented, where the two amplifiers input the same reference voltage, they can be replaced by a fully differential amplifier, where the reference voltage is tied to a "Common Mode Reference Input", instead to one of the differential inputs in the single ended amplifiers. Figure 19 describes our comparator in the "Add Compare Select" (ACS) Viterbi cell.

The comparator is based on a simple switched comparator.

When SNCMP is in "Low", current sources transistors (1901, 1902) are not conducting current, and the comparator is floating. Transistors (1903, 1904) are conducting current.

Hence, the input voltages (VINP, VINN) are applied on both ends of the comparator (VP,

VN).

When SNCMP turns "High", the comparator is disconnected from the inputs, where transistors (1903, 1904) are not conducting, and the current sources (1901, 1902) are activated.

The SRFF latch (1005), keeps the state of the comparator for the time where SMCMP is

"low".

Figure 20 shows how all the cells in figures 16 - 19 are connected together in our innovationist Analog "Add Compare Select" (ACS) cell.

The operation of our ACS cell, is based on two phase. The first is the "even" phase and the second is the "odd" phase. Each phase can not make its calculations, without using the data stored in the previous phase. The above is an iterative method to calculate our

Viterbi path metrics. Each "even" or "odd" phase is divided by two sub-cycles. The first, selects the new state metric and the second store it, to be used in the successive phase.

There are five V2I sub-cells, where four of them (2001, 2002, 2003, 2004), are tied to early State Metrics outputs (SM [I], SM [J]), and to the two inputs y [0] and y [I].

The connectivity is through a switching mechanism (2005, 2006, 2007, and 2008).

The cells supporting y[0] and y[l] (2001, 2002), have X2 control (yOX2, ylX2), which enables the V2I to double its output ΔI.

The fifth V2I (2010), is tied to the average or maximum, state metric calculator. This cell is designed to prevent the voltages over the entire set of state metric outputs (SM [I], SM

[J]), to integrate above a certain value.

AU state metric outputs are integrated during packet transfer. Hence, since we are just comparing the SM values relative to each other, there is no need to let the average, being integrated. Therefore, by removing the average or maximum level from all SM's, we limit the dynamic range required, and keeping the relative difference between them at maximum dynamic range possible.

Every few cycles, the average or maximum value is subtracted by activating this mechanism. During "next SM calculation", and branch metric calculation, activation is not needed. The input to SM average (2010) is multiplied by -1 (= remove average), or by

0 (= do not remove average), with the switches (2019). The SM average operation, is detailed in figure 13, shows how the "AVG_SUBTRACT" control signal (1309) controls the average subtraction.

The four current sources (2015-2018) roll is to compensate the sum of currents from the

V2I sub-cells (as shown in figures 8, 9).

Two I2V sub-cells (2011, 2012) are placed in our ACS cell. One I2V (2011), is calculating and sampling in odd phases, while the second (2012), is operating in even cycles and keeps the last value of state metric (SM [K]) for its calculations, and visa versa in a "ping-pong" manner.

Selector (2014) selects the output tied to SM [K] node, while the other selector (2013) selects the output which serves for branch metric calculation.

The signal controlling the "even or odd" for the two selectors is "EVENNODD", described in figure 22.

This selected "EVENODD" output serves the comparator (2024), to decide, it its output

(BM[k] select), which branch is selected during the branch metric calculation, where the timing is described in (2201, 2206). The comparator is operational when the control input

SNCMP is going from "Low" to "High" (2201, 2202). The general operation of the comparator is described in figure 9.

After branch metric is selected, the comparator result is in "hold" for the next cycle

(2203), and the inputs to the four V2I circuits are controlled by the comparators output, to calculate the next SM [K] (2206). In the next sub-cycles (of the "odd" phase), the cell holds SM [K] and the "odd" 12V )I l I l) circuit, is operational, getting the stored SM [K] as input.

COMPOUT (2208) is the output from the comparator. This output is also used by the digital control (described in figure 21), to decide whether the branch selection was upper

"1", or lower "0".

Figure 21 describes the connections between our analog ACS cell (shown in figure 11 and 1201 here) activated by our digital control block (2102).

Figure 22 Shows the timing operation of our ACS cell described in figures 20, 21. Figure 23a describes the implementation of our Ultra Low Power Flip Flop (ULPFF). The circuit is comprised of two parts. One is the clock circuit built of XOR gate (14a22), which compares the input data D

(HaOO), with the ULPFF, Q output (23a01). The XOR (23a01) disables the clock input, using transistors (23a05-23a06), when the input data D (23a00) is equal to the ULPFF Q

(23a01).

Figure 23b describes the operation of a bit cell memory, which is based on our ULPFF, used in the tracking array, which is described in figure 24.

The cell in this figure supports the "Register exchange" algorithm.

Figure 23c describes the Viterbi tracking array storage cell, for trace back.

This cell is built of ULPFF (23cθl) and one select block (23cO2).

Figure 24a describes our innovationist PMU tracking array, for the register exchange algorithm.

The Flip Flops (FF's) in our PMU described in figure 23b. Exceptional are the FF in the

Walking One control register (W/O) (24a01). This register is comprised of our ULPFF, described in figure 23a.

Figure 24b describes the tracking array, for the "trace back" algorithm. This tracking array is built of the flip flop that was described in figure 23c.

The Walking One register (24b01) is shifting from the left to the right and visa versa, dependent on the "store or trace - back" control line, "STOR NTRACEBK". When its value is in "high", the array stores the vit_dec_comp[I] bit, and when its value is "low", the "trace back" is performed.

Figure 24c describes the connection of the "trace back" algorithm circuit, to the tracking array of figure 24b. Its purpose is to recover the transmitted bits, according to the branch metric selection bit, stored in every trellis stage.

The Flip Flops (24c01) are the last row of storage registers tracking array, demonstrated in figure 24b.

Figure 25a describes how all the components, ACS cells (figure 21), "tracking array"

(figures 24a, 24b) and control block of our Viterbi decoder, are connected together.

Our Viterbi decoder circuit, shown in this figure, is built of four sub-circuits.

The first is the Viterbi tracking array (256aO4), saves the ACS cells comparator bits, and later, at the end of the packet transfer, it used to recover the transmitted bit stream.

The second is the sub-circuit comprised of ACS cells array (25aO6), "avg_calc" (25aO9) and "hard" wired loop (25aO7). The third is the digital control (25alO), which synchronize the whole operation of our

Viterbi decoder.

And the fourth is, the input sampler sub-circuits (25a01-25a03).

The Viterbi ACS cells array (25aO6) is built of N ACS cells. Their state metric outputs

"SM [N-1 :0]", are "hard" wired through loop (25aO7) to the input of our Viterbi ACS cells array.

The "avg calc" (25aO9) is responsible to the state metric values average calculation, which is done every few cycles, for the purpose of normalization, to avoid state metric overflow.

The state metric values average value "sm avg" is feed back to the ACS cells array, which subtracts this value from every state metric.

Figure 25b describes two tracking arrays for the "trace back" algorithm,

"Viterbi_Tracking_Array_O" and "Viterbi_Tracking_Array_l" (25bθl, 25bO2) (VTAO₅

VTAl), which function in a "ping pong" manner.

Figure 26a describes the timing of our whole Viterbi system.

Figure 26b shows the timing of the tracking array in trace back mode.

The timing is divided to 3 parts:

The first part (26b01) shows the last cycles in the "Store" operation of the tracking array.

The second part (26bO2) shows the cycles to find, which explained later figures are. In

"MIN S[M]", the first selection of the N-M select, is defined by finding the State Metric with the minimum SM value, hence, it is the most likely State Metric to show the correct data received and decoded. This mechanism is described later in figure 28 and the timing is explained in figure 29.

The third part (26bO3), describes the trace back period.

The clock in this case is doubled, and its frequency is equal to the system clock

(SYS_CLK) frequency.

The Walking one (WO) register is "walking" the one from right to left; hence, the location in the register is going to the left (26bO4).

The Adress<N-l :0> select, is changing every clock cycle (17bO5) and the dataO bus is updated every clock cycle (26bO6). Figure 27 shows our two possible embodiments of the average circuit:

Part A, shows a continues time implementation. The amplifier (2701) is a fully differential amplifier with a common mode feedback which is not shown in the symbol. Since the output of the amplifier is an input to a V2I circuit as described in figure 12, the common mode feedback is to a reference voltage VCOMM, which is the common mode voltage of the inputs to the V2I circuit.

This is a summing amplifier topology. All the resistors values (2703-2708) are R (Resistor value in Ohms), and the feedback resistors (2709, 2710) value is R/N, where N is the number of branches in the viterbi trellis. Hence, there are N inputs SM [N-1 :0]. And the output is SM AVG:

SM_AVG = sm_avg_p - sm avg n

The output is obeying the function:

SM_AVG = 1/N * Σ_N SM [K]

Part B shows a switched capacitors implementation, where the amplifier (2702) is a fully differential amplifier with a common mode feedback, as described in part A (2701).

When PHIl is activated, every couple of capacitors (2726, 2729 and 2727, 2730 and

2728, 27831) is loaded with the value SM [K].

During PHI2, all capacitors are shorted together, and the voltage is averaged by "charge re-distribution" over the capacitors.

When using the part A continues version, the SM A VG is continuously following the average value of SM [K]. When using the part B switched capacitors, the value of

SM AVG have to stabilize during a short period PHI2. However, the amplifier is not supplying in this phase a charge to the capacitors, since the average is based on "charge re-distribution". The amplifier would consume relatively low current.

Figure 28a describes a fully differential "Minimum state metric finder" (MIN_SM) with a common mode feedback.

There are two phases of operation for the circuit. First phase is SMPL, where the specific

SM [K] is sampled upon the cell. The second phase is INT, where the state metric SM

[K] is integrated and compared. There are 3 inputs to the circuit. SM [K] is the state metric. FS is the full scale value, which is added to the SM, and INT is integration value which is input to the cell during INT phase.

Additional embodiment to the cells in figures 27, 28a:

Whenever a folly differential amplifier is implemented, it can be replaced by a couple of single ended amplifiers, where, the two inputs to the differential amplifier are separated.

Each input is going to a single ended input amplifier, and each output is separated the same way.

The reference input to each of the amplifiers is the "common mode voltage" reference, for the fully differential amplifier.

Figure 28b describes how the minimum value of SM [K] is translated to the selection of the "best probability" branch.

As explained earlier, our correct viterbi trellis branch is the one with the minimal (SM

[K]) value. Hence, the Adress[M-l:O] selection should be of the one with the minimum value in SM[K] .In other words, the one "MIN SM" cell where its FF output is raised earlier then the others.

The content of the cells (28b01-28b03) is described in figure 28a. The digital control

(28bO4) controls the SMPL phase and INT phase and gets, as inputs, all FF outputs Q[N-

1:0].

Figure 29 - Additional embodiment of MIN SM select timing:

This embodiment, of the minimum SM [K] select, is based upon existing circuitry which is described in figure 11. The timing of the additional embodiment is described in this figure.

At the end of the packet transfer, the output SM [K] is stored at the output of each analog cell (2901)

The operation of adding the Full Scale (FS) value is implemented by the cell dedicated for the average cancellation, by adding FS instead average to the input of that cell.

At the end of the packet transfer, additional Phase M+l is added (2902), where the FS value is added and stored back at the SM [K] output.

This embodiment is implemented by adding a ramp voltage to the same input as before

(2903). By doing so, the output at SM [K] is integrated during the "INT" phase in the same manner as described in figure 19a. "Ultra Low Power Fully Differential Current Mode Viterbi Decoder Subsystem'' :

In order to describe and explain our innovationist Viterbi decoder, we have divided our

Viterbi decoder into logical & functional partitions. (We have chosen one way of partitioning among many).

In figure 30 the "Add Compare Select" (ACS), which lies in the basis for our Viterbi subsystem, is described.

Our ACS signals are divided into three sections. The first is the digital control signals

(3017), which are the outputs of the CONTROL (3007). These controls synchronize the operation of the Viterbi decoder ACS. The second, all analog inputs and outputs of the

Viterbi decoder are voltage mode signals. The third, internal signals INP and INN

(3013,3014) are current mode signals.

Our ACS is comprised of the three sub-blocks. The first is the control block (3007), which generates the digital control and monitors the operation of the ACS. The second are the processing cells, YCELL (3001,3002), SMCELL (3003,3004) and two modes secondary AVGCELL's (3005). The third is Current Mode Sample and Hold (CMS&H)

(3006), which perform the summation and hold of the ACS.

The YCELL's (3001,3002) provide fully differential current, which present the input values yθ, y 1. In this figure we have described only two YCELL's for two analog input per Viterbi decoder stage. However, since the processing is done in the current domain, a third and fourth (and so forth) YCELL's could be added easily. Therefore, theoretically, there is no limit on the number of input cells that could be added. The YCELL's get their inputs (yθ, yl) from a "common to all" Viterbi decoder sample & hold (S&H) cell.

It is important to mention, that the YCELL should be physically placed near the

"common to all" Viterbi decoder S&H cell, because the need of:

• Matching requirements between the primary "common to all" Viterbi decoder S&H cell and the YCELL secondary, is better in terms of transistor threshold and conduction factor.

• Matching requirements in term of Lithography during the die manufacturing.

• Eliminating junction temperature, supply voltages, ground voltages and noise differences between two remoter locations. The SMCELL's (3003, 3004), are functionally similar with the YCELL's. They provide fully differential current replica of the state metric inputs, to the particular ACS. Every ACS cell gets in its inputs the state metric values of other two ACS cells, where one of them, may be, in some cases, the same cell. In later explanations these inputs will be denoted as SM [L] and SM [K].

The two modes AVGCELL's (3005), which are functionally similar to the previous two ones. Their purpose is to enable the subtraction of the state metrics average or maximum value from all states metric in the Viterbi decoder equally (when the orientation of the state metric is positive the AVEGCELL will subtract the maximum value, and when the orientation of the state metric is unknown, the AVGCELL subtracts the average value). This without affecting the difference in values between state metrics in order of avoiding overflows and underflows resulted from the accumulation of branch metric in every stage.

It is noted that only the difference between the state metric values is important, therefore, common values, from an AVGCELL (3005), could be subtracted evenly from all states metric.

It is the choice of the system designer to decide how frequently the average subtraction is performed. As the subtraction is more frequent, the average values are kept smaller, however, the average subtraction circuitry consumes power, therefore, as the use of it, is more frequent, more power is consumed. (There is also a primary AVGCELL, detailed in figures 35, 35a).

As in the case of YCELL, both SMCELL and secondary AVGCELL are to be physically placed near the sources of their analog inputs.

CMS&H cell (3006) is summing all the currents from the five, or more, input cells through the inputs IINP, IINN (3013,3014). This circuit is operating in two basic clock cycles (see figure 30a). The first is the "Compare and Select". The second is "Add". In the first clock cycle, all the inputs are controlled to provide at the summing current inputs a subtraction between the two updated state metrics. In the second clock, the minimal selected state metric is re-calculated for the successive iteration of the Viterbi Decoder. The VREF input to the CMS&H cell (3006) is the reference voltage, which is forced upon the current summing inputs IINP, IINN by the feedback loop in the circuit, therefore, reducing the effective capacitance at the current summing inputs. The output VITCMP (Viterbi Compare) (3015) is the outcome of the first phase "Compare and Select". This output is going to the CONTROL (3007), for selecting the minimal state metric input, to be re-calculated in the successive clock cycle. This output is also going to the register array, to be written "as is" if the "trace back" method is utilized, or, to select a "register exchange" if its method is utilized.

The analog voltage outputs (3016) are the values of the state metric which are going to the other ACS cells.

Figure 30a demonstrates the whole system timing operation, working in two 0, 1 phases (3000a-3001a). During Phase 1, values indexed "PHIO", are changing, and while all values indexed "PHIl" are frozen.

During Phase 0, values indexed "PHIl", are changing, while the "PHIO" values are

"frozen".

The "frozen" values are "inputs", while the changing ones are calculated and/or stored.

Figure 31 shows the "Common to all Viterbi System" S&H input cell.

The input voltage V (Yin) is connected to a "Voltage to Current" (V2I) translator (3101).

The differential output values are IBY/2 + ΔY, IBY/2 - ΔY. Where IBY/2 is the DC value and ΔY is the differential current, representing the input value.

Figure 32 shows the ACS YCELL which translates the input values yθ, yl into the current summing inputs of the CMS&H IINP, IINN (figure 30 - 3013,3014).

There are three groups of transistors in this figure. The first, are the current sources reflecting the input value (yθ or yl) during phase 1 (3201-3204) and all the gates voltages connected to their respective gates indexed "PHIl" (figure 31 - 3106,3108)

The second, indexed "PHIO", which is operational during phase 0, operates the same way

(3205-3208).

The third group, are the P-channel current sources (3209-3212), operating when the N- channel transistors are active. The P-channel current sources subtract the DC current from the N-channel sources, hence, only the delta currents +/-ΔY are flowing out through the outputs YOP, YON.

Each of the P-channel sources is a switched current source with DC current of IBY/2.

Each of the N-channel transistors carries IBY/2 +/- ΔY current. The current difference, flowing to the output is therefore, IBY/2 - (IBY/2 +/- ΔY) = -/+ ΔY.

The inputs to the ACS are added or subtracted, according to the associated state metric function, hence; every N-channel current source is routed by two transistors to the output.

YNEG is the addition sign. When YNEG is positive, the current source connected to

YPPHIl, YPPHIO (3101,3102,3105,3106) is routed to YOP, while the current source connected to YNPHIl, YNPHIO (3103,3104,3107,3108) is routed to YON. On the other hand, when YNEG is negative, the current source connected to YPPHIl, YPPHIO is routed to YON and the current source connected to YNPHIl, YNPHIO is routed to YOP.

During calculation, every input can be also multiplied by a factor of 2, hence, the added inputs are multiplied by 1 (YxI) or 2 (Y*2). The N-channel sources (3101, 3103, 3105,

3107) are sourcing the currents whenever the input is selected, however, the rest of the N- channel sources (3102, 3104, 3106, 3108) are providing current when the inputs are multiplied by 2. Also, the DC current is multiplied. In order to compensate for this additional DC current, the P-channel source is multiplied too. The P-channel sources

(31031 , 3110) are selected whenever the Yx 1 input is used and the sources (3111, 3112) are selected when the Y^χ2 input is used.

Figure 33 shows the SMCELL in the ACS cell.

Transistors (3301-3304) operation is similar to transistors (3101-3108) in figure 31, but without multiplication by 2.

Current sources (3301, 3302) and (3303,3304) are supplying the differential currents to the outputs during time PHIl and PHIO respectively.

The currents supplied through the switches (3301a-3304a, 3301b-3304b).

Figure 34 shows the Current Mode Sample and Hold (CMS&H) cell. This cell is summing all the input currents and routs them into the transistor chains (3410 - 3413).

The cell is similar to the Y input common part described in figure 8.

Figure 35 shows our "average subtract" common part.

Our common part AVGCELL is used as a primary sub-circuit in a current mirror circuit, which calculates the average or maximum value of all state metrics, providing the analog voltage value to the inputs of our secondary AVGCELL's. This circuit is activated only when the "average subtract" is to be performed.

Figure 35a: describes our differential "Winner Takes it All" (WTA) circuit, which is used for two tasks. The first, finding the maximum value of differential state metrics, for the purpose of normalization, to avoid overflow. The second, finding the minimal state metric value, toward the end of the Viterbi decoding process, to select the most probable path.

Figure 36 describes the ACS AVGCELL. The analog inputs, AVGP and AVGN, connected to the P-channel chains (3603, 3604), replicate the currents in the common part AVGCELL (average current) or common part MAXCELL (maximum current) described earlier in figures 35, 35a respectively.

The n-channel current sources (3601, 3602) are subtracting the bias current IB, hence, the output currents of the cell through IINP and IINN are +/-ΔR.

Figure 37 shows the full integration of our Viterbi decoder subsystem.

There are N states in the system. Hence, there are N ACS cells (3704-3706). Each cell provides four analog outputs. Therefore, there are four analog signals busses. The busses are feedback to the set of N ACS cells as a couple of inputs in every cell, and to the

AVG_SUBTRACT_COMMON cell (3701).

In this figure there are two input cells (3702, 3703), however, as described earlier, additional input cells could be added. Accordingly, YCELL should be added and in every

ACS cell.

Figure 38 describes a typical timing diagram of our Viterbi sub-system.

Figure 39, describes rate 1/3 Viterbi encoder (K=7), that is being used by many communication standards today. The input (3901) is fed into a delay line (3914-3919) from which three outputs output A (3920), B (3921) and C (3922), are calculated. The outputs are XOR combinations (3902-3913) of the recently stored data.

Figure 40, describes our "Thresh-holding Scarce State Viterbi decoder" (TSST-VD), for the Viterbi encoder of figure 39. Our TSST-VD, assumes that the path resulted from state "0000000" is the most likely trellis path, and a special block is responsible of selecting most likely N sub-set states.

Our TSST-VD is comprised of seven main blocks:

The first is, hard decision unit (4002), which is built of three comparators (4002a-4002c).

The second is inverse encoding circuit (4003), which uses the, three hard decision data, and generates the "recovered" transmitted bit stream.

The third is, rate 1/3, K=7 Viterbi encoder (4005), which uses the "recovered" transmitted data and generate valid Viterbi encoded stream, used to modulate the analog input data (4001), and to generate "nearly all zero" transmitted data.

The fourth is the input data modulator (4006), which changes the sign of the input data stream, according to the encoded Viterbi stream (4005a-4005c). The fifth is our Viterbi decoder that gets the modulator (4006) outputs and decodes the data. Practically the decoded bit stream at the Viterbi decoder (4007) should have "nearly all zero" data, which makes the "0000000" trellis path, the most probable path.

The sixth is a delay line (4004) that eliminates the modulation of the "recovered" bit stream (4005a-4005c) on the input data (4001, 4006).

The seventh is, ACS on/off selection unit (4008), responsible of switching on and off the different analog ACS units, and therefore to further reduce the power consumption.

"Current Mode Micro Power Multiplier with floating gate offset cancellation for multiplication of two variable currents"

A floating gate analog multiplier performs multiplication between two arbitrary numbers

"a" and "x". The analog multiplier produces at the output the multiplication result "α"«"x" . The inputs "a", "x" , and the output "a"»"x" , are represented by analog parameters such as voltages or currents.

A new and innovationist fully differential floating gate analog multiplier is described in this patent application, ("our multiplier").

Figure 41describes our multiplier cell is constituted off a floating gate multiplier which is operated in the sub-threshold region of transistor operation and the result is an ultra low power multiplication.

Our multiplier could be used in a wide range of application utilizing analog signal processing and devices such as: WiMAX, WiFi Blue tooth, Mobile TV, Ultra Wide Band receiver for cameras, MP3/4 players, iPODs Image pipe and all known wireless devices.

Figure 42 describes the basic multiplier cell which is based on a current mirror circuit.

The multiplier cell (Figure 42a) is built of transistors (4201,4202).

The current mirror multiplier transistors are operated in the sub-threshold region of operation.

Figure 43a describes our 2q fully differential multiplier.

VREF [0] (4307a) and VREF [1] (4306a) are functioning as described in figure 1 (VREF

(4207) and VREFL (4208)) respectively. The value of W is supplied to the cell through these inputs as described earlier in figure 1.

The differential current is supplied to the input through the nets IINP and HNN (4317a,

4318a). Figure 43b describes our 2 quadrants (2q) fully differential multiplier with cascode.

Figure 43c describes our 4 quadrant fully differential multiplier.

Our circuit will not be explained under this paragraph but later in the explanation of the 4 quadrant cell in figure 43 d.

Our circuit is similar to the circuit in figure 43 a, however, our cell includes two primary branches (4315c, 4316c) and each one of them has a couple of secondary branches

(431 Ic and 43143c, 4313c and 4314c). Additional difference is, that instead two inputs -

VREF [0] (4308c) and VREF [I] (4307c) - an additional input is added - VREF [-1]

(4306c).

Figure 43d describes our 4 quadrant (4q) fully differential multiplier with cascode.

Our 4q multiplier is a fully differential multiplier.

Figure 44 shows the relation between the reference positive/negative L and our multiplier constant "w".

For a given "w", positive L (4401), determines VREF [I] (4307d), while negative L

(4402) determines VREF [-1] (4306d).

In other words, we demonstrate in figure 44, what are the values of voltages needed in

VREF [I] (4307d), VREF [-1], (4306d) for a constant "w".

Also it is clear from figure 44, that the relation between positive/negative L to "w" is a logarithmic relation.

We have shown that our multiplier can function with all constant "w" values.

Figure 45 shows how to use our multiplier for cases where "w" is variable. References

(4500, 4501, 4502, 4503, 4504) show our multiplier, with the two control inputs VREF

[1} (4503), VREF [-1] (4504) that are connected to a logarithmic circuits (4505,4506) that calculate the logarithmic values for "1+w" (4507, 4509) and "1-w" (4508, 4509).

Therefore, by using the circuits (4505, 4506, 4507, 4508), it is possible to use our multiplier in cases where "w" is variable.

Although that our multiplier works in the logarithmic sub-threshold range, still, as

We have shown in figure 45, it can function with all variable "w" values, which enable our multiplier, to be used, with extremely low power.

We will cover the operational principal of our multiplier. Our multiplier is comprised of two sub-circuits. The first is the multiplication cell, multiplicand sub-circuit ("our multiplicand sub-circuit"), which deals with the first operand of the multiplication. The second is the multiplication cell, multiplier sub-circuit ("our multiplier sub-circuit"), which deals with the second operand of the multiplication. This cell is based on a multiplication cell presented in our Patent "Current Mode Micro Power Multiplier with floating gate offset cancellation" (Israeli patent app. No.187075).

We will cover here, in detail, the operational principals of our multiplier. We will show, step by step, the equations that demonstrate the relation between the input and the output of our multiplicand sub-circuit.

Figure 46 is been referenced now. A single cell is supplying these inputs, and hence, the inputs are named VREF, VREFP, and VREFN respectively. Also, the multiplier has two variable currents as inputs, and hence, the names are changed from IINN, IINP to

IINNl, IINP1 respectively.

This circuit is based on primary transistors branch (4605), secondary transistor branch

(4605,4607) and performs the multiplication of input differential current (4610-4611) by a coefficient "W", represented by VREFN2 (4602), VREFP2 (4603) & VREF

(4604).

Figure 47 is the VREFP2 (4710), VREFN2 (4709) generator circuit. The purpose of this circuit is to Generate voltages VREFP2 (4710), VREFN2 (4709) that are:

• Represents the second differential operand IIN2 in our multiplication cell.

• Based on logarithmic function.

• Cancel the effect of the temperature equivalent potential (Ut), seen in equations (4712).

Our circuit is comprised of four sub-circuits :

The first, is the floating gate programming arrangement, built of two pairs of programming voltages (4708), switches (4706) and floating gate transistors M1,M2 &

M3 (4701,4702,4705), which is used to compensate against process variations, by implementing "floating gate programming mechanism " [1], changing the threshold voltage of each transistor by charging it's floating gate.

The second, responsible of generating reference voltage VREFl (4713), as a function of

VREF (4714), current source with the value Idc (4707) & Ut.

The third, generates VREFN2 (4709) as a function of IINN2 (4711).

The fourth, generates VREFP2 (4710) as a function of IINP2 (4711).

Figure 48 presents the block diagram of the complete fully differential current mode analog multiplier which is built of two circuits. The first, is the multiplier sub-circuit (4801), which gets one of the multiplication operands, differential current IIN2 (4803), and generates reference voltages, as was explained above (figure 47) which are a function of the differential current IIN2.

The second, is the multiplicand sub-circuit (4802), which gets the reference voltages

VREFP2,VREFN2, on one input, and the other multiplication operand, differential current IIN1 (4804), on the other input.

The result of the multiplication is presented as differential current at the output (4805).

On the right side of figure 48, the symbol of the complete multiplier is shown and has two differential current inputs operands IIN1, IIN2, and one differential current output

IOUT.

The derivation for the output current Eq(29, 30) is demonstrated by equations (4807).

In the technology known today power consumption in long line of application is too high and shortens battery life. We have solved this problem.

In our patent we have presented our innovationist analog multiplier.

In our earlier patent, "Current Mode Micro Power Multiplier with floating gate offset cancellation" (Israeli patent app. No. 187075 & PCT/U2008/001692), we have shown multiplier functions by multiplying the input by a constant values (Figures 1,2,3), then we have demonstrated how our multiplier functions in multiplying variable values (Figure

3,4,5,6,7). In the mentioned patent, we have proved that our multiplier improves significantly energy consumption of signal processing by reducing the power consumption.

We have compared our multiplier to the newest low power digital multiplier demonstrated in US 2003/0120695 Al, that shows the lowest power consumption digital

8x8 bits resolution multiplier, working at lOMhz (see table 3 there), manufactured in

0.5μm process. The reported power, in that patent, is about 0.88 mWatts, which means that in 0.13μm and lMhz, the power consumption is :

0.88ιwwαtts /10 5068nwatts I Mhz

In our multiplier, the power consumption for the same multiplier 8X8 bits resolution at

1 MHz is:

6 * 50nAmp * Iv / 3Mhz + (3 * 50nAmp + 1 OOnAmp) * Iv / 3Mhz = 183wwαtø I Mhz It is clear that this invention is about 28 times better, in power consumption terms. References:

[IJ "Adaptive Algorithm Using Hot-Electron Injection for Programming Analog Computational Memory Elements Within 0.2% of Accuracy Over 3.5 Decades " by Abhishek Bandyopadhyay, Member, IEEE, Guillermo J. Serrano, and Paul Hosier, Senior Member, IEEE. IEEE JOURNAL OF SOLID- STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006

"Complete Current Mode Micro Power Divider circuit with floating gate offset cancellation";

A floating gate analog divider performs division between any two arbitrary numbers "a"

and "x", for example. The analog divider produces at the output the division result 'V

The above inputs and output are represented by analog parameters such as voltages or currents.

In general, analog divider relates to the area of "analog signal processing", in which rather then using a digital processing, an analog processing is utilized. By doing so, the power consumption of the processor is reduced significantly and transistor total count is decreased.

A new and innovationist fully differential floating gate analog divider is described in this patent application, ("our divider").

Our divider is designed to divide a differential currents representing "a" by differential current, representing "x". The result is presented as a differential current at the output of the divider.

Our divider cell is based upon floating gate multipliers which are operated in the subthreshold region of transistor operation - and the result is an ultra low power division. Our divider could be used in all analog signal processing applications such as: WiMAX, WiFi Blue tooth, Mobile TV, Ultra Wide Band receiver for cameras, MP3/4 players, iPOD, Image pipe and all known wireless devices.

The following description will explain our new divider which is relied on the two multiplier patents, explained in the background.

Figure 49 describes our divider cell multiplicand sub-circuit, which describes subthreshold multiplier built of FG-MOS transistors, with two differential outputs. The first output (4909,4910) generates the multiplication of the differential input current

(4907,4908) by the multiplication coefficient "W", determined by VREFP2, VREFN2 &

VREF (4914).

The second output (4911, 4912), generates differential current, representing the multiplication of the coefficient "W" by the IREFP2 and IREFN2 relative to VREF

(4914).

Figure 50 describes the complete, fully differential, sub-threshold divider. Our divider is built of three sub-circuits. The first is the divider cell, differential multiplier (905). The second is the divider cell, multiplicand sub-circuit (900). The third is the divider cell control circuit, built of differential amplifier (908), common voltage correction circuit

(5009, 5010, 5011, 5012, and 5013) and the current bus (5006).

Figure 51 describes our preferred embodiment (out of many), of the differential error amplifier (5008 in figure 50) with common voltage control (5009 in figure 50).

The amplifier is built of three sub-blocks. The first is a common mode sub-circuit (5101,

5104).

The second is differential mode sub-circuit (5102, 5103).

The third is an optional output amplifier (5106).

The inputs from the differential current subtraction (5001 in figure 50) VlD, V2D (5012,

5013 in figure 50) compared to the common mode voltage reference , VREFCOMM

(5108), by the common mode differential pair (5101), while the differential voltages,

VlU, V2U are amplified by the differential pair (5102).

The results of the common mode differential pair operation are increase or decrease of outputs VRP, VRN together (5107) to the desired level.

Current mirror (5104) is part of the common mode amplification (5101) and also, it serves as active loads for the differential pair (5102). IfVREFCOMM is higher then the average of VlD, V2D, the current source to differential pair (5102) is lowered, and the load current from the current mirror (5104) is going higher, hence, the common mode of

VOl, VO2 (5105) is going higher , and visa versa.

In our patent we have presented our innovationist analog fully differential divider cell.

We have shown how our divider functions by dividing one input variable by another input variable, represented by differential currents. We have shown this process in figures

(49, 50, and 51). Our divider works in the sub-threshold region of operation, and works with differential current.

Therefore, we have proved that our divider decrease significantly energy consumption of signal processing by reducing the power consumption.

We have compared our divider to the newest low power digital multiplier (when we have assumed that the power of digital divider is greater than digital multiplier) demonstrated in US 2003/0120695 Al, that shows the lowest power consumption digital 8x8 bits resolution multiplier, working at lOMhz (see table 3 there), manufactured in 0.5μm process. The reported power, in that patent, is about 0.88 mWatts, which means that in

0.13μm process and 1 MHz, the power is:

OMmwatts 110 • f -Jζ) = 5068mvαtø / Mhz

In our divider, the power consumption for the same multiplier 8:8 bits resolution at lMhz is:

4 * 50nAmp * lv/3Mhz +

+ (3 * 50nAmp + 2 * 1 OOnΛmp) * Iv / 3 Mhz

+ (4 * 50nAmp + 3 * 50nAmp) * Iv / 3Mhz

2 * 100nAmp* lv/3Mhz

= 366nwatts I Mhz

It is clear that this invention is about 14 times better, in power consumption terms.

"Ultra Low Power (ULP) Carrier Frequency Correction for OFDM Receivers";

In today's known communication standards, the receivers use DSP to process the samples coming from the antenna and decode it to a digital bits stream. In a communication system, the transmitter and receiver are remote, and hence, the transmitter and receiver are using different clock sources to supply the Radio Frequency (RF) in the transmitter and the local oscillator (LO) in the receiver. The two frequencies at both sources are almost the same. However, there is a small frequency difference - Δf. Figure 52, describes the mathematical operation done by the receivers mixer (5201). The two multipliers (5204, 5205) get the RF signal from the RF IN (5212) and the mixer multiplies each one with cosine and sine waves, where their phases are changing at the rate of the LO frequency - f(LO). The Low Pass Filters (LPF) (5206, 5207) remove unwanted harmonics, which are higher then the base band frequencies. Then, the output is going to the carrier correction (5208, 5209).

Figure 53, shows the basic multiplication cell. This figure is also valid for DSP implementations, where the multiplications and additions are digital, and also, for our discrete time analog signal processing implementation. In figure 53, Iin and Qin (5301, 5302), are fed into four multipliers (5305-5308), which multiply the input (5301, 5302) by the Sine{ φ(i) } and Cos{ φ(i) } values, as described earlier in equation 5. The output is generated at the adders (5303, 5304) outputs. Figure 54, describes our novel ULP carrier correction circuit array. The circuit described in figure 53 is placed "N" times (5441-5443, 5451-5453, 5461- 5463). These cells are called "Multiplier Multiplicand Cells" (MMCC). Figure 55, shows two modules. The first is, "Multiplication Multiplier Cell" (MMTC). The second is the DAC.

The number of digital bits at the DAC input is "N2", which is the number of bits required to support the accuracy of multiplication, resulted from performance needs. Our calculation shows that N2 is usually 8 bits. The DAC is based on a current steering DAC architecture, with a very low consumption current. The current needed to support the MMTC module, is in the range of 10OnA - 20OnA, hence, a unit cell for 8 bits DAC is carrying a current of V₂₅₆ of these values, resulted in 0.38nA - 0.75nA Per unit. This is a very low current and special measures have to be taken in order to keep the accuracy of the DAC.

Figure 56, is the "Multiplier Multiplicand Cell" (MMCC), which is the realization of our cell in figure 3. This cell gets as an inputs the differential currents Kn (I) (5601) and Qin(I) (5602).

Figure 57, describes the top level "Carrier Correction Module" (CCM). Figure 58 describes the preferred embodiment for the "N cells Current Sampler". The input is coming from the node V2I (5823).

The basic current sampler cell is based on "Current Copier Cell" architecture (5817). The amount of cells in the array is "4*N" cells, similar to (5817). The current copier gets the input current at the input node (5819). When the "SAMPLE" control (5821) is asserted, the cell operates in closed loop, where one of the amplifiers (5803, 5804) controls the gate voltage through the input (5818). As a result, the gate

(5824) assigns at the transistor the same current as in the input (5819).

Figure 59, describes the timing diagram in which, the System clock is in the first row

(5901). The rate of the system clock is equivalent to the sampling frequency.

V (Iin) and V (Qin) (5902) are voltages coming continuously from the receiver's tuner.

There are two control inputs PHIEVEN and PHIODD.

When PHIEVEN is asserted (5903), all the outputs, driven by first group cells (5805,

5807, 5809, 5811, 5813, 5815), are sinking currents at the Iin [N-I: 0] outputs, which are the inputs to the CCM (in figure 7 - 703).

When PHIODD is asserted (5904), the first group is sampling the inputs, while the second (5806, 5808, 5810, 5812, 5814, 5816) supply's the output (which is the input to the CCM).

"Ultra Low Power (ULP) Timing Synchronization Method for Wired and Wireless Receivers":

Here we present a new innovative ultra low power timing synchronization method for wired and wireless receivers, modems and serial digital communications ("our ULP timing synchronization"). A novel "phase rotator" implementation is introduced, for the purpose of timing correction.

In other implementations, a phase rotator is built off analog multipliers, usually, employing Current Mode Logic (CML) methods.

This way, by having a first, set of "In Phase" (I) and "Quadrate Phase" (Q), close to the output frequency. A second, sine and cosine signals, represent the phase correction. A third, multipliers and adders, any arbitrary phase, at the output, could be achieved. These multipliers, adders are consuming relatively high current.

In our invention, we present a way to perform the same function without the need of these multipliers and adders. Instead, our invention employs low-power capacitive Digital to Analog Converter (DAC) and a simple comparator. By doing so, the power consumption is significantly reduced, and the accuracy of the phase is improved.

In communications system, sometimes, the function of timing synchronization is done on the received data, rather than in the clock. This function is performed by interpolating symbols samples, in such away, that the interpolation result representing a new sample, on the right sampling time, which is between two received samples. We have compared the power consumption of this method to our innovative method here.

We will show later how we reduce the power consumption in a ratio of 1 : 35.

In figure 5 above, which describe a full wireless OFDM receiver, the transmitted signal bandwidth is very low compared to the RP frequency. As a result, the bandwidth of the information signal after mixing is maintained.

The tuner (501) is supplying two outputs. The first is, called "In Phase" (I). The second is, "Quadrate" (Q). These signals are going to "Sample and Hold" (S/H) (502, 503) which produce a stream of I & Q analog voltages in the sample rate defined by the receiver.

As mentioned before, there is a small, about 50-300ppm, frequency difference (Δf) between received sample rate, and the transmitter sample rate.

A special module (504) "Sampling Timing Clock Correction" is providing a clock with

"Δf ' shift in frequency, hence, the new receiver sample rate is identical to the transmitters sample rate.

The frequency shift "Δf ', is generated by "Timing/Carrier Estimation" (512), which

"measures" the sampling time difference between the transmitter and receiver. There are many methods for the timing estimation, most however, include a Phase Lock Loop

(PLL) for iterative process. In this way the sample rate S/H (502, 503) is adjusted to be as the rate at the transmitter.

The rest of the modules in the signal chain (509, 510, 519, 520, 521, 522, and 523) have to be also synchronized to the same clock provided by the "Sampling Timing Clock

Correction" (504). Hence, this module (504) provides the synchronization clock of all the modules in the receiver and the data rate at the output (524) is synchronized to the adjusted clock.

Figure 60 describes the result of sampling frequency difference problem.

To demonstrate the problem, we use a simple "Pulse Amplitude Modulation" (PAM), which is coming out of the tuner (501). In this example we show a four levels PAM signal, where the amplitudes are -3, -1, 1, and 3.

A sampling clock (6002) is providing the S/H sampling clock rate. Whenever the sampling clock (6002) is crossing zero, the PAM signal (6001) is sampled.

In this example, we provided a Δf frequency error, which is reflected in the figure by the value ΔT, where T & f are the corrected values of the sampling period & frequency respectively, and ΔT, Δf represent their associate deviations. Figure 61 shows the implementation of our new innovationist method, with some details on the frequency correction operations.

Figure 62, shows the state machine that supplies the sine and cosine, four values which are stored in registers (6109-6112). This state machine, is working in a rate, which is a fraction of the symbol rate (fθ+ Δf). The reason is, that the phase D (nT) is changing very slowly compared to the cycle time T.

It should be noted, that since the crystal oscillator receiver, is usually used to supply the clock frequency (fO+ Δf), and it's accuracy is measured in "Parts Per Million" (PPMs) of the ratio / ₍rø₊ ^_f). It is in the range of +/- 50ppm to +/-300ppm, hence, the rate of updating φ(nT) does not need to be high, and can be every few tens of (fθ+ Δf) cycles.

Figure 63, shows our DAC preferred embodiment. This is a capacitive DAC, which can operate at high frequency, with a relatively, low current consumption.

In this embodiment we show a solution of 6 bits DAC, where the digital input is marked as B [5:0].

The DAC presented here, is a fully differential with two sets of buffers, a first set of buffers (6326) to drive the positive part, and a second set of buffers (6327) to drive the negative part.

Figure 64, is a timing diagram demonstrating the operation of our synchronization method.

ief Description of the figures

Figure 1 : OFDM symbol structure.

Figure 2: general digital signal processing system block diagram.

Figure 3: receiver implementation block diagram based on digital signal processing method. Figure 4: OFDM receiver implementation using digital signal processing. Figure 5: ultra low power, discrete time analog signal processing based,. OFDM receiver. Figure 6: eight points Fast Fourier Transform (FFT) flow/block diagram. Figure 7: Addition and multiplication symbols with low power circuit implementation. Figure 8: ultra low power OFDM receiver - with analog processing for parameters estimations/calculations. Figure 9: ultra low power OFDM receiver - with Digital siganl Processing (DSP) for parameters estimations/calculations .

Novel ultra low power Viterbi Decoder circuit.

Figure 10: Viterbi encoder circuit

Figure 11 : Viterbi encoder state machine description

Figure 12: Channel model with Viterbi encoder noise and Viterbi decoder

Figure 13: Trellis description of the Viterbi paths possibilities

Figure 14: Viterbi decoder Add Compare Select

Figure 15: Viterbi decoder block diagram

Figure 16: V2I

Figure 17: 12 V version c

Figure 18: Additional embodiment of the I2V

Figure 19: Comparator

Figure 20: Analog Add Compare Select (ACS) Viterbi Cell

Figure 21 : A Digital control with our ACS Cell

Figure 22: Viterbi ACS Cell Timing

Figure 23a: Ultra Low Power Flip Flop (ULPFF)

Figure 23b: Viterbi Tracking array Storage Cell For Register Exchange Solution

Figure 23 c: Viterbi Tracking array Storage Cell For Trace Back Solution

Figure 24a: Viterbi tracking array For Register Exchange Solution

Figure 24b: Viterbi tracking array For Trace Back Solution Part 1

Figure 24c: Trace Back Mechanism

Figure 25a: Viterbi Decoder top level description Version A

Figure 25b: Viterbi Tracking Array for Trace Back Algorithm.

Figure 26a: Viterbi System Timing

Figure 26b: Viterbi Trace Back Timing

Figure 27: Average calculator circuit

Figure 28a: MIN_SM cell

Figure 28b: MIN_SM cell

Figure 29: Viterbi decoder additional embodiment timing

Ultra Low Power Fully Differential Current Mode Viterbi Decoder Subsystem

Figure 30: Analog "Add Compare Select" (ACS) Figure 30a: Functional timing of our Viterbi decoder

Figure 31 : Input Cell Common Part

Figure 32: Input ACS Cell

Figure 33 : State Metric Cell

Figure 34: Current Mode State Metric Sample and Compare cell

Figure 35: Average Subtract - Common Part

Figure 36: Differential "Winner Takes it All" circuit

Figure 37: Average Subtract cell at ACS (AVGCELL)

Figure 38: Full Analog Module

Figure 39: Analog Module Timing

Figure 40: Rate 1/3 Viterbi encoder K=7 (Ultra Wide Band)

Figure 41 : Thresh-holding Scarce State (TSST) Viterbi decoder

Current Mode Micro Power Multiplier with floating gate offset cancellation for multiplication of two variable currents

Figure 42: Basic multiplier cell

Figure 43a: 2q multiplier concept without cascode.

Figure 43b: 2q multiplier concept with cascode.

Figure 43c: 4q multiplier concept without cascode.

Figure 43d: 4q multiplier concept with cascode.

Figure 44: The voltage ratio (L) versus W (Multiplier factor)

Figure 45: Our multiplier with variable "w" values

Figure 46: Multiplicand multiplier cell

Figure 47: VREFP2,VREFN2 Generator (multiplier, multiplier cell)

Figure 48: Complete Diffrential Micro Power Multiplier

Complete Current Mode Micro Power Divider circuit with floating gate offset cancellation

Figure 49: Divider cell, multiplicand sub-circuit

Figure 50: Compele, fully diffrential, sub-threshold divider.

Figure 51 : Divider cell, differential amplifier implementation.

Ultra Low Power (ULP) Carrier Frequency Correction for OFDM Receiver Figure 52: Definition of the Carrier Problem

Figure 53: Carrier Correction Implmentation Principle

Figure 54: Top level implementation: Carrier Correction Module

Figure 55: DAC and Multiplier Multiplier Cell (MMTC)

Figure 56: Multiplier Multiplicand Cell (MMCC)

Figure 57: Top level of the system, including Current Samplers

Figure 58: N Cells Current Sampler

Figure 59: Timing Diagram

Ultra Low Power (ULP) Timing Synchronization Method for Wired and Wireless Receivers

Figure 60: A Definition of the signals at the receiver.

Figure 61 : Synchronization solution

Figure 62: Sine and Cosine Constants Digital Module.

Figure 63 : Example of 6 bits Capacitive Differential Digital to Analog Converter.

Figure 64: Synchronization Signals

Claims

Claims

1. Our OFDM receiver circuit comprised of: a. Analog OFDM signal source. b. "Sample and hold" unit. c. Base band processor, based on discrete time analog signal processing.

2. Also, our OFDM receiver circuit comprised of : a. Tuner for pre-processing the RF signal. b. "Sample and hold" units for the I & Q. c. Base band processing unit for decoding the received data.

3. Our OFDM receiver circuits as in claims 1 & 2, in which the base band processing unit is comprised of: a. A synchronization circuit - for the detection and synchronization of the OFDM symbol. b. Sampling time correction clock, connected to the "sample and hold" units. c. Carrier deviation correction unit. d. A memory element to store the input data. e. A transform element that transform the input. f. Equalization unit. g. Phase correction, h. De-mapping unit. i. One or more De-interleaving, j . Forward error correction unit, k. Parameter estimation block.

4. Our OFDM receiver of claim 3, in which the signal chain blocks (a-k) are operating in the discrete time analog signal processing domain.

5. Our OFDM receiver of claim 4, in which, the multiplier used for the analog processing is a. Extremely low power, based on current mode processing. b. Operating in the sub-threshold of transistor region of operation. c. Based on FG-MOS, to allow compensation for process variations.

6. Our OFDM receiver of claim 3, in which the parameter estimation block is implemented using discrete time analog signal processing.

7. Our OFDM receiver of claim 6, in which, the parameter estimation block is implemented using: a. Extremely low power multiplier, division, addition and subtraction circuits, based on current mode processing. b. Signal processing blocks, operating in the sub-threshold region of transistor operation. c. FG-MOS transistors, to allow compensation for process variations.

8. Our OFDM receiver of claim 3, in which the parameter estimation block is implemented using Digital Signal Processing.

9. Our OFDM receiver of claim 8, in which the Digital Signal Processing comprised of: a. An analog to digital converter b. A digital signal processor based on ASIC DSP or ISA DSP methods.

Novel ultra low power Viterbi Decoder circuit

10) Our Viterbi Decoder Subsystem is comprised of : a) Digital tracking array. b) Analog computational array. c) A routing scheme to connect the state metrics at the outputs of the analog computational array to its inputs. d) A circuit to calculate the average state metric. e) Control logic to synchronize the operation of the system.

11) Claim as 10a, where the Digital tracking array is comprised of tracking array, which is used to recover the transmitted bit of the most probable path to be correct.

12) Claim as 11, where the tracking array is serving the algorithm of Register Exchange in the Viterbi.

13) Claim as 12 , where the tracking array is comprised of: a) Walking one control register for controlling the actual storage column. b) An array of Special storage cells arranged in rows and columns, where the number of rows is equal to the number of states in use, and the number of columns is equal to the length in number of bits of the block to be stored. c) Claim as 13b, where each row has a comparator input for selecting between two rows at the input, to be stored at the current row storage cells. d) Claim as 13b, where the storage cell is comprised of: i) First level "select" to select between two inputs from two different rows, ii) Second level "select" to select between the first select output and the input to be stored, where this input is pre-defined by the state row, in which the cell is instantiated, iii) An Ultra low power Flip Flop, where the data is stored.

14) Claim as 1 Ib, where the tracking array is serving the algorithm of Trace back in Viterbi decoder.

15) Claim as 14, where the tracking array is comprising of: a) Two tracking arrays. b) Two trace back state machines. c) Claim as 6a , where the tracking array comprised off: i) A walking one register to perform the two operations:

(1) When during storing data, the walking one register is walking a logical "one" from the list to the most significant bit, selecting the column where the current comparator value is stored.

(2) When during trace back, the walking one register is walking a logical "one" from the most to the list significant bit, selecting the column, where the trace back core logic is decoding data. ii) An array of Special storage cells arranged in rows and columns, where the number of rows is equal to the number of states in use, and the number of columns is equal to the length in number of bits of the block to be stored. iii) Claim as 15Cii, where the storage cell is comprising of:

(1) One "Select" between the inputs from the comparator in the analog part and between the values stored, in order to keep the value.

(2) An Ultra low power Flip Flop, where the data is stored. d) Claim as 15a, where the tracking arrays are working in a "ping pong" manner, where, one is storing new data and the other keeps the data and visa versa. e) Claim as 15b, where the Trace back state machine works in a "ping pong" manner. When one is decoding data stored in the tracking array, the other rests, and visa versa. f) Claim as 15b, where the trace back state machine comprised of: i) An N-M select for each column of the tracking array, select one of N state bits. ii) A select M -> 1 selecting one of the columns ("M" in number) to be processed by the trace back state machine core, iii) A trace back state machine core, which keeps track of the data decoded, and decoding the data backwards, relying on "trace back algorithm" of Viterbi decoder. iv) A row of enabling cells, v) A row of storage cells as in claim όciii

16) Claim as 10 where the analog array is comprised of a column of cells, where the number of cells is equal to the number of states in the Viterbi decoding.

17) Claim as 16 where each analog cell comprised of a digital control sub-circuit and an analog "Add Compare Select" sub-circuit.

18) Claim as 17 , where the analog "Add Compare Select" sub-circuit comprised of: a) Five voltages to current cells (V2I).

Two cells convert the two bits input voltages to currents.

Two cells convert to input state metric voltages to currents.

One cell converts the average state metric value to current and subtracts it from the currents of all other cells in order to subtract the average. b) Claim as 18a, where each input to the V2I has switches at its input, either to enable and disable the input, or, to invert the inputs for the purpose of subtracting its value. c) P-channel current sources at the differential summing nodes to compensate for the V2I's currents. d) Two current to voltage converters (I2V), which also perform sample and hold (S/H), working in "ping pong" manner. When one converts current to voltage, the other holds the last value, and visa versa. e) Two selectors working in a "ping pong" manner, where, one select routs one I2V result to the output, and the other routes the other I2V result to the comparator. f) A comparator to select the prioritized branch metric to decide which is the next state metric to be calculated in the ACS cell, and for the purpose of finding the minimum state metric value at the end of the process.

19) Claim as 18d, where the I2V comprised of: a) A pair of differential amplifiers with resistors to convert current to voltage. b) A pair of differential amplifiers with switches and capacitors to perform a sample and hold (S/H) of the voltage. c) Claim as 19a, where, instead a pair of differential amplifier, one fully differential amplifier is employed. d) Claim as 19b, where, instead a pair of differential amplifier, one fully differential amplifier is employed.

20) Claim as 18d, where the 12 V comprised of : a) A pair of differential amplifiers. b) Couple of resistors to convert current to voltage. c) Couple of capacitors, to store the voltage. d) Four switches for a sample and hold operation.

21) Claim as 20, where instead a pair of differential amplifiers, mentioned in claim 11a, one fully differential amplifier is employed.

22) Claim as 18a, where the V2I comprised of: a) A couple of operational amplifiers and a couple of MOS transistors, to create a couple of amplified source followers. b) A resistor between the sources of the transistors, to convert voltage to current with the ratio "R", which is the resistance value of that resistor. c) Resistors and switches to change the amplification ratio of the V2I. d) A couple of current sources to pull down to the ground, current from the sources of the MOS transistors.

23) Claim as 22, where instead claim 13a, only couple of MOS transistors without the amplifiers, to be used as the source followers.

24) Claim as 1 Od, where the Average State Metric calculation circuit comprised of: a) A fully differential amplifier. b) A Set of summing resistors to amplify all input state metrics equally, by the ratio of /N, where N is the number of states.

25) Claim as 1Od, where the Average State Metric calculation circuit comprised of: a) A fully differential amplifier. b) "N" number in couple of capacitors, to store the input state metric voltages. c) A set of switches to allow sampling the state metric, and then, short all capacitors together over the differential amplifier outputs, for the purpose of charge redistribution.

26) Claim as 18 where: a) The comparator of claim 9f serves also for the purpose of finding the minimum State Metric. b) One state metric is selected at each ACS cell. c) One input is receiving a ramp voltage. d) The outputs of the comparators in all the ACS cells are routed to the digital control module of claim Ie, for the purpose of selecting the first state, where its comparator is changed from "zero" to "one".

27) Claim as 10 , where a circuit for calculating the minimum state metric is added, and the actions taken in claim 17 are discarded, where this circuit is comprised of: a) A column of analog cells to perform a subtraction of a common ramp voltage from the state metric value. b) A digital asynchronous logic to find the first analog cell which is changing its value from "zero" to "one", in order to select the most likely state metric to be with the correct data. c) Claim as 27a, where the analog cell comprised of: i) A fully differential amplifier. ii) Resistors and switches to add Full scale value to the state metric input, iii) A pair of capacitors to apply an integration voltage (ramp voltage) at the output of the amplifier, beginning at the subtracted voltage value, iv) A comparator to sense "zero" crossing at the output of the amplifier.

"Ultra Low Power Fully Differential Current Mode Viterbi Decoder Subsystem"

28) Our Viterbi decoder subsystem (figure 37) based on analog signal processing and on differential current mode circuitry, comprised of : a) Analog ACS units, which are used for the determination of the new state metric. b) Common state metrics average or maximum value computation block. c) Common input stage, for sampling the input received data. d) Control mechanism to our Viterbi operation. e) Programming mechanism for offset and manufacturing deviation cancellation.

29) Our TSST-VD (figure 17), where the analog inputs are altered to represents nearly all "0" transmission. 30) Claim as 28 & 29, where our Viterbi decoder includes special circuitry that control the ON/OFF state of the ACS cells, by using a threshold value determined by state 0 metric value and the N sub states.

31) Claim as 28e, where the programming of the different analog circuitry current sources, current mirrors etc, is based on Floating Gate MOS (FGMOS) gate programming.

32) Claim as 28e, where the offset manufacturing deviation cancellation is based on programmed current sources.

33) Claim as 31, where the floating gates of the FGMOS transistors are connected via tri- state buffers of JTAG circuitry, enabling serial programming.

34) Claim as 31, where a group of FGMOS transistor includes special circuit for measuring the offset, and the measured offset data "1" or "0" is read by the JTAG read mode.

35) Claim as 28a, where the analog ACS (figure 7) is comprised of: a) At least two y cells (YCELLS), which are used to translate the differential input voltage to a differential current, having the ability to multiply the current by 1 or by 2. b) At least two State metric cells (SMCELL), which are used to re-generate the state metric differential current, that were previously stored as primary branch of current mirror gate voltages. c) One average cell (AVGFCELL), which is used to subtract the state metrics average or maximum differential current, for avoiding overflow. d) One CMS&H cell, which is used to sum the YCELL currents, state metric current, average or maximum value, and to hold the new state metric value. e) One digital control block (CONTROL), which is used to generate the control and clock signals to the said YCELLS, SMCELLS, AVGCELL and CMS&H cell.

36) Claim as 28c, where the input cells is used to S&H the input analog stream, working with two phases - phase 0 & phase 1. To allow our Viterbi decoder to work, while phase 1 is active on samples stored during phase 0 and simultaneously store new sample.

37) Claim as 36, in which there are at least two differential input cells, where each input cell (figure 31) is comprised of: a) Input differential voltage to differential current converter. b) Two differential analog memory circuits, where the first is sampling during phase O, and the second is sampling during phase 1.

38) Claim as 37b, where each differential memory circuits, is based on two current copier sub-circuits, each of them connected to the positive and negative nodes of the input. Our copier sub-circuit comprised of: a) Two switches, where the first is used as an input switch to analog memory element, and the second is used to connect the input current to the main transistor. b) An analog memory element, which is used to hold the gate voltage of the main transistor, which drains the input current. c) A main transistor element which is part of the loop control. d) Operational amplifier, which controls our current copier sub circuit main transistor gate voltage.

39) Claim as 35a, where each of the YCELLS (figure 32) is working in two phases (stagard mode) - phase 0 & phase 1. While in phase 0, data that were stored in phase 1 is used as an input and visa versa. Built of identical YCELLS sub-circuits, where each of them comprised of: a) Four main transistors, to generate the two copies of the differential current. b) Four "one to two" switches, used to generate negative an positive currents. c) DC bias current circuit that generate the correct bias, so to give at the output, the differential analog current representing the inputs.

40) Claim as 35b, where the SMCELL (figure 33) is built of two identical sub-circuits, working in two phases - phase 0 & phase 1. While in phase 0, state metric that was stored previously, during phase 1 is used, and visa versa. Where each of the sub- circuits is comprised of: a) Two current sources transistors that generate the current representing the state metric differential values. b) Two "one to two" switches, to allow generating positive and negative currents. c) DC bias current circuit that generate the correct bias, so to give at the output, the differential analog current representing the inputs.

41) Claim as 35d, where the CMS&H (figure 34) is built of two identical sub-circuits working in two phases - phase 0 & phase 1. While working in phase 0, data that was previously stored in phase 1 , is used to indicate the state metric value and visa versa. Where each of the sub-circuit is comprised of: a) Two analog memory units, one for the positive node of the current and the other for the negative node.

42) Claim as 41, where the analog memory unit is comprised of : a) A first switch which drive a capacitor through operational amplifier. b) A capacitor that holds the data, and is used as an input to a transistor, which is the primary branch of a current mirror. c) A transistor, which its gate voltage is connected to the said capacitor and its drain current, is forced to be identical to the input current, through the loop control. d) A second switch which is used to connect the said transistor drain pin to the input, while it is in sampling mode.

43) Claim as 35c, where the AVGCELL (figure 36) comprised of two main sub blocks. The first is the average cell common part, and the second is the average subtract cell located in every ACS cell.

44) Claim as 28b, where the average cell common part (figure 35) comprised of : a) Operational amplifier, which is used to drive the gates of multiple transistors, through a switch. b) A switch which is used to connect the operation amplifier to a capacitor, which is connected to the gates of the said multiple transistors. c) A capacitor, which is used to hold the voltage, representing the average of all SMCELLS currents. d) Multiple couples each comprised of two serially connected transistors, where the first one is used as a switch to connect the input to the drain of the current source transistor. And the second one is used to generate a current which is a function of the said capacitor value.

45) Claim as 28b, where our average cell common part (figure 25a), based on differential "Winner Takes it All" circuit, comprised of : a) Multiple SMCELLS to generate the state metrics differential currents for our multiple comparison blocks. b) Multiple comparison units, connected via common wire, each having a differential current input and a digital output, where the comparison cell with the maximal value would have "1" at its output, and all other will have "0". c) A maximal value selection unit, using the said digital outputs.

46) Claim as 45b, where a comparison unit is built of: a) Differential to single ended converter, for finding the maximal value. b) Main transistor, which is connected to the said single ended current. c) Loop transistor, connected to the main transistor, which sets the common voltage. d) Comparison transistor, which its gate is connected to the output of the loop transistor.

47) Claim as 35, where our differential "Winner Takes it All " could be used either, to find the maximal value, or the minimal value.

48) Claim as 47, where our differential "Winner Takes it All " includes a control polarity switch with two modes. The first, regular polarity, which is used to find the maximal value. The second, reverse polarity, which is used to find the minimal value.

49) Claim as 33, where the average subtract cell, is located in every ACS cell of claim 35c. comprised of: a) Enable pin, which switch on and off the average subtract cell. While in ON mode, the average subtract cell will generate a differential current, representing the average or maximum current of all state metric cells. b) Two current mirror secondary branches, which generate the differential current. Each branch generates the average or maximum current through PMOS transistor that its gate connected to the said capacitor of claim 44c. c) Two DC bias current secondary branches, connected to the said PMOS transistor branches, for eliminating the PMOS bias current.

50) Claim as 27, where our Viterbi sub system ACS units, include ON/OFF control, to further save power.

"Current Mode Micro Power Multiplier with floating gate offset cancellation for multiplication of two variable currents

51) Our complete analog multiplier comprised of two sub-circuits (figure 48). The first is multiplier sub-circuit. The second is multiplicand sub-circuit. Where, the multiplier sub-circuit, gets one variable of the multiplication, "multiplier" as current, and generates, reference voltages, representing it as "voltage". And the other, multiplicand sub-circuit, gets the second variable, as a current, on one input and on the other input gets the voltages, generated by the said multiplier sub-circuit. The result is multiplication between two currents, and presented as current at the output.

52) Claim as 51, where Our four quadrants multiplicand sub-circuit analog multiplier, Built of six pairs of cascode transistors (as shown in figure 5) : a) This multiplier is comprised of two secondary and one primary, transistors circuits. b) One input to the multiplier is differential current drain pins of the primary circuits. c) Another input to the multiplier is three input voltages - VREF, VREFP and VREFN - connected to the source pins of the multiplier transistors. d) The multiplier output is differential current outputs, connected to drain pins of the secondary circuit. e) The circuit's transistors are either NMOS or PMOS type. f) The circuit's transistors are regular transistors and Floating Gate MOS (FGMOS) transistors. g) When the circuit works with floating gate type, then it's used to compensate for process variations by applying a charge into the floating gate through a "floating gate programming" method. h) This multiplier is built with either programming compensation circuit or without it.

53) Claim as 51, where the multiplier sub-circuit (in figure 6) is built of: a) Sub-circuit generating logarithmic reference voltage relative to VREF and to the equivalent temperature potential - Ut, to allow compensation against temperature variation. b) Sub-circuit to generate a logarithmic voltage, as a function to the positive part of the differential input current, relative to a reference voltage, and also relative to Ut, to allow compensation against temperature variation. c) Sub-circuit to generate a logarithmic voltage, as a function to the negative part of the differential input current, relative to a reference voltage, and also relative to Ut, to allow compensation against temperature variation. d) Claim as 53b and 53c above, where the reference voltage is provided by a current source - and voltage source , VREF, and a MOS transistor - where its "Gate to Source voltage" (VGS) is subtracted from VREF, and VGS is derived by applying the current source over this transistor.

54) Claim as 53, where the multiplier sub-circuit is built of FG-MOS transistor for process variation and offset cancellation, by applying a charge into the floating gate, through a "floating gate programming" method. 55) Claim as 51 , where our multiplier includes FG-MOS transistors, which are used to compensate against process variations, by applying a charge into the floating gate through a "floating gate programming" method.

56) Claims as 53b and 53c, where the sub circuits are built of MOS transistors and error operational amplifiers, and generates reference voltages at the source pins of the transistors. These voltages are relative to the drain input currents.

57) Claim as 51, where our multiplier, is comprised of 11 switches, programming voltages and FG-MOS transistors, used to compensate against process variations by applying a charge into the floating gate through a "floating gate programming" method.

58) Claim as 51, where our multiplier built to be used in multipliers array circuit having: a) One, or more, multiplicand sub-circuits connected to one multiplier sub-circuits and to VREF sources. b) A circuit as in claim 57 above, which allows compensation of the multiplier transistors by floating gate programming by applying a charge into the floating gate through a "floating gate programming" method.

59) Our multiplier built to be used with plural processing with variable inputs.

60) Our multiplier built to be used with plural multipliers having the ability to perform: a) Linear and non-linear block processing. b) Filter operation. c) Channel estimation. d) Equalization. e) Frequency and timing correction in communication devices.

61) Our multiplier, which is part of discrete time analog signal processing function.

"Complete Current Mode Micro Power Divider circuit with floating gate offset cancellation"

62) Our complete analog divider comprised of three sub-circuits. The first is multiplier sub-circuit.

The second is divider cell multiplicand sub-circuit. The third is the divider cell control circuit.

63) Claim as 62, where our complete analog divider variables are represented by differential currents. 64) Claim as 62, where the multiplier & multiplicand sub-circuits are working in the subthreshold region of the transistor operation.

65) Claim as 62, where the divider cell, multiplier sub-circuit performing a multiplication between two currents, and the output is a differential current.

66) Claim as 62, where the divider cell, multiplicand sub circuit is a MOS Structure, operated in the sub Threshold region of operation, where a trans-linear operation is implemented by connecting gates of transistors together, however, supplying different voltages to their source pins, where these voltages are a logarithmic function of the result current.

67) Our complete analog divider built of FG-MOS transistor, for the purpose of process variation cancellation by applying a charge into the floating gate through a "floating gate programming" method.

68) Claim as 67, where our complete analog divider includes special circuitry for the programming of the FG-MOS transistors, for the purpose of process variation and offset cancellation by applying a charge into the floating gate through a "floating gate programming" method.

69) Claim as 66, where divider cell, multiplicand sub-circuit is based on current mirror multiplication having: a) One primary transistor sub-circuit, comprised of two branches, used as the primary part of the current mirror. b) Two secondary transistor sub-circuits, comprised of four branches, used as the secondary branches of the current mirror. c) One differential current output, flowing from the secondary branch drain pins. d) One reference voltage extraction circuit built of one transistor branch, having reference current flowing through the drain pin, and is generating reference voltage relative to Equivalent Temperature Potential (Ut) voltage and to the reference voltage VREF. e) A second output, comprised of two transistor branch, which is connected to the first said reference voltage of claim 69d. And second, to the bias voltages VREFP2, VREFN2 which are represented by the multiplication coefficient "W".

70) Claim as 62, where the divider cell control circuit, is built of four sub-circuits. The first is a common voltage sensing circuit.

The second is a differential current sensing circuit. The third is common voltage error amplifier, connected to the common voltage sensing circuit.

The fourth is differential current error amplifier.

71) Claim as 70, where divider cell control circuit, gets its input from the subtraction of the differential current between the multiplicand sub-circuit and the multiplier sub- circuit.

72) Claim as 70, where the common voltage sensing circuit is built of resistors and current source network for the two nodes of the differential current. And the outputs from the sensing network are summed and amplified by the common voltage error amplifier.

73) Claim as 70, where the differential current error amplifier, controls the two reference pins of the multiplicand sub-circuit, VREFP2 and VREFN2.

74) Claim as 70 where the differential current error amplifier has a common voltage input to control the common voltage of VREFP2 and VREFN2.

75) Claim as 70, where the differential error amplifier is built of three sub-circuits. The first is differential amplifier, consisted of differential pair transistors.

The second is common mode amplification, built of a differential pair, comparing the common mode voltage at the input to the common voltage reference, controlling the bias current of the first differential amplifier. The third is an output differential amplifier.

"Ultra Low Power (ULP) Carrier Frequency Correction for OFDM Receivers"

76) Our ULP carrier frequency correction (figure 57) comprising of: a) A digital module that calculates the corrective phase φ(i). b) A digital look up table for the calculation of corrective phase, ψ(i), sine and cosine values. c) Carrier correction module that performs phase-de-rotation on the input samples, using the corrective phase sine & cosine values. d) Two N cells current samples, one for the real part, second for the imaginary part, used for sampling and hold of the input signal.

77) Claim as 76a, where the digital module is comprised of: a) First register that holds the corrective phase radian frequency ω. b) Second register that holds the accumulated phase φ (i). c) Third, digital cyclic adder that adds the corrective phase radian frequency to the accumulated phase φ (i), every accumulation clock cycle.

78) Claim as 76b, where the look up table having one input for the corrective phase, comprised of memory capable of outputting multiple sine and cosine values,.

79) Claim as 78, where the look up table, may include a second input for phase shift, and comprised of: a) Memory unit, having one input and multiple outputs for the sine and cosine of the corrective phase. b) Cyclic adder, which calculate the address pointer for the shifted corrective phase, having two inputs. The first is, the corrective phase and the second one is, the phase shift.

80) Claim as 75c, where the carrier correction unit (figure 4) has input buses, representing the corrective phase sine and cosine values. Store control inputs that pass the sine and cosine values to a first set of register array. Update control input, which pass the values of the said first register array set to a secondary register set. Comprised of K rows by M columns array, having: a) First set of 2*K register, each with N2 bits, which hold the corrective phase sine and cosine values. b) A second set of 2*K registers, each with N2 bits, which hold the corrective phase sine and cosine values and which are connected to the DAC array inputs. c) 2*K differential DAC array, where each two, are designated to one time zone, and generate the analog representation of the corrective phase sine and cosine values. d) 2*K multiplication multiplier cells, where each pair are designated to one time zone and each multiplication multiplier array generates two reference voltages, indicating the positive and negative reference input for the multiplication multiplicand cell. e) K rows by M columns multiplication multiplicand array cells. Where the M consecutive columns cells are connected to one couple of multiplication multiplier array and M complex signal inputs.

81) Claim as 80, where the carrier correction module has a set of 2*K store control inputs, connected to the "strobes" inputs of the said first register array. And where the 2*K second register array is connected to the outputs of the said first register array, where the "strobes" control inputs of the 2^nd register array are connected to one wire, "UPDATE" input, which is used to update the 2^nd register array DAC inputs, in one cycle.

82) Claim as 80c, where the differential DAC (figure 5) is based on current steering architecture, comprised of: a) Two output pins for the output. b) N2 inputs bits, which controls the steering of the associated current. In case of "1" the current is steered to the "positive" output, in case of "0" the current is steered to the "negative" output pin.

2*Idc _/ c) N2 current sources, where the MSB current source value is 12 and

LSB current source value is /?^N2-

83) Claim as 8Od, where the multiplication multiplier cell, has three inputs and two outputs. Two inputs are the current from the associate DAC, and one input is the common voltage VREF. One output is the positive reference voltage and second output is the negative reference voltage. The cell is comprised of : a) Two log current to voltage converters, having two operational amplifier which keep the input nodes at the save voltage as the common voltage. b) Ut trans-linear extraction circuit, connected to the VREF input, which eliminates the temperature variations.

84) Claim as 80e, where the multiplication multiplicand array (figure 6) is based on current mirror multiplier circuit. Comprised of: a) Two primary transistor branches, which are used as the primary part of the current mirror multiplier. b) Four secondary transistor branches, which are used as the secondary branches of the current mirror multiplier.

85) Claim as 84, where each of the transistor branches is comprised of two P channel cascade pair, where one if Floating Gate MOS and second is regular MOS.

86) Claim as 85,86,87 where the transistors are operating in the sub-threshold region of operation.

87) Claim as 85,86,87 where each of the FGMOS (Floating Gate Metal Oxide Semiconductor Field Effect Transistor) is connected to a programming mechanism, which allows the programming of the FGMOS transistor for offset cancellation. 88) Claim as 87, where the FGMOS transistor gates are connected to a digital , serial communication channel connected to a bus (such as the JTAG standard), through switches.

89) Claim as 75d, where each of the N cells current samplers (Figure 8) is sampling differential current and is working in two phases - PHIEVEN and PHIODD. Where each cell, out of the N cells, is comprised of two current samplers sub- cells, one that sample during PHIEVEN and another that sample the current during PHIODD.

90) Claim as 88 where each of the sub cell is comprised of : a) A switch which connects the output of the sampler through operational amplifier to a capacitor, connected to a transistor gate which is used to sample the current. b) A capacitor that holds the current value. c) A transistor that its drain current is controlled by the capacitor voltage. d) A first switch which connect the said transistor to the input. e) A second switch which connect the said transistor to the output.

91) In every cell described in this patent, every P-channel group of transistors connected to supply is replaced by the same topology of N-channel transistor connected to ground and visa versa.

In this case, all currents directions are altered. An N-channel transistor sinking current is altered to a P channel transistor supplying current, and visa versa.

"Ultra Low Power (ULP) Timing Synchronization Method for Wired and Wireless Receivers"

92) Our timing synchronization method, based on phase rotation of a first reference clock by a corrective phase ( "φ" in figure 4), comprised of: a) A digital phase calculation module, with phase step (frequency) input, and corrective phase output. b) Look up table (LUT), which is connected to the said digital phase calculation corrective phase output. c) Four registers, to hold the sine and cosine of the corrective phase. d) Four to one selection array, to select one of the said four registers, used to pass one register at a time to the DAC input. e) A DAC, working at 4 times comparative to the input reference frequency. f) A low pass filter (LPF), for selecting first order harmonic and attenuate higher frequency harmonics. g) Comparator, for detecting the zero crossing point, h) Output buffer, for driving the sampling clock.

93) Claim as 92, where the input reference clock, sine and cosine wave are : a) Sampled 4 times in one cycle. b) Sampled in step interval of π/2, having reference frequency sine and cosine samples values of +1, 0 & -1, and therefore, simplifying the phase rotation operation by eliminating the need for multipliers and adder.

94) Claim as 92, where the phase rotation algorithm is implemented using a mechanism to pass the +/- sine values or +/- cosine values of the corrective phase ("φ" in figure 4) to the output. Where the sign and the selection between the corrective phase, sine and cosine value, is determined by the reference +1 or -1 clock sign of claim 93.

95) Claim as 93, when the reference clock sine and cosine values (+1,-1), are embedded in the sign of the LUT values of claim 92b.

96) Claim as 93, where the DAC of claim 92e has an input control, representing the +1 or -1 sign of the reference clock.

97) Claim as 92b, where the LUT includes a "control mechanism" to generate an arbitrary constant phase shift, to adjust the sampling phase.

98) Claim as 97, where the control mechanism is implemented using a binary adder, having two inputs. The first, for the corrective phase "φ". The second, for the constant phase shift "ω*TS".

99) Claim as 92e, where the DAC, is implemented using capacitive DAC, for the purpose of power reduction.

100) Claim as 92f, where the LPF is implemented using a simple first order RC filter.