KR102608022B1 - Data receiving circuit, data receiving system and storage device - Google Patents

Abstract

A data receiving circuit, a data receiving system, and a storage device are disclosed. A data reception circuit according to an embodiment of the present invention includes a first amplification module and a second amplification module. The first amplification module includes an amplification unit including a first node, a second node, a third node, and a fourth node; A first NMOS transistor, one end of which is connected to the first node; a second NMOS transistor having one end connected to the other end of the first NMOS transistor and the other end connected to a second node; A third NMOS transistor, one end of which is connected to a third node; and a fourth NMOS transistor, one end of which is connected to the other end of the third NMOS transistor and the other end of which is connected to the fourth node, wherein one gate of the first NMOS transistor and the second NMOS transistor has a first feedback signal and a level. A first complementary feedback signal that is opposite to each other is received, an enable signal is received at the other gate, and a second feedback signal whose level is opposite to the second feedback signal is received at the gate of one of the third and fourth NMOS transistors. A complementary feedback signal is received, and an enable signal is received at the other gate. Embodiments of the present invention can improve the processing speed of data signals while improving the reception performance of the data reception circuit.

Description

Data receiving circuit, data receiving system and storage device

Embodiments of the present invention relate to semiconductor technology, and particularly to data reception circuits, data reception systems, and storage devices.

This application claims priority to Chinese Patent Application No. 202210787529.7, filed on July 4, 2022, titled “Data Receiving Circuit, Data Receiving System and Storage Device,” the entire disclosure of which is incorporated into the present invention. do.

As signal transmission speeds increase day by day in memory applications, channel loss has a greater impact on signal quality, which can easily cause inter-symbol interference. In addition, the difference in level value between the data signal received by the data receiving circuit of the memory and the reference signal affects the data receiving circuit's judgment regarding the data signal, thereby affecting the accuracy of the signal output from the data receiving circuit.

Currently, channels are typically compensated using equalization circuits. The equalization circuit may be selected from a Continuous Time Linear Equalizer (CTLE) or a Decision Feedback Equalizer (DFE). However, the accuracy of the signal output from the current equalization circuit and the reception performance of the equalization circuit must be improved, and power consumption must be reduced.

Embodiments of the present invention are intended to provide a data reception circuit, a data reception system, and a storage device that can improve the processing speed of data signals along with improving the reception performance of the data reception circuit.

According to some embodiments of the present invention, the data receiving circuit of the embodiment of the present invention receives an enable signal, a first feedback signal, a second feedback signal, a data signal, a first reference signal, and a second reference signal, and the In a section where the enable signal has a first level value, respond to a sampling clock signal, select the data signal and the first reference signal based on the first feedback signal, perform a first comparison, and the result of the first comparison output a first signal pair, or select the data signal and the second reference signal in response to the sampling clock signal and based on the second feedback signal, perform a second comparison, and as a result of the second comparison Outputting two signal pairs, performing the first comparison in response to the sampling clock signal in a section where the enable signal has a second level value, and outputting a first signal pair, the first feedback signal and the first a first amplification module wherein the levels of two feedback signals are opposite to each other, the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal; and a second amplification module that receives the output signal of the first amplification module as an input signal pair, amplifies the voltage difference between the input signal pair, and outputs a first output signal and a second output signal as a result of the amplification process. ; wherein the first amplification module includes a first node, a second node, a third node, and a fourth node, the first node outputs the first signal, and the second node outputs the first signal. Outputs a second signal, the third node outputs the third signal, the fourth node outputs the fourth signal, and receives the data signal, the first reference signal, and the second reference signal. an amplifying unit; a first NMOS transistor whose end is connected to the first node; a second NMOS transistor having one end connected to the other end of the first NMOS transistor and the other end connected to the second node; a third NMOS transistor, one end of which is connected to the third node; and a fourth NMOS transistor, one end of which is connected to the other end of the third NMOS transistor and the other end of which is connected to the fourth node, wherein the gate of one of the first NMOS transistor and the second NMOS transistor includes the first NMOS transistor. A first complementary feedback signal whose level is opposite to that of the feedback signal is received, the enable signal is received at the other gate, and the second feedback signal is received at the gate of one of the third NMOS transistor and the fourth NMOS transistor. A second complementary feedback signal whose signal and level are opposite to each other is received, and the enable signal is received at the other gate.

In some embodiments, the first amplification module includes a fifth NMOS transistor, one end of which is connected to the first node; and a sixth NMOS transistor, one end of which is connected to the other end of the fifth NMOS transistor and the other end of which is connected to the second node, wherein the gate of one of the fifth NMOS transistor and the sixth NMOS transistor is connected to the second node. 1 A complementary feedback signal is received, and the enable signal is received at the other gate.

In some embodiments, the enable signal is received at the gate of the first NMOS transistor, the first complementary feedback signal is received at the gate of the second NMOS transistor, and the channel width of the first NMOS transistor is the first. 2 greater than the channel width of the NMOS transistor, the first complementary feedback signal is received at the gate of the fifth NMOS transistor, the enable signal is received at the gate of the sixth NMOS transistor, and the channel of the fifth NMOS transistor is The width is smaller than the channel width of the sixth NMOS transistor.

In some embodiments, the channel width of the fifth NMOS transistor is the same as the channel width of the second NMOS transistor, the channel width of the sixth NMOS transistor is the same as the channel width of the first NMOS transistor, and the first The channel length of the NMOS transistor, the channel length of the second NMOS transistor, the channel length of the fifth NMOS transistor, and the channel length of the sixth NMOS transistor are the same.

In some embodiments, the first amplification module includes a seventh NMOS transistor, one end of which is connected to the third node; and an eighth NMOS transistor having one end connected to the other end of the seventh NMOS transistor and the other end connected to the fourth node, wherein the gate of one of the seventh NMOS transistor and the eighth NMOS transistor is connected to the second node. A complementary feedback signal is received, and the enable signal is received at the other gate.

In some embodiments, the enable signal is received at the gate of the third NMOS transistor, the second complementary feedback signal is received at the gate of the fourth NMOS transistor, and the channel width of the third NMOS transistor is the first. greater than the channel width of the 4 NMOS transistor, the second complementary feedback signal is received at the gate of the seventh NMOS transistor, the enable signal is received at the gate of the eighth NMOS transistor, and the channel of the seventh NMOS transistor is The width is smaller than the channel width of the eighth NMOS transistor.

In some embodiments, the channel width of the seventh NMOS transistor is the same as the channel width of the fourth NMOS transistor, the channel width of the eighth NMOS transistor is the same as the channel width of the third NMOS transistor, and the third The channel length of the NMOS transistor, the channel length of the fourth NMOS transistor, the channel length of the seventh NMOS transistor, and the channel length of the eighth NMOS transistor are the same.

In some embodiments, the sampling clock signal includes a first sampling clock signal and a second sampling clock signal, the amplifier includes the first node and the second node, and the data signal and the first reference a first comparison circuit that receives a signal and performs the first comparison in response to the first sampling clock signal; Receives the enable signal and the raw sampling clock signal and outputs the second sampling clock signal, and in a section where the enable signal has the first level value, the phase of the second sampling clock signal and the raw sampling clock signal A clock generation circuit where the phases are opposite to each other and the second sampling clock signal is a logic high level signal in a section where the enable signal has the second level value; and the third node and the fourth node, receiving the data signal and the second reference signal, and responding to the second sampling clock signal in a section where the enable signal has the first level value. Performing a second comparison, wherein the connection path between the third node and the ground terminal and the connection path between the fourth node and the ground terminal are conducted in a section where the enable signal has the second level value. circuit; includes.

In some embodiments, the first comparison circuit includes: a first current source connected between a power node and a fifth node and supplying current to the fifth node in response to the first sampling clock signal; It is connected to the first node, the second node, and the fifth node, receives the data signal and the first reference signal, and makes the first comparison when the first current source supplies current to the fifth node. a first comparison unit that performs and outputs the first signal and the second signal; and a first reset unit connected to the first node and the second node and resetting the first node and the second node in response to the first sampling clock signal, wherein the second comparison circuit is , a second current source connected between the power node and the sixth node and supplying current to the sixth node in response to the second sampling clock signal: connected to the third node, the fourth node, and the sixth node A device that receives the data signal and the second reference signal, performs the second comparison when the second current source supplies current to the sixth node, and outputs the third signal and the fourth signal. 2 comparison section; and a second reset unit connected between the third node and the fourth node and resetting the third node and the fourth node in response to the second sampling clock signal.

In some embodiments, the first current source includes a first PMOS transistor connected between the power node and the fifth node and receiving the first sampling clock signal as a gate, and the second current source includes: It includes a second PMOS transistor connected between a power node and the sixth node and receiving the second sampling clock signal through a gate.

In some embodiments, the first comparison unit may include a third PMOS transistor connected between the first node and the fifth node and receiving the data signal through a gate; and a fourth PMOS transistor connected between the second node and the fifth node and receiving the first reference signal as a gate, wherein the second comparison unit is connected between the third node and the sixth node. A fifth PMOS transistor is connected and receives the data signal through its gate; and a sixth PMOS transistor connected between the fourth node and the sixth node and receiving the second reference signal through a gate.

In some embodiments, the first reset unit may include a ninth NMOS transistor connected between the first node and a ground terminal and receiving the first sampling clock signal as a gate; and a tenth NMOS transistor connected between the second node and the ground terminal and receiving the first sampling clock signal as a gate, wherein the second reset unit is connected between the third node and the ground terminal. An 11th NMOS transistor whose gate receives the second sampling clock signal; and a twelfth NMOS transistor connected between the fourth node and the ground terminal and receiving the second sampling clock signal through a gate.

In some embodiments, the clock generation circuit includes a first NAND gate circuit that receives the raw sampling clock signal at one input terminal, has another input terminal connected to a power node, and outputs the first sampling clock signal at an output terminal. do.

In some embodiments, the clock generation circuit includes a second NAND gate circuit that receives the raw sampling clock signal through one input terminal, receives the enable signal through another input terminal, and outputs the second sampling clock signal through an output terminal; Includes.

In some embodiments, the second amplification module is connected to a seventh node and an eighth node, receives the first signal pair, performs a third comparison, and results in the seventh node and the eighth node as a result of the third comparison. a first input unit providing signals to each of the eighth nodes; Connected to the seventh node and the eighth node, receiving the second signal pair, performing a fourth comparison, and providing signals to the seventh node and the eighth node as a result of the fourth comparison, respectively. second input unit; and is connected to the seventh node and the eighth node, amplifies and latches the signal of the seventh node and the signal of the eighth node, and outputs the first output signal through the first output node and the second output node, respectively. and a latch unit that outputs the second output signal.

In some embodiments, the first input unit may include a thirteenth NMOS transistor whose drain is connected to the seventh node, whose source is connected to a ground terminal, and whose gate receives the first signal; and a 14th NMOS transistor whose drain is connected to the eighth node, whose source is connected to the ground terminal, and whose gate receives the second signal, wherein the second input unit has a drain connected to the seventh node. A 15th NMOS transistor whose source is connected to the ground terminal and whose gate receives the third signal; and a 16th NMOS transistor whose drain is connected to the eighth node, whose source is connected to the ground terminal, and whose gate receives the fourth signal.

In some embodiments, the latch unit may include a seventeenth NMOS transistor whose source is connected to the seventh node, whose drain is connected to the first output node, and whose gate is connected to the second output node; a seventh PMOS transistor whose source is connected to a power node, a drain connected to the first output node, and a gate connected to the second output node; an 18th NMOS transistor whose source is connected to the eighth node, a drain connected to the second output node, and a gate connected to the first output node; and an eighth PMOS transistor whose source is connected to the power node, whose drain is connected to the second output node, and whose gate is connected to the first output node.

In some embodiments, the second amplification module further includes a third reset unit connected between a power node and an output terminal of the latch unit and resetting the output terminal of the latch unit.

In some embodiments, the third reset unit may include a 139 PMOS transistor connected between the first output node and a power node and receiving a raw sampling clock signal as a gate; and a 14th PMOS transistor connected between the second output node and the power node and receiving the raw sampling clock signal through a gate.

In some embodiments, a first inverting circuit that receives the first feedback signal and outputs the first complementary feedback signal; and a second inverting circuit that receives the second feedback signal and outputs the second complementary feedback signal.

In some embodiments, the first inverting circuit includes a first inverter, and the second inverting circuit includes a second inverter.

In some embodiments, the first inverting circuit includes a third NAND gate that receives the first feedback signal and the enable signal through both input terminals and outputs the first complementary feedback signal to an output terminal, The second inverting circuit includes a fourth NAND gate that receives the second feedback signal and the enable signal through both input terminals and outputs the second complementary feedback signal to an output terminal.

According to some embodiments of the present invention, the data receiving system of the embodiment of the present invention includes one of the data receiving circuits described above and a latch circuit connected to the data receiving circuit, and transmits a plurality of data connected in cascade. circuit; wherein the output signal of the data transfer circuit of the previous stage is the feedback signal of the data transfer circuit of the next stage, and the output signal of the data transfer circuit of the last stage is the feedback signal of the data transfer circuit of the first stage. It is a feedback signal.

In some embodiments, the data receiving circuit receives data in response to the sampling clock signal, and the data receiving system includes four data receiving circuits connected in cascade, and the data receiving circuit is adjacent to each other. The phase difference of the sampling clock signal is 90°.

In some embodiments, the first output signal and the second output signal output by the second amplification module of the data transmission circuit of the previous stage are the feedback signals of the data transmission circuit of the next stage, or the latch of the previous stage The signal output by the circuit is the feedback signal of the data transmission circuit of the next stage.

According to some embodiments of the present invention, a storage device of an embodiment of the present invention includes a plurality of data ports; and a plurality of any one of the above-described data reception systems, each corresponding to the data port.

The technical solution according to the embodiments of the present invention has the following advantages.

While the first amplification module receives the data signal, the first reference signal, and the second reference signal, it receives an enable signal and a first complementary feedback signal through the first NMOS transistor and the second NMOS transistor to generate the first node and the second node. The potentials of the nodes are controlled, and the potentials of the third and fourth nodes are controlled by receiving an enable signal and a second complementary feedback signal through the third NMOS transistor and the fourth NMOS transistor. Specifically, in a section where the enable signal has a first level value, one of the first NMOS transistor and the second NMOS transistor and one of the third NMOS transistor and the fourth NMOS transistor are turned on based on the enable signal. . The other one of the first NMOS transistor and the second NMOS transistor is turned on or off in response to the first complementary feedback signal, and the other one of the third NMOS transistor and the fourth NMOS transistor is responsive to the second complementary feedback signal. It is turned on or turned off. Since the level of the first feedback signal is opposite to the level of the second feedback signal, the level of the first complementary feedback signal is opposite to the level of the first feedback signal, and the level of the second complementary feedback signal is equal to that of the first feedback signal. Therefore, the level of the first complementary feedback signal is opposite to the level of the second complementary feedback signal. In a section where the enable signal has a first level value, one of the remaining one of the first NMOS transistor and the second NMOS transistor and the remaining one of the third NMOS transistor and the fourth NMOS transistor is turned on and the other is turned on. -It turns off. Accordingly, the first amplification module selectively performs the first comparison or the second comparison in response to the sampling clock signal, and one of the output first and second signal pairs is valid and the other is not valid. . Therefore, the influence of inter-symbol interference of the received data signal on the data receiving circuit can be reduced, and since the first amplification module performs one of the first comparison and the second comparison and the other does not operate, the data receiving circuit Power consumption can be reduced. In addition, because the on-resistance of the NMOS transistor is much smaller than that of the PMOS transistor under the same conditions, compared with the PMOS transistor, the first NMOS transistor, second NMOS transistor, third NMOS transistor, and fourth NMOS of the first amplification module The transistor may be turned on or off more quickly in response to the signal received at each gate, making it easier for the first amplification module to perform only one of the first comparison and the second comparison at the same time. Accordingly, the data signal processing effect and processing speed of the first amplification module can be improved. In this way, the reception performance of the data reception circuit can be improved and the processing speed of the data signal can be improved.

Additionally, in a section where the enable signal has a second level value, the first amplification module performs only the first comparison in response to the sampling clock signal and outputs a fixedly valid first signal pair. Since the circuit for outputting the second signal pair from the first amplification module does not operate, power consumption of the data reception circuit can be further reduced.

One or more embodiments are illustratively described through the accompanying drawings, and the embodiments are not limited by these examples. Components with the same reference numerals in the drawings are similar components, and unless otherwise specified, the proportions in the accompanying drawings are not limited. Hereinafter, in order to explain the embodiments of the present invention or the technical content of the prior art in more detail, drawings for the embodiments will be briefly described. The drawings attached below are only some embodiments of the present invention, and it is obvious that a person skilled in the art can draw drawings for other embodiments without creative efforts.
1 is a block diagram showing the function of a data reception circuit according to an embodiment of the present invention.
Figure 2 is a block diagram showing other functions of a data reception circuit according to an embodiment of the present invention.
Figure 3 is a block diagram showing the function of the first amplification module of the data reception circuit according to an embodiment of the present invention.
Figure 4 is a block diagram showing another function of a data reception circuit according to an embodiment of the present invention.
5 and 6 are diagrams schematically showing the circuit structures of the first amplification module and the second amplification module of the data reception circuit according to an embodiment of the present invention.
Figure 7 is a diagram schematically showing the circuit structure of the second amplification module of the data reception circuit according to an embodiment of the present invention.
Figure 8 is a diagram schematically showing the circuit structures of the second amplifying module, the first inverting circuit, and the third inverting circuit of the data receiving circuit according to an embodiment of the present invention.
Figure 9 is a block diagram showing the function of a data reception system according to an embodiment of the present invention.

A data reception circuit, a data reception system, and a storage device according to an embodiment of the present invention are disclosed. The data receiving circuit uses the enable signal, the first feedback signal, and the second feedback signal and selects whether to consider the influence of the inter-symbol interference of the data received by the data receiving circuit on the data receiving circuit, and generates the first amplifying module. Additional control can be performed. For example, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit, that is, in the period where the enable signal has the first level value, the first amplification module responds to the sampling clock signal and the first NMOS One of the first comparison and the second comparison is selected and performed using the transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor. Accordingly, one of the first signal pair and the second signal pair may be output validly, and the other may be output invalidly. Furthermore, because the difference in level values between signals of a valid signal pair is large, the second amplification module receives a differential signal pair with a larger difference in level values between signals. In addition, the low on-resistance of the NMOS transistor prevents the first amplification module from performing the first comparison and the second comparison simultaneously and can improve the processing effect and processing speed of the data signal by the first amplification module. . When the effect of inter-symbol interference on the data receiving circuit is not considered, the enable signal is in the second level value section, and the first amplification module performs only the first comparison in response to the sampling clock signal to generate a valid first signal. By outputting pairs fixedly, the power consumption of the data receiving circuit can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that numerous technical details are provided herein to facilitate understanding of embodiments of the present invention. However, the technology to be protected in the embodiments of the present invention may be implemented without various changes and modifications based on these technical details and the following embodiments.

One embodiment of the present invention relates to a data reception circuit. Hereinafter, a data reception circuit according to an embodiment of the present invention will be described with reference to the attached drawings. 1 is a block diagram showing the function of a data reception circuit according to an embodiment of the present invention. Figure 2 is a block diagram showing other functions of a data reception circuit according to an embodiment of the present invention. Figure 3 is a block diagram showing the function of the first amplification module of the data reception circuit according to an embodiment of the present invention. Figure 4 is a block diagram showing another function of a data reception circuit according to an embodiment of the present invention. 5 and 6 are diagrams schematically showing the circuit structures of the first amplification module and the second amplification module of the data reception circuit according to an embodiment of the present invention. Figure 7 is a diagram schematically showing the circuit structure of the second amplification module of the data reception circuit according to an embodiment of the present invention. Figure 8 is a diagram schematically showing the circuit structures of the second amplifying module, the first inverting circuit, and the third inverting circuit of the data receiving circuit according to an embodiment of the present invention.

Referring to FIG. 1, the data reception circuit 100 may include a first amplification module 101. The first amplification module 101 includes an enable signal (EnDfe), a first feedback signal (fbp), a second feedback signal (fbn), a data signal (DQ), a first reference signal (VR+), and a second reference signal ( VR-) is received. The first amplification module 101 responds to the sampling clock signal clkN in a section where the enable signal EnDfe has a first level value and generates the data signal DQ and A first comparison is performed by selecting the first reference signal (VR+), and a first signal pair is output as a first comparison result. Alternatively, the first amplification module 101 responds to the sampling clock signal (clkN) and selects the data signal (DQ) and the second reference signal (VR-) based on the second feedback signal (fbn) to perform the second comparison. and output a second signal pair as a second comparison result. The first amplification module 102 performs a first comparison in response to the sampling clock signal clkN and outputs a first signal pair in a section where the enable signal EnDfe has a second level value. The levels of the first feedback signal (fbp) and the second feedback signal (fbn) are opposite to each other. The first signal pair includes a first signal (Sn+) and a second signal (Sp+), and the second signal pair includes a third signal (Sn-) and a fourth signal (Sp-).

Continuing to refer to FIG. 1, the first amplification module 101 includes an amplification unit 131, a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), and a fourth NMOS transistor. Includes (MN4). The amplifier 131 includes a first node (net1), a second node (net2), a third node (net3), and a fourth node (net4). A first signal (Sn+) is output from the first node (net1), and a second signal (Sp+) is output from the second node (net2). A third signal (Sn-) is output from the third node (net3), and a fourth signal (Sp-) is output from the fourth node (net4). The amplifier 131 receives the data signal (DQ), the first reference signal (VR+), and the second reference signal (VR-). One end of the first NMOS transistor (MN1) is connected to the first node (net1). The second NMOS transistor MN2 has one end connected to the other end of the first NMOS transistor MN1 and the other end connected to the second node net2. One end of the third NMOS transistor (MN3) is connected to the third node (net3). One end of the fourth NMOS transistor (MN4) is connected to the other end of the third NMOS transistor (MN3) and the other end is connected to the fourth node (net4). A first complementary feedback signal (fbpN) whose level is opposite to that of the first feedback signal (fbp) is received at the gate of one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), and at the other gate, An enable signal (EnDfe) is received. A second complementary feedback signal (fbnN) whose level is opposite to that of the second feedback signal (fbn) is received at the gate of one of the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4), and at the other gate, An enable signal (EnDfe) is received. The second amplification module 102 receives the output signal of the first amplification module 101 as an input signal pair, amplifies the voltage difference between the input signal pair, and provides a first output signal (Vout) and a second output signal (VoutN). ) is output as the result of amplification processing.

For reference, the section in which the enable signal (EnDfe) is the first level value is the section in which the first amplification module 101 determines that the enable signal (EnDfe) is in the level value range of logic level 1, that is, a high level. means. The section in which the enable signal (EnDfe) has a second level value refers to the section in which the first amplification module 101 determines that the enable signal (EnDfe) is in the level value range of logic level 0, that is, at a low level. it means. In addition, the levels of the first feedback signal (fbp) and the second feedback signal (fbn) are opposite to each other, meaning that when one of the first feedback signal (fbp) and the second feedback signal (fbn) is at a high level, the other is at a high level. Indicates low level. The fact that the levels of the first complementary feedback signal (fbpN) and the first feedback signal (fbp) are opposite to each other means that when one of the first complementary feedback signal (fbpN) and the first feedback signal (fbp) is at a high level, the other one is at a high level. Indicates low level. That the levels of the second complementary feedback signal (fbnN) and the second feedback signal (fbn) are opposite to each other means that when one of the second complementary feedback signal (fbnN) and the second feedback signal (fbn) is at a high level, the other is at a high level. Indicates low level. In this way, the first complementary feedback signal (fbpN) and the second complementary feedback signal (fbnN) are opposite to each other.

In this way, when the influence of inter-symbol interference on the data receiving circuit 100 needs to be reduced, the first signal is used in the section where the enable signal EnDfe has the first level value, that is, when the enable signal EnDfe is logic level 1. One of the 1 NMOS transistor (MN1) and the second NMOS transistor (MN2), and one of the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) are turned on based on the enable signal (EnDfe). Additionally, the other of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is turned on or off in response to the first complementary feedback signal (fbpN), and the third NMOS transistor (MN3) and the second NMOS transistor (MN3) are turned on or off. Another one of the four NMOS transistors (MN4) is turned on or off in response to the second complementary feedback signal (fbnN). When one of the first complementary feedback signal (fbpN) and the second complementary feedback signal (fbnN) is at a high level, the other is at a low level, so the other one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) One of the third NMOS transistors MN3 and the fourth NMOS transistor MN4 is turned on and the other transistor is turned off. Accordingly, the first amplification module 101 can selectively perform the first comparison or the second comparison in response to the sampling clock signal clkN, and one of the output first signal pair and the second signal pair is valid. and the other becomes invalid, and the influence of inter-symbol interference of the received data signal on the data reception circuit 100 can be reduced. In addition, since only one of the circuit performing the first comparison and the circuit performing the second comparison in the first amplification module 101 is in an operating state and the other is in an inactive state, the power consumption of the data receiving circuit 100 is reduced. can be reduced. At this time, based on the enable signal (EnDfe), the first feedback signal (fbp), and the second feedback signal (fbn), the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are connected to the first node (net1). and the second node (net2), or the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) conduct the connection path between the third node (net3) and the fourth node (net4). Make it conductive. Since the two nodes in the conductive path cannot output a valid signal pair, the amplifier 131 selectively performs the first comparison or the second comparison.

In addition, since the on-resistance of the NMOS transistor is much smaller than the on-resistance of the PMOS transistor under the same conditions, compared to the PMOS transistor, the first NMOS transistor (MN1) and the second NMOS transistor (MN2) of the first amplifier module 101 And the third NMOS transistor MN3 and fourth NMOS transistor MN4 are turned on or off faster in response to signals received through their respective gates. This facilitates the first amplification module 101 to perform only either the first comparison or the second comparison at the same time, so that the processing effect and processing speed of the data signal DQ of the first amplification module 101 are It improves. In this way, the reception performance of the data reception circuit 100 can be improved and the processing speed of the data signal DQ can be improved.

In a section where the enable signal (EnDfe) has a first level value, the first amplification module 101 selectively performs the first comparison or the second comparison, so that the first amplification module 101 selects an effective first signal pair. Or output a second signal pair. At this time, the other can be understood as being invalid. That the first signal pair is valid means that the difference between the level value of the first signal (Sn+) and the level value of the second signal (Sp+) of the first signal pair is large to a certain degree, and that the second signal pair is valid means that the level value of the first signal (Sn+) of the first signal pair is large to a certain extent. This means that the difference between the level value of the third signal (Sn-) and the level value of the fourth signal (Sp-) is large to a certain extent. In this way, the second amplification module 102 receives a pair of differential signals with a large difference in signal level values, so that the influence of inter-symbol interference of the received data signal DQ on the data reception circuit 100 is reduced. It decreases.

In addition, when the influence of inter-symbol interference on the data reception circuit 100 is not considered, in the section where the enable signal EnDfe has a second level value, that is, when it is logic level 0, this enable signal (EnDfe) Based on EnDfe), one of the first NMOS transistor MN1 and the second NMOS transistor MN2 is turned off, and the connection path between the first node net1 and the second node net2 is disconnected. In addition, one of the third node (net3) and the fourth NMOS transistor (MN4) is turned off, and the connection path between the third node (net3) and the fourth node (net4) is disconnected, and the amplification unit 131 performs only the first comparison through its own control. In addition, the first NMOS transistor (MN1), the second NMOS transistor (MN2), the third NMOS transistor (MN3), and the fourth NMOS transistor (MN4) are all integrated into the first amplification module 101, and the data reception circuit ( 100) The overall layout area can be further reduced.

At this time, the case where inter-symbol interference must be considered is generally when the data signal (DQ) received by the data reception circuit 100 is high-speed data, that is, when the data transmission rate is very high. A case in which there is no need to consider inter-symbol interference is when the data signal DQ received by the data reception circuit 100 is generally low-speed data, that is, when the data transmission rate is relatively low.

In some embodiments, the level value of the first reference signal (VR+) is different from the level value of the second reference signal (VR-), so that for the data signal (DQ) having a different level value, the data signal (DQ) and the second reference signal (VR-) are different. The difference between the level values of either the first reference signal (VR+) or the second reference signal (VR-) may become larger. When the first amplification module 101 can perform the first comparison and the second comparison simultaneously, the first amplification module 101 can output a signal pair with a larger difference in level values. In one embodiment of the present invention, when inter-symbol interference exists in the data signal (DQ) received by the data reception circuit 100, the first amplification module 101 generates the first feedback signal (fbp) and the second The first comparison or the second comparison can be selectively performed based on the feedback signal (fbn). One of the first signal pair and the second signal pair output by the first amplification module 101 is valid and the other is invalid. Since a valid signal pair is a signal pair in which the difference in level values is greater when the first comparison and the second comparison are performed simultaneously, the effect of inter-symbol interference of the received data signal DQ on the data reception circuit 100 is low. can be reduced. In a section where the enable signal (EnDfe) has a first level value, the first amplification module 101 processes the data signal (DQ) based on the received first feedback signal (fbp) and the second feedback signal (fbn). A more desirable comparison method can be selectively performed. That is, by selectively performing the first comparison or the second comparison, a more desirable signal pair can be obtained. As such, in the section where the enable signal EnDfe has the first level value, the first amplification module 101 performs the more desirable one of the first comparison and the second comparison while the other is not operated. Therefore, the power consumption of the data receiving circuit can be reduced.

In addition, in the section where the enable signal (EnDfe) has a second level value, regardless of the change in the level values of the first feedback signal (fbp) and the second feedback signal (fbn) obtained based on previously received data, , At this time, the first amplification module 101 constantly performs the first comparison based on the enable signal (EnDfe). That is, at this time, the first amplification module 101 steadily outputs a valid first signal pair. At this time, the first amplification module 101 does not perform the second comparison. That is, the circuit for outputting the second signal pair from the first amplification module 101 is in a non-operating state, which is advantageous in further reducing power consumption of the data receiving circuit.

How the data reception circuit 100 reduces the influence of inter-symbol interference of the received data signal DQ on the data reception circuit 100 will be described in detail below through specific examples.

In some embodiments, if the level value of the first reference signal (VR+) is greater than the level value of the second reference signal (VR-), and the data signal (DQ) is at a low level and the data receiving circuit 100 receives the data When inter-symbol interference exists in the signal DQ, in a section where the enable signal EnDfe has the first level value, the first amplification module 101 generates the enable signal EnDfe and the first feedback. A first comparison is performed based on the signal fbp and the second feedback signal fbn. That is, the first amplification module 101 outputs a valid first signal pair. At this time, the level value difference between the data signal (DQ) and the first reference signal (VR+) is greater than the level value difference between the data signal (DQ) and the second reference signal (VR-), so that performing the first comparison is performed by the second reference signal (VR+). It is possible to produce pairs of output signals with greater differences in level values than performing a comparison. The second amplification module 102 may receive a valid first signal pair and output a first output signal (Vout) and a second output signal (VoutN) with improved accuracy. Accordingly, the influence of inter-symbol interference of the received data signal DQ on the data receiving circuit 100 can be reduced.

In addition, when the data signal DQ is at a high level and there is inter-symbol interference of the data signal DQ received by the data receiving circuit 100, a section in which the enable signal EnDfe has the first level value In , the first amplification module 101 performs the second comparison based on the enable signal (EnDfe), the first feedback signal (fbp), and the second feedback signal (fbn) at this time. That is, the first amplification module 101 outputs a valid second signal pair. At this time, since the level value difference between the data signal (DQ) and the first reference signal (VR+) is smaller than the level value difference between the data signal (DQ) and the second reference signal (VR-), it is best to perform the second comparison. It is possible to produce pairs of output signals with larger differences in level values than performing a 1 comparison. The second amplification module 102 may receive a valid second signal pair and output a first output signal (Vout) and a second output signal (VoutN) with improved accuracy. Accordingly, the influence of inter-symbol interference of the received data signal DQ on the data receiving circuit 100 can be reduced.

In actual application, the level value of the first reference signal (VR+) may also be smaller than the level value of the second reference signal (VR-).

At this time, Figure 1 shows that an enable signal (EnDfe) is received at the gate of the first NMOS transistor (MN1) and the gate of the third NMOS transistor (MN3), and a first complementary feedback signal is received at the gate of the second NMOS transistor (MN2). (fbpN) is received, and the second complementary feedback signal (fbnN) is received at the gate of the fourth NMOS transistor (MN4). In actual application, the gate of the first NMOS transistor (MN1) may also receive the first complementary feedback signal (fbpN), and the gate of the third NMOS transistor (MN3) may also receive the second complementary feedback signal (fbnN). In addition, the gate of the second NMOS transistor MN2 and the gate of the fourth NMOS transistor MN4 may also receive the enable signal EnDfe.

Referring to FIG. 2, in some embodiments, the first amplification module 101 further includes a fifth NMOS transistor (MN5) and a sixth NMOS in addition to the first NMOS transistor (MN1) and the second NMOS transistor (MN2). can do. One end of the fifth NMOS transistor (MN5) is connected to the first node (net1). One end of the sixth NMOS transistor MN6 is connected to the other end of the fifth NMOS transistor MN5 and the other end is connected to the second node net2. A first complementary feedback signal (fbpN) is received at the gate of one of the fifth NMOS transistor (MN5) and the sixth NMOS transistor (MN6), and an enable signal (EnDfe) is received at the other gate.

The branch formed by the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 is in parallel with the branch formed by the first NMOS transistor MN1 and the second NMOS transistor MN2. In this way, when the connection path is conducted between the first node (net1) and the second node (net2), the total path resistance of the connection path between the first node (net1) and the second node (net2) is reduced, and the first node (net1) is connected to the second node (net2). The speed at which the connection path between (net1) and the second node (net2) is conducted in response to the enable signal (EnDfe) and the first complementary feedback signal (fbpN) may be improved.

In some embodiments, the channel width-to-length ratio of the transistor receiving the enable signal EnDfe among the first NMOS transistor MN1 and the second NMOS transistor MN2 is greater than the channel width-to-length ratio of the other one, Among the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6, the channel width-to-length ratio of the transistor receiving the enable signal EnDfe is greater than the channel width-to-length ratio of the other one.

At this time, when the level value of the signal received at the gate of the NMOS transistor changes frequently, the larger the channel width of the NMOS transistor, the larger the gate capacitance, and thus the sensitivity to changes in the level value of the signal detected by the gate decreases. Therefore, in the case of an NMOS transistor whose gate reception level value changes frequently, reducing the channel width of the NMOS transistor is advantageous in reducing the effect of its gate capacitance on the NMOS transistor. In this way, the level value of the enable signal (EnDfe) is fixed in the section where the enable signal (EnDfe) has the first level value, and the first NMOS transistor (MN1), the second NMOS transistor (MN2), and the fifth NMOS transistor In the case of the (MN5) and sixth NMOS transistors (MN6), the gate capacitance of the two NMOS transistors receiving the enable signal (EnDfe) does not have a significant effect on the data receiving circuit 100. At this time, since the level value of the first complementary feedback signal (fbpN) continues to change frequently, the effect of the gate capacitance on the NMOS transistors is that the channel width of the two NMOS transistors receiving the first complementary feedback signal (fbpN) is smaller. It is advantageous to reduce

Additionally, the larger the ratio between the channel width and length of the NMOS transistor, the smaller the on-resistance and the faster the turn-on or turn-off switching speed. In a state where the channel width of the two NMOS transistors receiving the first complementary feedback signal (fbpN) is relatively small, the ratio of the channel width and length of the two NMOS transistors receiving the enable signal (EnDfe) becomes relatively large. , the total on-resistance of the connection path between the first node (net1) and the second node (net2) can be reduced. Therefore, when comprehensively considering the two factors of the gate capacitance and on-resistance of the NMOS transistor, two NMOS transistors receiving the first complementary feedback signal (fbpN) in the section where the enable signal (EnDfe) has the first level value By doing so, a change in the level value of the first complementary feedback signal (fbpN) can be sensitively detected, and the speed of conducting or disconnecting the connection path between the first node (net1) and the second node (net2) can be increased. .

Continuing to refer to FIG. 2 , in one example, an enable signal (EnDfe) is received at the gate of the first NMOS transistor (MN1), and a first complementary feedback signal (fbpN) is received at the gate of the second NMOS transistor (MN2). is received. The channel width of the first NMOS transistor (MN1) is larger than the channel width of the second NMOS transistor (MN2), so that the ratio of the channel width and length of the first NMOS transistor (MN1) receiving the enable signal (EnDfe) is complementary to the first NMOS transistor (MN1). It can be greater than the ratio of the channel width and length of the second NMOS transistor (MN2) receiving the feedback signal (fbpN). Additionally, the first complementary feedback signal (fbpN) is received at the gate of the fifth NMOS transistor (MN5), and the enable signal (EnDfe) is received at the gate of the sixth NMOS transistor (MN6). The channel width of the fifth NMOS transistor (MN5) is smaller than that of the sixth NMOS transistor (MN6), so that the ratio of the channel width and length of the sixth NMOS transistor (MN6) receiving the enable signal (EnDfe) is complementary to the first channel width. It can be larger than the ratio of the channel width and length of the fifth NMOS transistor (MN5) that receives the feedback signal (fbpN).

2 shows that an enable signal (EnDfe) is received at the gate of the first NMOS transistor (MN1) and the gate of the sixth NMOS transistor (MN6), and the gate of the second NMOS transistor (MN2) and the fifth NMOS transistor (MN5) are received. An example is shown in which the first complementary feedback signal (fbpN) is received through the gate of . In actual application, the gate of the first NMOS transistor (MN1) and the gate of the sixth NMOS transistor (MN6) may also receive the first complementary feedback signal (fbpN), and the gate of the second NMOS transistor (MN2) and the fifth The gate of the NMOS transistor MN5 may also receive the enable signal EnDfe.

In some embodiments, the channel width of the fifth NMOS transistor (MN5) is the same as the channel width of the second NMOS transistor (MN2), and the channel width of the sixth NMOS transistor (MN6) is the same as the channel width of the first NMOS transistor (MN1). Same as width. Additionally, the channel length of the first NMOS transistor (MN1), the channel length of the second NMOS transistor (MN2), the channel length of the fifth NMOS transistor (MN5), and the channel length of the sixth NMOS transistor (MN6) are all the same. In this way, the total equivalent capacitance of the first NMOS transistor (MN1) and the fifth NMOS transistor (MN5) at the first node (net1), and the second NMOS transistor (MN2) and the sixth NMOS at the second node (net2) Since there is no difference compared to the total equivalent capacitance of the transistor (MN6), the load of the first node (net1) and the load of the second node (net2) are the same.

Referring to FIG. 2, in some embodiments, the first amplification module 101 includes a seventh NMOS transistor (MN7) and an eighth NMOS transistor (MN8) in addition to the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4). ) may further be included. One end of the seventh NMOS transistor (MN7) is connected to the third node (net3). One end of the eighth NMOS transistor MN8 is connected to the other end of the seventh NMOS transistor MN7 and the other end is connected to the fourth node net4. A second complementary feedback signal (fbnN) is received at the gate of one of the seventh NMOS transistor (MN7) and the eighth NMOS transistor (MN8), and an enable signal (EnDfe) is received at the other gate.

The branch formed by the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 is in parallel with the branch formed by the third NMOS transistor MN3 and the fourth NMOS transistor MN4. In this way, when the connection path between the third node (net3) and the fourth node (net4) is conducted, the total path resistance of the connection path between the third node (net3) and the fourth node (net4) is reduced, and the third node (net4) is connected. The conduction speed may be improved in response to the enable signal (EnDfe) and the second complementary feedback signal (fbnN) of the connection path between (net3) and the fourth node (net4).

In some embodiments, the ratio of the channel width and length of any one of the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) that receives the enable signal (EnDfe) is greater than the ratio of the channel width and length of the other one. , the width-to-length ratio of one channel receiving the enable signal EnDfe among the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 is greater than the width-to-length ratio of the other channel.

As described above, when the level value of the signal received at the gate of the NMOS transistor changes frequently, the larger the channel width of the NMOS transistor, the larger the gate capacitance, so the sensitivity to changes in the level value of the signal detected by the gate increases. It gets lower. Therefore, in the case of an NMOS transistor whose gate reception level value changes frequently, the influence of the gate capacitance on the NMOS transistor can be reduced by reducing the channel width of the NMOS transistor. In this way, the level value of the enable signal (EnDfe) is fixed in the section where the enable signal (EnDfe) has the first level value, and the first NMOS transistor (MN1), the second NMOS transistor (MN2), and the fifth NMOS transistor In the case of the (MN5) and sixth NMOS transistors (MN6), the gate capacitance of the two NMOS transistors receiving the enable signal (EnDfe) does not have a significant effect on the data receiving circuit 100. At this time, since the level value of the second complementary feedback signal (fbnN) continues to change frequently, the smaller the channel width of the two NMOS transistors receiving the second complementary feedback signal (fbnN) is due to the effect of the gate capacitance on the NMOS transistors. It is advantageous to reduce

Additionally, the larger the ratio between the channel width and length of the NMOS transistor, the smaller the on-resistance and the faster the turn-on or turn-off switching speed. In a state where the channel width of the two NMOS transistors receiving the second complementary feedback signal (fbnN) is relatively small, the ratio of the channel width and length of the two NMOS transistors receiving the enable signal (EnDfe) becomes relatively large. , the total on-resistance of the connection path between the third node (net3) and the fourth node (net4) can be reduced. Therefore, when comprehensively considering the two factors of the gate capacitance and on-resistance of the NMOS transistor, two NMOS transistors receiving the second complementary feedback signal (fbnN) in the section where the enable signal (EnDfe) has the first level value A change in the level value of the second complementary feedback signal fbnN can be sensitively detected, and the speed of connecting or disconnecting the connection path between the third node net3 and the fourth node net4 can be increased.

Among the first NMOS transistor (MN1) and the second NMOS transistor (MN2), the channel width and length ratio of the transistor receiving the enable signal (EnDfe) is greater than the channel width and length ratio of the other one, and the fifth NMOS transistor ( Among the sixth NMOS transistor (MN5) and MN6, the channel width-to-length ratio of the transistor that receives the enable signal (EnDfe) is greater than the channel width-to-length ratio of the other one. In addition, among the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4), the width-to-length ratio of one channel receiving the enable signal (EnDfe) is greater than the ratio of the channel width to length of the other channel, and the seventh Among the NMOS transistor MN7 and the eighth NMOS transistor MN8, the width-to-length ratio of one channel receiving the enable signal EnDfe is greater than that of the other channel. In this way, the speed of connecting or disconnecting the connection path between the first node (net1) and the second node (net2) is increased, and at the same time, the connection path between the third node (net3) and the fourth node (net4) is increased. The speed of conduction or disconnection can be increased. Therefore, when one of the connection paths between the first node (net1) and the second node (net2) and the connection path between the third node (net3) and the fourth node (net4) is quickly turned on, the other is quickly turned on. By being disconnected, the first amplification module 101 may be prevented from performing the first comparison and the second comparison at the same time.

Continuing to refer to FIG. 2 , in one example, an enable signal (EnDfe) is received at the gate of the third NMOS transistor (MN3), and a second complementary feedback signal (fbnN) is received at the gate of the fourth NMOS transistor (MN4). is received. In actual application, the channel width of the third NMOS transistor (MN3) is larger than the channel width of the fourth NMOS transistor (MN4), so that the channel width and length of the third NMOS transistor (MN1) receiving the enable signal (EnDfe) It may be advantageous to make the ratio larger than the ratio of the channel width and length of the fourth NMOS transistor (MN4) receiving the second complementary feedback signal (fbnN). Additionally, the second complementary feedback signal fbnN is received at the gate of the seventh NMOS transistor MN7, and the enable signal EnDfe is received at the gate of the eighth NMOS transistor MN8. The channel width of the seventh NMOS transistor (MN7) is smaller than the channel width of the eighth NMOS transistor (MN8), so that the ratio of the channel width and length of the eighth NMOS transistor (MN8) receiving the enable signal (EnDfe) is the second complement. It may be advantageous to make it larger than the ratio of the channel width and length of the seventh NMOS transistor (MN7) receiving the feedback signal (fbnN).

2 shows that an enable signal (EnDfe) is received at the gate of the third NMOS transistor (MN3) and the gate of the eighth NMOS transistor (MN8), and the gate of the fourth NMOS transistor (MN4) and the seventh NMOS transistor (MN7) are received. An example is shown in which the second complementary feedback signal (fbnN) is received through the gate of . In actual application, the gate of the third NMOS transistor (MN3) and the gate of the eighth NMOS transistor (MN8) may also receive the second complementary feedback signal (fbnN), and the gate of the fourth NMOS transistor (MN4) and the seventh The gate of the NMOS transistor MN7 may also receive the enable signal EnDfe.

In some embodiments, the channel width of the seventh NMOS transistor (MN7) is the same as the channel width of the fourth NMOS transistor (MN4), and the channel width of the eighth NMOS transistor (MN8) is the channel width of the third NMOS transistor (MN3). Same as width. Additionally, the channel length of the third NMOS transistor (MN3), the channel length of the fourth NMOS transistor (MN4), the channel length of the seventh NMOS transistor (MN7), and the channel length of the eighth NMOS transistor (MN8) are all the same. In this way, the total equivalent capacitance of the third NMOS transistor (MN3) and the seventh NMOS transistor (MN7) at the third node (net3), and the fourth NMOS transistor (MN4) and the eighth NMOS at the fourth node (net4) Since there is no difference compared to the total equivalent capacitance of the transistor MN8, the load of the third node net3 and the load of the fourth node net4 become the same.

Taking FIG. 2 as an example, the ratio of the channel width and length of the first NMOS transistor MN1 and the sixth NMOS transistor MN6 receiving the enable signal EnDfe is the channel width and length ratio of the channel width and length of the first complementary feedback signal fbpN. The third NMOS transistor (MN1) and the eighth NMOS transistor (MN8) are larger compared to the ratio of the channel width and length of the 2 NMOS transistor (MN2) and the fifth NMOS transistor (MN5), and receive the enable signal (EnDfe). ) may be larger compared to the ratio of the channel width and length of the fourth NMOS transistor (MN4) and the seventh NMOS transistor (MN7) that receive the second complementary feedback signal (fbnN). In the section where the enable signal (EnDfe) has the first level value, the first NMOS transistor (MN1), the sixth NMOS transistor (MN6), the third NMOS transistor (MN3), and the eighth NMOS transistor (MN8) are all in. It is permanently turned on based on the enable signal (EnDfe). The second NMOS transistor (MN2) and the fifth NMOS transistor (MN5) sensitively detect changes in the level value of the first complementary feedback signal (fbpN), and the fourth NMOS transistor (MN4) and the seventh NMOS transistor (MN7) A change in the level value of the second complementary feedback signal (fbnN) can be sensitively detected. The second NMOS transistor (MN2) and the fifth NMOS transistor (MN5) are quickly turned on in response to the first complementary feedback signal (fbpN), and the fourth NMOS transistor (MN4) and the seventh NMOS transistor (MN7) are turned on. 2 It can be turned off quickly in response to the complementary feedback signal (fbnN). Alternatively, the second NMOS transistor (MN2) and the fifth NMOS transistor (MN5) are quickly turned off in response to the first complementary feedback signal (fbpN), and the fourth NMOS transistor (MN4) and the seventh NMOS transistor (MN7) Can be turned on quickly in response to the second complementary feedback signal (fbnN). In this way, in the section where the enable signal EnDfe has the first level value, the first amplification module 101 can perform only one of the first comparison and the second comparison.

Hereinafter, everything is described based on the example of FIG. 2.

3 and 4, in some embodiments, the sampling clock signal clkN includes a first sampling clock signal clkN1 and a second sampling clock signal clkN2. The amplifier 131 includes a first comparison circuit 111, a clock generation circuit 151, and a second comparison circuit 121. The first comparison circuit 111 has a first node (net1) and a second node (net2), receives a data signal (DQ) and a first reference signal (VR+), and receives a first sampling clock signal (clkN1). A first comparison is performed in response to . The clock generation circuit 151 receives the enable signal (EnDfe) and the original sampling clock signal (clk) and outputs the second sampling clock signal (clkN2). In the section where the enable signal (EnDfe) has the first level value, the phase of the second sampling clock signal (clkN2) and the phase of the original sampling clock signal (clk) are opposite to each other, and the enable signal (EnDfe) is at the second level. In the section having a value, the second sampling clock signal (clkN2) is a logic high level signal. The second comparison circuit 121 includes a third node (net3) and a fourth node (net4) and receives the data signal (DQ) and the second reference signal (VR-). The second comparison circuit 121 performs a second comparison in response to the second sampling clock signal clkN2 in a section where the enable signal EnDfe has the first level value. In the section where the enable signal has the second level value, the connection path between the third node and the ground terminal and the connection path between the fourth node (net4) and the ground terminal are conducted.

In a section where the enable signal (EnDfe) has the first level value, the second NMOS transistor (MN2) and the fifth NMOS transistor (MN5) are connected to the first node (net1) in response to the first complementary feedback signal (fbpN). When the connection path between the second node net2 is disconnected, the first comparison circuit 111 may perform the first comparison in response to the first sampling clock signal clkN1. In the section where the enable signal (EnDfe) has the second level value, the first NMOS transistor (MN1) and the sixth NMOS transistor (MN6) are connected to the first node (net1) based on the enable signal (EnDfe) at this time. When the connection path between the two nodes (net2) is disconnected, the first comparison circuit 111 may also perform a first comparison in response to the first sampling clock signal (clkN1). Regardless of whether the enable signal EnDfe is a section having a first level value or a second level value, that is, regardless of whether the effect of inter-symbol interference on the data receiving circuit 100 is taken into account, the first comparison circuit It can be seen that 111 performs the first comparison in response to the first sampling clock signal clkN1. On the other hand, in the section where the enable signal (EnDfe) has the first level value, the fourth NMOS transistor (MN4) and the seventh NMOS transistor (MN7) respond to the second complementary feedback signal (fbnN) to the third node (net3) Only when the connection path between and the fourth node (net4) is disconnected, the second comparison circuit 121 performs the second comparison in response to the second sampling clock signal (clkN2) whose level value changes. In a section where the enable signal EnDfe has a second level value, the second sampling clock signal clkN2 is a logic high level signal. The second comparison circuit 121 conducts the connection path between the third node (net3) and the ground terminal and the connection path between the fourth node (net4) and the ground terminal, so that the third node output from the third node (net3) The level value of the signal Sn- and the level value of the fourth signal Sp- output from the fourth node net4 are both pulled down to 0. That is, the second comparison circuit 121 does not perform the second comparison and cannot output a valid second signal pair.

In some embodiments, the phase of the first sampling clock signal clkN1 is opposite to the phase of the raw sampling clock signal clk, and the second sampling clock signal is in a period in which the enable signal EnDfe has the first level value. The phase of (clkN2) is opposite to the phase of the raw sampling clock signal (clk). The phase of the first sampling clock signal (clkN1) is synchronized with the phase of the second sampling clock signal (clkN2) at this time, and the first comparison circuit 111 performs the first comparison in response to the first sampling clock signal (clkN1). Alternatively, the second comparison circuit 121 may perform the second comparison in response to the second sampling clock signal clkN2. At the same time, based on the enable signal (EnDfe), the first complementary feedback signal (fbpN), and the second complementary feedback signal (fbnN), the first NMOS transistor (MN1), the second NMOS transistor (MN2), and the fifth NMOS The transistor (MN5) and the sixth NMOS transistor (MN6) perform additional control on the potentials of the first node (net1) and the second node (net2), and the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) ), the seventh NMOS transistor (MN7) and the eighth NMOS transistor (MN8) perform additional control on the potentials of the third node (net3) and the fourth node (net4). For example, by making the potentials of the first node (net1) and the second node (net2) the same, the amplifier 131 does not actually perform the first comparison and cannot output a valid first signal pair. . Alternatively, the potentials of the third node (net3) and the fourth node (net4) are made the same, so that the amplifier 131 does not actually perform the second comparison and cannot output a valid second signal pair. In this way, the amplification unit 131 can selectively perform the first comparison or the second comparison.

Continuing to refer to FIGS. 3 and 4 , in some embodiments, the first comparison circuit 111 includes a first current source 1111, a first comparison unit 1112, and a first reset unit 1113. The first current source 1111 is connected between the power node (Vcc, see FIG. 5) and the fifth node (net5), and supplies current to the fifth node (net5) in response to the first sampling clock signal (clkN1). . The first comparison unit 1112 is connected to the first node (net1), the second node (net2), and the fifth node (net5), and receives the data signal (DQ) and the first reference signal (VR+). When the first current source 1111 supplies current to the fifth node (net5), the first comparison unit 1112 performs the first comparison and outputs the first signal (Sn+) and the second signal (Sp+) . The first reset unit 1113 is connected to the first node (net1) and the second node (net2), and operates the first node (net1) and the second node (net2) in response to the first sampling clock signal (clkN1). Reset it.

Current is supplied to the sixth node (net6) in response to the second sampling clock signal (clkN2). The second comparison unit 1212 is connected to the third node (net3), the fourth node (net4), and the sixth node (net6), and receives the data signal (DQ) and the second reference signal (VR-). When the second current source 1211 supplies current to the sixth node (net6), the first comparison unit 1112 performs the second comparison to generate the third signal (Sn-) and the fourth signal (Sp-). Print out. The second reset unit 1213 is connected between the third node (net3) and the fourth node (net4), and is connected to the third node (net3) and the fourth node (net4) in response to the second sampling clock signal (clkN2). resets.

The first comparison unit 1112 determines the difference between the current provided to the first node (net1) and the current provided to the second node (net2) based on the voltage difference between the data signal (DQ) and the first reference signal (VR+). is controlled, and the first signal (Sn+) and the second signal (Sn-) are output. The second comparison unit 1212 determines the current provided to the third node (net3) and the current provided to the fourth node (net4) based on the voltage difference between the data signal (DQ) and the second reference signal (VR-). The difference is controlled and a third signal (Sp+) and a fourth signal (Sp-) are output. In addition, the data receiving circuit 100 receives a data signal (DQ), a first reference signal (VR+), and a second reference signal (VR-), and receives a first output signal (Vout) and a second output signal (VoutN). After completing the output of The level values of the node (net3) and the fourth node (net4) can be reset to their initial values. Accordingly, it may be easy for the data receiving circuit 100 to receive and process the next data.

In some embodiments, the circuit structure of the first current source 1111 is the same as that of the second current source 1211, and the circuit structure of the first comparison unit 1112 is the same as the circuit structure of the second comparison unit 1212. same. In this way, the first signal pair output by the first comparison circuit 111 is mainly influenced by the first reference signal VR+, or the difference between the second signal pair output by the second comparison circuit 121 is mainly influenced by the first reference signal VR+. It can be affected by the second reference signal (VR-). Furthermore, the data receiving circuit 100 determines the influence of inter-symbol interference of the received data signal (DQ) on the data receiving circuit 100 based on the first reference signal (VR+) and the second reference signal (VR-). It may be more advantageous to reduce it. Accordingly, the accuracy of the first output signal (Vout) and the second output signal (VoutN) output by the second amplification module 102 can be further improved.

5 and 6, in some embodiments, the first current source 1111 includes a first PMOS transistor MP1. The first PMOS transistor MP1 is connected between the power node Vcc and the fifth node net5 and receives the first sampling clock signal clkN1 through its gate. Additionally, the second current source 1211 includes a second PMOS transistor MP2. The second PMOS transistor MP2 is connected between the power node Vcc and the sixth node net6, and the second sampling clock signal clkN2 is received through the gate.

In this way, when the first sampling clock signal clkN1 is at a low level, the first sampling clock signal clkN1 is received at the gate of the first PMOS transistor MP1 and turned on, and is transmitted to the fifth node net5. Current is supplied, and the first comparator 1112 is in an operating state, that is, in a state in which a first comparison is performed between the received data signal DQ and the first reference signal VR+. At the same time, the enable signal (EnDfe) is at a high level, the first complementary feedback signal (fbpN) is at a low level, the second NMOS transistor (MN2) and the fifth NMOS tube (MN5) are both turned off, and the The connection path between the first node (net1) and the second node (net2) is disconnected. When the second sampling clock signal clkN2 is at a low level, the second sampling clock signal clkN2 is received at the gate of the second PMOS transistor MP2 and turned on, and current is supplied to the sixth node net5. Thus, the second comparator 1212 is in an operating state, that is, in a state in which a second comparison is performed between the received data signal DQ and the second reference signal VR-. At the same time, the enable signal (EnDfe) is at a high level, the second complementary feedback signal (fbnN) is at a low level, the fourth NMOS transistor (MN4) and the seventh NMOS tube (MN7) are both turned off, and the The connection path between the third node (net3) and the fourth node (net4) is disconnected.

In one example, the phase of the first sampling clock signal (clkN1) is opposite to the phase of the raw sampling clock signal (clk), and when the impact of inter-symbol interference on the data receiving circuit 100 must be reduced, enable In a section where the signal EnDfe has a first level value, that is, a high level section, the phase of the second sampling clock signal clkN2 is opposite to the phase of the original sampling clock signal clk. The phase of the first sampling clock signal (clkN1) and the phase of the second sampling clock signal (clkN2) are synchronized, so that the first current source 1111 prepares the first comparison unit 121 to perform the first comparison. Current may be supplied to the node net5, and the second current source 1211 may supply current to the sixth node net6 to prepare the second comparison unit 122 to perform the second comparison. At this time, if the enable signal (EnDfe) is at a high level and the first complementary feedback signal (fbpN) is at a low level, the connection path between the first node (net1) and the second node (net2) is disconnected and the first comparison unit ( 121) performs the first comparison. At this time, if the second complementary feedback signal (fbnN) is at a high level, the connection path between the third node (net3) and the fourth node (net4) is conducted and the second comparison unit 122 cannot perform the second comparison. . When the first complementary feedback signal (fbpN) is at a high level, the connection path between the first node (net1) and the second node (net2) is conducted, so that the first comparison unit 121 cannot perform the first comparison. . At this time. When the second complementary feedback signal fbnN is at a low level, the connection path between the third node net3 and the fourth node net4 is disconnected, and the second comparison unit 122 performs the first comparison.

In addition, when there is no need to consider the influence of inter-symbol interference on the data receiving circuit 100, in a section where the enable signal EnDfe has a second level value, that is, in a section where it is a low level, the second sampling clock signal (clkN2) is a logic high level signal, and the second PMOS transistor MP2 is always turned off, so the current of the second comparison unit 1212 becomes almost 0. Accordingly, power consumption of the data receiving circuit 100 can be reduced. Additionally, at this time, the second comparison unit 1212 cannot perform the second comparison and thus cannot output a valid second signal pair. At this time, the first sampling clock signal clkN1 is a clock signal, and the first PMOS transistor MP1 may be turned on in response to the clock signal. Accordingly, the first comparison unit 1112 performs the first comparison and outputs a valid first signal pair. Accordingly, the entire data reception circuit 100 can operate normally.

Continuing to refer to FIGS. 5 and 6 , in some embodiments, the first comparison unit 1112 includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The third PMOS transistor MP3 is connected between the first node net1 and the fifth node net5 and receives the data signal DQ through the gate. The fourth PMOS transistor MP4 is connected between the second node net2 and the fifth node net5, and the first reference signal VR+ is received through the gate. The second comparison unit 1212 includes a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6. The fifth PMOS transistor MP5 is connected between the third node net3 and the sixth node net6 and receives the data signal DQ through the gate. The sixth PMOS transistor MP6 is connected between the fourth node net4 and the sixth node net6, and the second reference signal VR- is received through the gate.

In the case of the first comparator 1112, the changes in the level values of the data signal DQ and the first reference signal VR+ are not synchronized, so the third PMOS transistor MP3 through which the data signal DQ is received is The turn-on time is different from the turn-on time of the fourth PMOS transistor MP4 at which the first reference signal VR+ is received. Additionally, at the same point in time, the degree to which the third PMOS transistor MP3 is turned on is not the same as the degree to which the fourth PMOS transistor MP4 is turned on. In a situation where the degree to which the third PMOS transistor MP3 is turned on is different from the degree to which the fourth PMOS transistor MP4 is turned on, the third PMOS transistor MP3 and The shunt capability of the fourth PMOS transistor MP4 is also different. Therefore, the voltage of the first node (net1) is different from the voltage of the second node (net2), and the first signal (Sn+) and the second signal (Sp+) are output as a first signal pair with a large difference in signal level value. It can be advantageous to

In the case of the second comparison unit 1212, the changes in the level values of the data signal DQ and the second reference signal VR- are not synchronized, so the fifth PMOS transistor MP5 through which the data signal DQ is received The turn-on time is not the same as the turn-on time of the sixth PMOS transistor MP6 at which the second reference signal VR- is received. Additionally, at the same point in time, the degree to which the fifth PMOS transistor MP5 is turned on is not the same as the degree to which the sixth PMOS transistor MP6 is turned on. In a situation where the degree to which the fifth PMOS transistor (MP5) is turned on is different from the degree to which the sixth PMOS transistor (MP6) is turned on, the current of the sixth node (net6) of the fifth PMOS transistor (MP5) and The shunt capability of the sixth PMOS transistor (MP6) is also different. Therefore, the voltage of the third node (net3) is different from the voltage of the fourth node (net4), and the third signal (Sn-) and the fourth signal (Sp-) are connected as a second signal pair with a large difference in signal level value. Can be printed.

In one example, the first amplification module 101 performs the first comparison, and when the level value of the data signal DQ is less than the level value of the first reference signal VR+, the third PMOS transistor MP3 The degree to which the fourth PMOS transistor (MP4) is turned on is greater than the degree to which the fourth PMOS transistor (MP4) is turned on. Accordingly, the current of the fifth node (net5) flows more to the path where the third PMOS transistor (MP3) is located, the current of the first node (net1) is larger than the current of the second node (net2), and the current of the first node (net1) is larger than the current of the second node (net2). The level value of the first signal (Sn+) output from (net1) becomes larger, and the level value of the second signal (Sp+) output from the second node (net2) becomes smaller. In another example, when the first amplification module 101 performs the second comparison, when the level value of the data signal DQ is less than the level value of the second reference signal VR-, the fifth PMOS transistor MP5 ) is turned on is greater than the degree to which the sixth PMOS transistor (MP6) is turned on, causing more current of the sixth node (net6) to flow into the path where the fifth PMOS transistor (MP5) is located, By making the current of the third node (net3) larger than the current of the fourth node (net4), the level value of the third signal (Sn-) output from the third node (net3) becomes larger, and the level value of the third signal (Sn-) output from the third node (net3) becomes larger. The level value of the fourth signal (Sp-) output from becomes smaller.

Likewise, when the level value of the data signal DQ is greater than the level value of the first reference signal VR+, the degree to which the third PMOS transistor MP3 is turned on is determined by the degree to which the fourth PMOS transistor MP4 is turned on. The level value of the first signal (Sn+) output from the first node (net1) is small, and the level value of the second signal (Sp+) output from the second node (net2) is large. When the level value of the data signal DQ is greater than the level value of the second reference signal VR-, the degree to which the fifth PMOS transistor MP5 is turned on is equal to the degree to which the sixth PMOS transistor MP6 is turned on. The level value of the third signal (Sn-) output from the third node (net3) is small, and the level value of the fourth signal (Sp-) output from the fourth node (net4) is large.

Continuing to refer to FIGS. 5 and 6 , the first reset unit 1113 includes a ninth NMOS transistor (MN9) and a tenth NMOS transistor (MN10). The ninth NMOS transistor MN9 is connected between the first node net1 and the ground terminal, and receives the first sampling clock signal clkN1 through its gate. The tenth NMOS transistor MN10 is connected between the second node net2 and the ground terminal, and receives the first sampling clock signal clkN1 through its gate. The second reset unit 1213 includes an 11th NMOS transistor (MN11) and a 12th NMOS transistor (MN12). The 11th NMOS transistor (MN11) is connected between the third node (net3) and the ground terminal, and the second sampling clock signal (clkN2) is received through the gate. The twelfth NMOS transistor MN12 is connected between the fourth node net4 and the ground terminal, and receives the second sampling clock signal clkN2 through its gate.

In one example, the phase of the first sampling clock signal clkN1 is opposite to that of the original sampling clock signal clk. When it is necessary to reduce the impact of inter-symbol interference on the data reception circuit, in the section where the enable signal (EnDfe) has the first level value, the phase of the second sampling clock signal (clkN2) is also similar to the original sampling clock signal (clk). are opposite to each other. At this time, the phase of the first sampling clock signal (clkN1) is synchronized with the phase of the second sampling clock signal (clkN2). When both the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are at low level, both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on. At this time, the 9th NMOS transistor (MN9), the 10th NMOS transistor (MN10), the 11th NMOS transistor (MN11), and the 12th NMOS transistor (MN12) are all turned off. At this time, based on the first complementary feedback signal (fbp) and the second complementary feedback signal (fbnN) being turned on, the connection path between the first node (ne1) and the second node (net2) and the third node ( One of the connection paths between ne3) and the fourth node (net4) is controlled to conduction. Accordingly, the first amplification module 101 can selectively perform the first comparison or the second comparison. At the same time, the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 serve as loads of the first comparison unit 1112, so that the amplification gain of the first comparison unit 1112 can be increased. Additionally, the 11th NMOS transistor MN11 and the 12th NMOS transistor MN12 serve as loads of the second comparison unit 1212, so that the amplification gain of the second comparison unit 1212 may be increased.

When both the first sampling clock signal (clkN1) and the second sampling clock signal (clkN2) are high level, the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are both turned off, and the first comparison unit No current flows through both 1112 and the second comparison unit 1212. At this time, the 9th NMOS transistor (MN9), the 10th NMOS transistor (MN10), the 11th NMOS transistor (MN11), and the 12th NMOS transistor (MN12) are all turned on, and the voltage of the first node (net1), The voltage of the second node (net2), the voltage of the third node (net3), and the voltage of the fourth node (net4) are pulled down. Accordingly, the first node (net1), the second node (net2), the third node (net3), and the fourth node (net4) are reset. Accordingly, subsequent data reception and processing in the data reception circuit 100 may be easy.

In addition, when there is no need to consider the influence of inter-symbol interference on the data receiving circuit 100, in a section where the enable signal EnDfe has a second level value, the second sampling clock signal clkN2 is at a logic high level. signal, and the second PMOS transistor MP2 is always turned off. At this time, both the 11th NMOS transistor (MN11) and the 12th NMOS transistor (MN12) are turned on, and the connection path between the third node (net3) and the ground terminal and the connection between the fourth node (net4) and the ground terminal The pass goes through. Accordingly, the third node (net3) and the fourth node (net4) are reset. At this time, the current of the second comparison unit 1212 becomes almost 0, so the power consumption of the data receiving circuit 100 can be reduced. At this time, when the first sampling clock signal clkN1 is at a low level, the first PMOS transistor MP1 is turned on, and both the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are turned off. Accordingly, the second comparator 1212 performs the first comparison and outputs a valid first signal pair, and the second amplification module 102 can continuously receive the first signal pair. Alternatively, when the first sampling clock signal clkN1 is at a high level, the first PMOS transistor MP1 is turned off, and both the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are turned on. Accordingly, the first node (net1) and the second node (net2) are reset. Accordingly, subsequent data reception and processing in the data reception circuit 100 may be easy.

Continuing to refer to FIGS. 5 and 6 , in some embodiments, the clock generation circuit 151 may include a first NAND gate circuit 1511. The first NAND gate circuit 1511 receives a raw sampling clock signal (clk) at one input terminal, has another input terminal connected to a power node (Vcc), and outputs a first sampling clock signal (clkN1) at an output terminal.

The input terminal of the first NAND gate 1511 connected to the power node (Vcc) receives a high level. At this time, if the raw sampling clock signal (clk) received through the other input terminal of the first NAND gate 1511 is at a high level, the first sampling clock signal (clkN1) is at a low level. If the raw sampling clock signal clk received through the other input terminal of the first NAND gate 1511 is low level, the first sampling clock signal clkN1 is high level. As such, since the first sampling clock signal clkN1 is at a high level, the phase of the first sampling clock signal clkN1 and the phase of the original sampling clock signal clk are opposite to each other. Therefore, when inter-symbol interference for the data receiving circuit is to be reduced, the phase of the first sampling clock signal (clkN1) and the phase of the second sampling clock signal (clkN2) are synchronized, so that the first amplification module 101 is selectively You can perform the first comparison or the second comparison.

Continuing to refer to FIGS. 5 and 6 , in some embodiments, clock generation circuit 151 may include a second NAND gate circuit 1512 . The second NAND gate circuit 1512 receives the raw sampling clock signal (clk) at one input terminal, receives the enable signal (EnDfe) at the other input terminal, and outputs the second sampling clock signal (clkN2) at the output terminal. do.

The phase of the first sampling clock signal (clkN1) and the phase of the original sampling clock signal (clk) are opposite to each other, and when inter-symbol interference for the data receiving circuit 100 must be reduced, the enable signal (EnDfe) is set to high. level, and when the original sampling clock signal (clk) is at a high level, the second sampling clock signal (clkN2) output from the second NAND gate 1512 is at a low level. At this time, the first sampling clock signal clkN1 also becomes low level. The first amplification module 101 selectively performs either the first comparison or the second comparison, whichever is more preferable, based on the first complementary feedback signal (fbpN) and the second complementary feedback signal (fbnN). Next, the second amplification module 102 receives a valid first signal pair or a second signal pair. Since the other signal pair is not valid, the influence of inter-symbol interference of the received data signal DQ on the data reception circuit 100 can be reduced. If the original sampling clock signal clk is at a low level, the second sampling clock signal clkN2 output from the second NAND gate 1512 is at a high level. At this time, the first sampling clock signal clkN1 also becomes high level. At this time, both the first amplification unit 131 and the second amplification unit 131 are in a non-operating state, and the first node (net1) and the second node (net2) are connected through the first reset unit 1113. The level value is reset to the initial value, and the level values of the third node (net3) and the fourth node (net4) may be reset to the initial value through the second reset unit 1213. Accordingly, subsequent data reception and processing in the data reception circuit 100 may be easy.

When there is no need to reduce inter-symbol interference for the data receiving circuit 100, the enable signal EnDfe is brought to a low level. At this time, regardless of whether the original sampling clock signal clk is high level or low level, the second sampling clock signal clkN2 output from the second NAND gate 1512 is high level. Therefore, regardless of whether the first sampling clock signal clkN1 is high level or low level, that is, regardless of whether the first comparison is performed in the first comparison unit 1112, the third of the second comparison circuits 121 The connection path between the node net3 and the ground terminal and the connection path between the fourth node net4 and the ground terminal may all be conductive. At this time, the current of the second comparison circuit 121 becomes almost 0 and the second comparison is not performed.

Referring to FIG. 4 , in some embodiments, the second amplification module 102 includes a first input unit 112, a second input unit 122, and a latch unit 132. The first input unit 112 is connected to the seventh node (net7) and the eighth node (net8), receives the first signal pair, and performs a third comparison. Additionally, the first input unit 112 provides signals to the seventh node (net7) and the eighth node (net8) as a result of the third comparison. The second input unit 122 is connected to the seventh node (net7) and the eighth node (net8), receives the second signal pair, and performs the fourth comparison. Additionally, the second input unit 122 provides signals to the seventh node (net7) and the eighth node (net8) as a result of the fourth comparison. The latch unit 132 is connected to the seventh node (net7) and the eighth node (net8), and amplifies and latches the signal of the seventh node (net7) and the signal of the eighth node (net8). Additionally, the latch unit 132 outputs a first output signal (Vout) and a second output signal (VoutN) through the first output node (net9) and the second output node (net10), respectively.

When it is necessary to reduce the impact of inter-symbol interference on the data reception circuit, in a section where the enable signal (EnDfe) has a first level value, the first amplification module 101 generates the first complementary feedback signal (fbpN) and the first complementary feedback signal (fbpN). 2 Based on the complementary feedback signal (fbnN), the first comparison and the second comparison are selectively performed. One of the first signal pair and the second signal pair output by the first amplification module 101 is valid, and the other is invalid. Also, at this time, what the input unit that can be turned on receives is a valid signal pair. A valid signal pair refers to a signal pair in which the difference in level values that can be output is greater when the first comparison and the second comparison can be performed simultaneously. Accordingly, the accuracy of the first output signal (Vout) and the second output signal (VoutN) output by the first amplification module 101 can be improved. When there is no need to consider the effect of inter-symbol interference on the data reception circuit 100, in a section where the enable signal EnDfe has a second level value, the first amplification module 101 generates a valid first signal pair. Prints out permanently. Additionally, the first input unit 112 is turned on or turned off in response to a valid first signal pair. Since the signal pair received by the second input unit 122 is invalid and is turned off, power consumption of the data receiving circuit can be reduced.

At this time, the latch unit 132 outputs a high level signal to the first output node (net9) and the second output node (net10) based on the signal of the seventh node (net7) and the signal of the eighth node (net8). It is used to output a low level signal, or to output a low level signal to the first output node (net9) and to output a high level signal to the second output node (net10).

Referring to FIGS. 7 and 8 , in some embodiments, the first input unit 112 may include a 13th NMOS transistor (MN13) and a 14th NMOS transistor (MN14). The drain of the thirteenth NMOS transistor (MN13) is connected to the seventh node (net7), the source is connected to the ground terminal, and the first signal (Sn+) is received at the gate. The drain of the fourteenth NMOS transistor (MN14) is connected to the eighth node (net8), the source is connected to the ground terminal, and the second signal (Sp+) is received at the gate. The second input unit 122 may include a 15th NMOS transistor (MN15) and a 16th NMOS transistor (MN16). The drain of the fifteenth NMOS transistor (MN15) is connected to the seventh node (net7), the source is connected to the ground terminal, and the third signal (Sn-) is received through the gate. The drain of the 16th NMOS transistor (MN16) is connected to the eighth node (net8), the source is connected to the ground terminal, and the fourth signal (Sp-) is received at the gate.

In one example, when the first amplification module 101 performs the first comparison, if the level value of the data signal (DQ) is greater than the level value of the first reference signal (VR+), the level of the first signal (Sn+) The value is small and the level value of the second signal (Sp+) is large, so the degree to which the 14th NMOS transistor (MN14) is turned on is greater than the degree to which the 13th NMOS transistor (MN13) is turned on. Accordingly, the voltage of the eighth node (net8) becomes lower than the voltage of the seventh node (net7). Likewise, if the level value of the data signal DQ is lower than the level value of the first reference signal VR+, the level value of the first signal Sn+ is large and the level value of the second signal Sp+ is small, The degree to which the 13th NMOS transistor (MN13) is turned on is greater than the degree to which the 14th NMOS transistor (MN14) is turned on. Accordingly, the voltage of the seventh node (net7) becomes lower than the voltage of the eighth node (net7).

In another example, when the first amplification module 101 performs the second comparison, if the level value of the data signal (DQ) is greater than the level value of the second reference signal (VR-), the third signal (Sn-) The level value of is small, the level value of the fourth signal (Sp-) is large, and the degree to which the 16th NMOS transistor (MN16) is turned on is greater than the degree to which the 15th NMOS transistor (MN15) is turned on. Accordingly, the voltage of the eighth node (net8) becomes lower than the voltage of the seventh node (net7). Likewise, if the level value of the data signal (DQ) is lower than the level value of the second reference signal (VR-), the level value of the third signal (Sn-) is large, and the level value of the fourth signal (Sp-) is It is small, and the degree to which the 15th NMOS transistor (MN15) is turned on is greater than the degree to which the 16th NMOS transistor (MN16) is turned on. Accordingly, the voltage of the seventh node (net7) becomes lower than the voltage of the eighth node (net7).

Continuing to refer to FIGS. 7 and 8 , in some embodiments, the latch unit 132 includes a 17th NMOS transistor (MN17), a 7th PMOS transistor (MP7), an 18th NMOS transistor (MN18), and an 8th PMOS transistor. (MP8) may be included. The source of the 17th NMOS transistor (MN17) is connected to the seventh node (net7), the drain is connected to the first output node (net9), and the gate is connected to the second output node (net10). The source of the seventh PMOS transistor MP7 is connected to the power node (Vcc), the drain is connected to the first output node (net9), and the gate is connected to the second output node (net10). The eighteenth NMOS transistor MN18 has its source connected to the eighth node net8, its drain connected to the second output node net10, and its gate connected to the second output node net10. The source of the eighth PMOS transistor MP8 is connected to the power node (Vcc), the drain is connected to the second output node (net10), and the gate is connected to the first output node (net9).

In one example, when the first amplification module 101 performs the first comparison, the level value of the data signal (DQ) is greater than the level value of the first reference signal (VR+), and the level value of the first signal (Sn+) The value is small, and when the level value of the second signal (Sp+) is large, the voltage of the eighth node (net8) becomes lower than the voltage of the seventh node (net7). Accordingly, the degree to which the 18th NMOS transistor (MN18) is turned on is greater than the degree to which the 17th NMOS transistor (MN17) is turned on. In addition, the voltage of the second output node (net10) is lower than the voltage of the first output node (net9), and the degree to which the eighth PMOS transistor (MP8) is turned on is the degree to which the seventh PMOS transistor (MP7) is turned on. is smaller, the latch unit 132 forms positive feedback amplification, so that the first output signal (Vout) output from the first output node (net9) becomes a higher high level, and the first output signal (Vout) output from the first output node (net10) becomes a higher high level. The second output signal VoutN becomes a lower low level. Likewise, if the level value of the data signal (DQ) is less than the level value of the first reference signal (VR+), the voltage of the seventh node (net7) becomes lower than the voltage of the eighth node (net7) and the first output node The first output signal (Vout) output from (net9) becomes a low level, and the second output signal (VoutN) output from the second output node (net10) becomes a high level.

In another example, when the first amplification module 101 performs the second comparison, if the level value of the data signal (DQ) is greater than the level value of the second reference signal (VR-), the third signal (Sn-) The level value of is small and the level value of the fourth signal (Sp-) is large, so the degree to which the 16th NMOS transistor (MN16) is turned on is greater than the degree to which the 15th NMOS transistor (MN15) is turned on. The voltage of the 8th node (net8) becomes lower than the voltage of the 7th node (net7). Accordingly, the first output signal Vout output from the first output node net9 becomes a high level, and the second output signal VoutN output from the second output node net10 becomes a low level. Likewise, if the level value of the data signal (DQ) is lower than the level value of the second reference signal (VR-), the level value of the third signal (Sn-) is large, and the level value of the fourth signal (Sp-) is It becomes small. At this time, the first output signal Vout output from the first output node net9 becomes a low level, and the second output signal VoutN output from the second output node net10 becomes a high level.

Referring to FIG. 4 , in some embodiments, the second amplification module 102 may further include a third reset unit 142. The third reset unit 142 is connected between the power node (Vcc) and the output terminal of the latch unit 132, and resets the output terminal of the latch unit 132. In this way, the data receiving circuit 100 receives the data signal (DQ), the first reference signal (VR+) and the second reference signal (VR-), and the first output signal (Vout) and the second output signal (VoutN). ), the level values of the first output node (net9) and the second output node (net10) can be reset to their initial values through the third reset unit 142. Accordingly, subsequent data reception and processing in the data reception circuit 100 may be easy.

Referring to FIGS. 7 and 8 , in some embodiments, the third reset unit 142 may include a ninth PMOS transistor MP9 and a tenth PMOS transistor MP10. The ninth PMOS transistor MP9 is connected between the first output node net9 and the power node Vcc, and receives the raw sampling clock signal clk through its gate. The tenth PMOS transistor MP10 is connected between the second output node net10 and the power node Vcc, and receives the raw sampling clock signal clk through its gate.

In one example, the phase of the first sampling clock signal (clkN1) and the phase of the raw sampling clock signal (clk) are opposite to each other, and when inter-symbol interference for the data receiving circuit 100 needs to be reduced, an enable signal ( EnDfe) becomes logic level 1. The phase of the second sampling clock signal (clkN2) and the phase of the original sampling clock signal (clk) are opposite to each other, and when the original sampling clock signal (clk) is at a high level, the first sampling clock signal (clkN1) and the second sampling The clock signal clkN2 all becomes low level, and both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on. At this time, the first amplification module 101 selectively performs either the first comparison or the second comparison based on the first complementary feedback signal (fbpN) and the second complementary feedback signal (fbnN). Accordingly, the first amplification module 101 may output only one of the valid first signal pair and the second signal pair. For example, when the first complementary feedback signal (fbpN) is at a low level and the second complementary feedback signal (fbnN) is at a high level, the first comparison unit 1112 performs the first comparison and the second comparison unit 1212 ) performs the second comparison. At this time, the 9th NMOS transistor (MN9), the 10th NMOS transistor (MN10), the 11th NMOS transistor (MN11), the 12th NMOS transistor (MN12), the 9th PMOS transistor (MP9), and the 10th PMOS transistor (MP10) Everything is turned off.

When the raw sampling clock signal (clk) is at a low level, both the first sampling clock signal (clkN1) and the second sampling clock signal (clkN2) become high level, so that the first PMOS transistor (MP1) and the second PMOS transistor ( MP2) are all turned off. At this time, the 9th NMOS transistor (MN9), the 10th NMOS transistor (MN10), the 11th NMOS transistor (MN11), and the 12th NMOS transistor (MN12) are all turned on, and the voltage of the first node (net1), The voltage of the second node (net2), the voltage of the third node (net3), and the voltage of the fourth node (net4) are pulled down. Accordingly, the first node (net1), the second node (net2), the third node (net3), and the fourth node (net4) can be reset. The ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are also turned on, so that the voltage of the first output node net9 and the voltage of the second output node net10 are pulled up. Accordingly, the first output node (net9) and the second output node (net10) may be reset.

When there is no need to consider the effect of inter-symbol interference on the data reception circuit 100, the enable signal EnDfe is at logic level 0. At this time, regardless of whether the original sampling clock signal clk is high level or low level, the second sampling clock signal clkN2 is always high level. Accordingly, the second PMOS transistor MP2 is always turned off, and the current of the second comparison circuit 121 is reduced. Accordingly, power consumption of the data receiving circuit 100 can be reduced.

Referring to FIG. 4 , in some embodiments, the data receiving circuit 100 may further include a first inverting circuit 114 and a second inverting circuit 124 . The first inverting circuit 114 receives the first feedback signal (fbp) and outputs the first complementary feedback signal (fbpN). The second inverting circuit 124 receives the second feedback signal (fbn) and outputs a second complementary feedback signal (fbnN).

4 to 6 , in some embodiments, the first inverting circuit 114 includes a first inverter 1141 and the second inverting circuit 124 includes a second inverter 1241.

Referring to FIG. 9, the data reception circuit 100 and the latch circuit 110 connected to the data reception circuit 100 may form a plurality of data transmission circuits 120. A plurality of data transmission circuits 120 connected in cascade constitute a data reception system. The output signal of the data transmission circuit 120 of the previous stage becomes the feedback signal (fb) of the data transmission circuit 120 of the next stage, and the output signal of the data transmission circuit 120 of the final stage becomes the data transmission circuit 120 of the first stage. It becomes the feedback signal (fb) of (120). The feedback signal (fb) includes a first feedback signal (fbp) and a second feedback signal (fbn).

When a plurality of data receiving circuits 100 are connected in cascade, the first output signal (Vout) and the second output signal (VoutN) output from the data receiving circuit 100 of the previous stage are each connected to the data receiving circuit of the next stage ( 100) and become the first feedback signal (fbp) and the second feedback signal (fbp). The data receiving circuit 100 in the next stage selectively performs first comparison or second comparison based on the received first feedback signal (fbp) and second feedback signal (fbn). The first output signal (Vout) and the second output signal (VoutN) output by the data receiving circuit 100 of the final stage are the first feedback signal (fbp) and the second feedback signal of the data receiving circuit 100 of the first stage, respectively. It becomes a signal (fbn). The data receiving circuit 100 of the first stage selectively performs first comparison or second comparison based on the received first feedback signal (fbp) and second feedback signal (fbn).

Specifically, the first output signal (Vout) output from the first output node (net9) of the data receiving circuit 100 of the previous stage becomes the first feedback signal (fbp) of the data receiving circuit 100 of the next stage, , the second output signal (VoutN) output from the second output node (net10) of the data receiving circuit 100 of the previous stage becomes the second feedback signal (fbn) of the data receiving circuit 100 of the next stage. In addition, the first inverter 1141 of the data receiving circuit 100 of the next stage converts the first feedback signal (fbp) into a first complementary feedback signal (fbpN), and the second NMOS transistor (MN2) of the corresponding stage It is provided to the gate and the gate of the fifth NMOS transistor (MN5). The second inverter 1241 of the data receiving circuit 100 of the next stage converts the second feedback signal (fbn) into the second complementary feedback signal (fbnN) and transmits it to the gate and gate of the fourth NMOS transistor (MN4) of the corresponding stage. It is provided to the gate of the seventh NMOS transistor (MN7).

The first output signal (Vout) output from the first output node (net9) of the data receiving circuit 100 of the previous stage is high level, and the second output signal (VoutN) output from the second output node (net10) is low level. If the level, the first feedback signal (fbp) of the next stage data receiving circuit 100 becomes a high level, and the second feedback signal (fbn) becomes a low level. Accordingly, the first complementary feedback signal (fbpN) becomes a low level, and the second complementary feedback signal (fbnN) becomes a high level.

4 and 8, in some embodiments, first inverting circuit 114 includes a third NAND gate 1142 and second inverting circuit 124 includes a fourth NAND gate 1242. can do. The third NAND gate 1142 receives a first feedback signal (fbp) and an enable signal (EnDfe) at both input terminals, respectively, and outputs a first complementary feedback signal (fbpN) at the output terminal. The fourth NAND gate 1242 receives a second feedback signal (fbn) and an enable signal (EnDfe) at both input terminals, respectively, and outputs a second complementary feedback signal (fbnN) at the output terminal.

At this time, in the section where the enable signal (EnDfe) has the first level value, that is, when the logic level is 1, the change in the level value of the first feedback signal (fbp) received by the third NAND gate 1142 is The change in level value of the output first complementary feedback signal (fbpN) is opposite to each other. That is, the levels of the first complementary feedback signal (fbpN) and the first feedback signal (fbp) are opposite to each other. Additionally, a change in the level value of the second feedback signal fbn received by the fourth NAND gate 1242 and a change in the level value of the second complementary feedback signal fbnN output are opposite to each other. That is, the levels of the second complementary feedback signal (fbnN) and the second feedback signal (fbn) are opposite to each other.

Referring to FIGS. 4 and 8 , in one example, when a plurality of data receiving circuits 100 are connected in cascade, the first output output from the first output node (net9) of the data receiving circuit 100 of the previous stage The signal (Vout) becomes the first feedback signal (fbp). The third NAND gate 1142 of the data reception circuit 100 of the previous stage receives the first feedback signal (fbp) and the enable signal (EnDfe), and provides first complementary feedback to the data reception circuit 100 of the next stage. Outputs a signal (fbpN). The second output signal VoutN output from the second output node net10 of the data receiving circuit 100 of the previous stage becomes the second feedback signal fbn. The fourth NAND gate 1242 of the data reception circuit 100 of the previous stage receives the second feedback signal (fbn) and the enable signal (EnDfe), and provides a second complementary feedback to the data reception circuit 100 of the next stage. Outputs a signal (fbnN). Additionally, the data receiving circuit 100 of the next stage selectively performs a first comparison or a second comparison based on the first complementary feedback signal (fbpN) and the second complementary feedback signal (fbnN). The first complementary feedback signal (fbpN) is generated by the third NAND gate 1142, and the driving ability of the first complementary feedback signal (fbpN) can be improved by using the third NAND gate 1142. The second complementary feedback signal fbnN is generated by the fourth NAND gate 1242, and the driving ability of the second complementary feedback signal fbnN can be improved by using the fourth NAND gate 1242. In this way, the first complementary feedback signal (fbpN) and the second complementary feedback signal (fbnN) are transmitted from the previous stage to the next stage, and when the transmission path is long, the third NAND gate 1142 and the fourth NAND gate 1242 Through this, the driving ability of the data transmission circuit 100 of the next stage of the first complementary feedback signal (fbpN) and the second complementary feedback signal (fbnN) can be increased.

In another example, when a plurality of data receiving circuits 100 are connected in cascade, the first output signal (Vout) and the second output signal (VoutN) of the data receiving circuit 100 of the previous stage are each connected to the first output signal (Vout) of the data receiving circuit 100 of the next stage. They become a feedback signal (fbp) and a second feedback signal (fbn). The third NAND gate 1142 of the data receiving circuit 100 of the next stage converts the first feedback signal (fbp) into a first complementary feedback signal (fbpN), and is connected to the gate of the second NMOS transistor (MN2) of the corresponding stage. and to the gate of the fifth NMOS transistor (MN5). The fourth NAND gate 1242 of the data receiving circuit 100 of the next stage converts the second feedback signal (fbn) into the second complementary feedback signal (fbnN) and transmits it to the gate of the fourth NMOS transistor (MN4) of the corresponding stage. and to the gate of the seventh NMOS transistor (MN7). Additionally, the third NAND gate 1142 may be disposed adjacent to the gate of the fourth NMOS transistor MN4 and the gate of the seventh NMOS transistor MN7.

Below, the specific operating principle of the data reception circuit 100 according to an embodiment of the present invention is described in detail through FIGS. 5, 7, and Table 1.

In one example, when a plurality of data receiving circuits 100 are connected in cascade, the first output signal (Vout) output from the first output node (net9) of the data receiving circuit 100 of the previous stage is connected to the data of the next stage. It becomes the first feedback signal (fbp) of the receiving circuit 100, and the second output signal (VoutN) output from the second output node (net10) of the data receiving circuit 100 of the previous stage is the data receiving circuit of the next stage. It becomes the second feedback signal (fbn) of (100).

Hereinafter, the case where the level value of the received first reference signal (VR+) is greater than the level value of the second reference signal (VR-) will be described as an example. The data signal DQ being at logic level 1 means that the level value of the data signal DQ is greater than the level value of the first reference signal VR+, and the data signal DQ being at logic level 0 means the data signal ( This means that the level value of DQ) is smaller than the level value of the second reference signal (VR-). In Table 1, 1 represents high level and 0 represents low level.

When the effect of inter-symbol interference on the data receiving circuit 100 must be considered, the enable signal EnDfe is at a high level, and at this time the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned on. , the second NMOS transistor (MN2) is turned on or off in response to the first complementary feedback signal (fbpN), and the fourth NMOS transistor (MN4) is turned on in response to the second complementary feedback signal (fbnN). It is turned on or turned off.

Referring to Table 1, when the data signal DQ1 received by the data receiving circuit 100 of the previous stage is logic level 1, the first output signal Vout output by the data receiving circuit 100 of the previous stage is, That is, the first feedback signal (fbp) of the data receiving circuit 100 of the next stage is high level, and the second output signal (VoutN) output by the data receiving circuit 100 of the previous stage, that is, the data receiving circuit of the next stage The second feedback signal (fbn) of (100) becomes low level. At this time, the first complementary feedback signal (fbpN) becomes a low level, the second complementary feedback signal (fbnN) becomes a high level, the second NMOS transistor (MN2) is turned off, and the fourth NMOS transistor (MN4) is turned on. Additionally, the first amplification module 101 performs the first comparison and outputs the first signal (Sn+) and the second signal (Sp+) through the first node (net1) and the second node (net2). The first input unit 112 performs a third comparison on the first signal (Sn+) and the second signal (Sp+) and provides signals to the seventh node (net7) and the eighth node (net8). At this time, no current flows through the second input unit 122.

When the data signal DQ1 received by the data receiving circuit 100 of the previous stage is logic level 1, the data signal DQ2 received by the data receiving circuit 100 of the next stage corresponds to the following two cases. .

Case 1: Referring to Table 1, when the data signal (DQ2) received by the data receiving circuit 100 of the next stage is logic level 0, the data signal (DQ1) received by the data receiving circuit 100 of the previous stage is logic level 0. The difference from the level value is large, and there is relatively large interference between symbols. At this time, the first amplification module 101 of the data receiving circuit 100 of the next stage performs the first comparison to output the first signal (Sn+) and the second signal (Sp+), and the first input unit 112 Turn it on. That is, the second amplification module 102 of the next stage data reception circuit 100 receives the first signal (Sn+) and the second signal (Sp+). At this time, in the data receiving circuit 100 of the next stage, the data signal (DQ2) is at logic level 0, and the voltage difference between the data signal (DQ2) and the first reference signal (VR+) is equal to the data signal (DQ2) and the second reference signal (VR+). It is larger than the voltage difference of VR-). At this time, if the second comparison can be performed, the difference in the level value of the signal of the effective first signal pair obtained by performing the first comparison is the level value of the signal of the effective second signal pair obtained by performing the second comparison. It's bigger than the difference. At this time, the second amplification module 102 may receive a valid first signal pair and output the first output signal (Vout) and the second output signal (VoutN) with higher accuracy. Accordingly, the influence of inter-symbol interference of the data signal DQ on the data receiving circuit 100 can be reduced, and power consumption of the data receiving circuit 100 can be reduced because the second comparison is not performed.

Case 2: Referring to Table 1, when the data signal (DQ2) received by the data receiving circuit 100 of the next stage is logic level 1, the data signal (DQ1) received by the data receiving circuit 100 of the previous stage The difference from the level value is small, and interference between symbols is small or non-existent. At this time, the first amplification module 101 of the data receiving circuit 100 of the next stage performs the first comparison to output the first signal (Sn+) and the second signal (Sp+), and the first input unit 112 Turn it on. That is, the second amplification module 102 of the next stage data reception circuit 100 receives the first signal (Sn+) and the second signal (Sp+).

Referring to Table 1, when the data signal DQ1 received by the data receiving circuit 100 of the previous stage is logic level 0, the first output signal Vout output by the data receiving circuit 100 of the previous stage is: That is, the first feedback signal (fbp) of the data receiving circuit 100 of the next stage is low level, and the second output signal (VoutN) output by the data receiving circuit 100 of the previous stage, that is, the data receiving circuit of the next stage The second feedback signal (fbn) at (100) becomes high level. At this time, the first complementary feedback signal (fbpN) becomes a high level, the second complementary feedback signal (fbnN) becomes a low level, the second NMOS transistor (MN2) is turned on, and the fourth NMOS transistor (MN4) is turned on. Additionally, the first amplification module 101 performs the second comparison and outputs the third signal (Sn-) and the fourth signal (Sp-) through the third node (net3) and the fourth node (net4). The second input unit 122 performs a fourth comparison on the third signal (Sn-) and the fourth signal (Sp-) and provides signals to the seventh node (net7) and the eighth node (net8). At this time, no current flows through the first input unit 112.

When the data signal DQ1 received by the data receiving circuit 100 of the previous stage is logic level 0, the data signal DQ2 received by the data receiving circuit 100 of the next stage corresponds to the following two cases. .

Case 3: Referring to Table 1, when the data signal (DQ2) received by the data receiving circuit 100 of the next stage is logic level 0, the data signal (DQ1) received by the data receiving circuit 100 of the previous stage is logic level 0. The difference from the level value is small, and interference between symbols is small or non-existent. At this time, the first amplification module 101 of the data receiving circuit 100 of the next stage performs the second comparison and outputs the third signal (Sn-) and the fourth signal (Sp-), and the second input unit 122 ) turns on. That is, the second amplification module 102 of the next stage data reception circuit 100 receives the third signal (Sn-) and the fourth signal (Sp-).

Case 4: Referring to Table 1, when the data signal (DQ2) received by the data receiving circuit 100 of the next stage is logic level 1, the data signal (DQ1) received by the data receiving circuit 100 of the previous stage is logic level 1. The difference from the level value is large, and there is relatively large interference between symbols. At this time, the first amplification module 101 of the data receiving circuit 100 of the next stage performs the second comparison and outputs the third signal (Sn-) and the fourth signal (Sp-), and the second input unit 122 ) turns on. That is, the second amplification module 102 of the next stage data reception circuit 100 receives the third signal (Sn-) and the fourth signal (Sp-). At this time, in the data receiving circuit 100 of the next stage, the data signal DQ2 is logic level 1, and the voltage difference between the data signal DQ2 and the second reference signal VR1 is equal to the data signal DQ2 and the first reference signal (VR1). It is larger than the voltage difference of VR+). At this time, if the first comparison can be performed, the difference in the level value of the signal of the effective second signal pair obtained by performing the second comparison is the level value of the signal of the effective first signal pair obtained by performing the first comparison. It's bigger than the difference. At this time, the second amplification module 102 may receive a valid second signal pair and output the first output signal (Vout) and the second output signal (VoutN) with higher accuracy. Accordingly, the influence of inter-symbol interference of the data signal DQ on the data receiving circuit 100 can be reduced, and power consumption of the data receiving circuit 100 can be reduced because the second comparison is not performed.

When there is no need to consider the effect of inter-symbol interference on the data reception circuit 100, the enable signal EnDfe is at a low level. At this time, the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned off, the first amplification module 101 constantly performs the first comparison, and the first signal (Sn+) and the second Outputs a signal (Sp+). The first input unit 112 is turned on or off in response to the first signal pair. At this time, the third signal (Sn-) and the fourth signal (Sp-) output by the second comparison circuit 121 are both logic low level signals, and the third signal (Sn-) and the fourth signal (Sp-) In response, the second input unit 122 is turned off.

In the description of the high level and low level above, the high level may be a level value above the power supply voltage, and the low level may be a level value below the ground voltage. Additionally, the high level and low level are relative, and the range of specific level values included in the high level and low level may be determined by the specific device. For example, for an NMOS transistor, the high level refers to the level value range of the gate voltage that can turn the NMOS transistor on, and the low level refers to the level value range of the gate voltage that can turn the NMOS transistor off. . For a PMOS transistor, the low level refers to the level value range of the gate voltage that can turn the PMOS transistor on, and the high level refers to the level value range of the gate voltage that can turn the PMOS transistor off. Additionally, the high level may be the above-described logic level 1, and the low level may be the above-described logic level 0.

In summary, data received by the data reception circuit 100 by additionally controlling the first amplification module 101 using the enable signal (EnDfe), the first feedback signal (fbp), and the second feedback signal (fbn). It is possible to select whether to consider the impact of inter-symbol interference on the data reception circuit 100. For example, when the influence of inter-symbol interference on the data receiving circuit 100 needs to be reduced, that is, in a section where the enable signal (EnDfe) has a first level value, the first amplification module 101 uses the sampling clock Responsive to the first level value of the signal clkN, and performing a first comparison using the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4. and optionally perform one of the second comparisons. Accordingly, one of the first signal pair and the second signal pair is valid and the other is invalid, so that the difference in the level value of the signal of the valid signal pair becomes larger, and the second amplification module 102 determines the level value of the signal. It is possible to receive a pair of differential signals with a larger difference. In addition, the low on-resistance of the NMOS transistor prevents the first amplification module 101 from simultaneously performing the first comparison and the second comparison, and the processing effect of the first amplification module 101 on the data signal DQ And processing speed can be improved. When the effect of inter-symbol interference on the data receiving circuit 100 is not considered, in a section where the enable signal (EnDfe) has a second level value, the first amplification module 101 generates a sampling clock signal (clkN) By performing only the first comparison in response to and fixedly outputting the valid first signal pair, the power consumption of the data receiving circuit 100 can be reduced.

A data reception system according to another embodiment of the present invention is provided. Hereinafter, a data reception system according to another embodiment of the present invention will be described in detail with reference to the attached drawings. Figure 9 is a functional block diagram of a data reception device according to another embodiment of the present invention.

Referring to FIG. 9, the data reception system includes a plurality of data transmission circuits 120 connected in cascade. Each data transmission circuit 120 includes a data reception circuit 100 according to an embodiment of the present invention and a latch circuit 110 connected to the data reception circuit. The output signal of the data transfer circuit 120 of the previous stage becomes the feedback signal (fb) of the data transfer circuit 120 of the next stage, and the output signal of the data transfer circuit 120 of the final stage becomes the data transfer circuit 120 of the first stage. It becomes the feedback signal (fb) of (120).

In some embodiments, the data receiving circuit 100 receives data in response to a sampling clock signal clkN, and the data receiving system includes four data receiving circuits 100 cascaded, with data receiving circuits adjacent to each other. The phase difference of the sampling clock signal clkN of the circuit 100 is 90°. In this way, the period of the sampling clock signal clkN is twice that of the data signal DQ received through the data port, making clock routing easy and power consumption reduced.

FIG. 9 shows an example in which the data reception system includes four data reception circuits 100 connected in cascade, and the phase difference of sampling clock signals of adjacent data reception circuits 100 is 90°. In actual application, the data receiving system is not limited to the number of data receiving circuits 100 connected in cascade, and the phase difference of the sampling clock signal of adjacent data receiving circuits 100 is determined by the number of data receiving circuits 100 connected in cascade. It can be set reasonably based on .

In some embodiments, the first output signal (Vout) and the second output signal (VoutN) output from the second amplification module 102 of the data transmission circuit 120 of the previous stage are the data transmission circuit 120 of the next stage. becomes the feedback signal (fb). In this way, since the output of the data reception circuit 100 is immediately transmitted to the data transmission circuit 120 of the next stage and does not pass through the latch circuit 110, the data transmission delay can be reduced. Alternatively, the signal output by the latch circuit 110 of the previous stage becomes a feedback signal of the data transmission circuit 120 of the next stage.

In summary, the data reception system according to another embodiment of the present invention additionally controls the first amplification module 101 using the enable signal (EnDfe), the first feedback signal (fbp), and the second feedback signal (fbn). By doing so, it is possible to select whether to consider the influence of inter-symbol interference of data received by the data receiving circuit 100 on the data receiving circuit 100. For example, when the influence of inter-symbol interference on the data receiving circuit 100 needs to be reduced, that is, in a section where the enable signal (EnDfe) has a first level value, the first amplification module 101 uses the sampling clock A first comparison or a second comparison is selectively performed in response to the first level value of the signal clkN and in response to the first feedback signal fbp and the second feedback signal fbn. Accordingly, one of the first signal pair and the second signal pair is valid and the other is invalid, so that the difference in the level value of the signal of the valid signal pair becomes larger, and the second amplification module 102 adjusts the level value of the signal. It becomes possible to receive a pair of differential signals with a larger difference. In addition, the low on-resistance of the NMOS transistor prevents the first amplification module 101 from simultaneously performing the first comparison and the second comparison, and the processing effect of the first amplification module 101 on the data signal DQ And processing speed can be improved. When the effect of inter-symbol interference on the data receiving circuit 100 is not considered, in a section where the enable signal (EnDfe) has a second level value, the first amplification module 101 generates a sampling clock signal (clkN) By performing only the first comparison in response to and outputting a fixedly valid first signal pair, the power consumption of the data receiving circuit 100 can be reduced.

A storage device according to another embodiment of the present invention includes a plurality of data ports and a plurality of data receiving systems corresponding to each data port. In this way, when the impact of inter-symbol interference on the storage device must be reduced, each data port of the storage device performs flexible coordination on the data signal (DQ) received through the data reception system, and the first output By increasing the tuning ability for the signal (Vout) and the second output signal (VoutN), the reception performance of the storage device can be improved. When there is no need to consider the effect of inter-symbol interference on the storage device, the first amplification module 101 performs only the first comparison in response to the sampling clock signal clkN and fixedly outputs a valid first signal pair. , the power consumption of the storage device can be reduced.

Those of ordinary skill in the technical field to which the present invention pertains will understand that the above-described embodiments are only specific embodiments for implementing the present invention, and that when applied in practice, they do not exceed the technical spirit and scope of the embodiments of the present invention. You will be able to understand that it can be changed into various forms and specific contents. A person skilled in the art to which the present invention pertains can make various changes and modifications without departing from the technical spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention is defined in the claims. will be decided by

Claims (26)

Receives an enable signal, a first feedback signal, a second feedback signal, a data signal, a first reference signal, and a second reference signal, and responds to a sampling clock signal in a section where the enable signal has a first level value. Select the data signal and the first reference signal based on a first feedback signal and perform a first comparison to output a first signal pair as a result of the first comparison, or respond to the sampling clock signal and provide the second feedback The data signal and the second reference signal are selected based on the signal, a second comparison is performed, a second signal pair is output as a result of the second comparison, and the enable signal has a second level value in a section. Perform the first comparison in response to the sampling clock signal and output a first signal pair, wherein the levels of the first feedback signal and the second feedback signal are opposite to each other, and the first signal pair is the first signal and the second feedback signal. a first amplification module comprising a second signal, the second signal pair comprising a third signal and a fourth signal; and
a second amplification module that receives the output signal of the first amplification module as an input signal pair, amplifies the voltage difference between the input signal pair, and outputs a first output signal and a second output signal as a result of the amplification process; Including,
The first amplification module is,
It has a first node, a second node, a third node, and a fourth node, wherein the first node outputs the first signal, the second node outputs the second signal, and the third node an amplifier that outputs the third signal, the fourth node outputs the fourth signal, and receives the data signal, the first reference signal, and the second reference signal;
a first NMOS transistor whose end is connected to the first node;
a second NMOS transistor having one end connected to the other end of the first NMOS transistor and the other end connected to the second node;
a third NMOS transistor, one end of which is connected to the third node; and
A fourth NMOS transistor, one end of which is connected to the other end of the third NMOS transistor and the other end of which is connected to the fourth node,
A first complementary feedback signal having a level opposite to that of the first feedback signal is received at the gate of one of the first NMOS transistor and the second NMOS transistor, and the enable signal is received at the other gate,
Data reception in which a second complementary feedback signal having a level opposite to that of the second feedback signal is received at the gate of one of the third NMOS transistor and the fourth NMOS transistor, and the enable signal is received at the other gate. Circuit. In claim 1,
The first amplification module is,
A fifth NMOS transistor, one end of which is connected to the first node; and
a sixth NMOS transistor having one end connected to the other end of the fifth NMOS transistor and the other end connected to the second node;
A seventh NMOS transistor, one end of which is connected to the third node; and
It further includes an eighth NMOS transistor, one end of which is connected to the other end of the seventh NMOS transistor and the other end of which is connected to the fourth node,
The first complementary feedback signal is received at the gate of one of the fifth NMOS transistor and the sixth NMOS transistor, and the enable signal is received at the other gate,
A data receiving circuit wherein the second complementary feedback signal is received at the gate of one of the seventh NMOS transistor and the eighth NMOS transistor, and the enable signal is received at the other gate. In claim 2,
The enable signal is received at the gate of the first NMOS transistor,
The first complementary feedback signal is received at the gate of the second NMOS transistor,
The channel width of the first NMOS transistor is larger than the channel width of the second NMOS transistor,
The first complementary feedback signal is received at the gate of the fifth NMOS transistor,
The enable signal is received at the gate of the sixth NMOS transistor,
The channel width of the fifth NMOS transistor is smaller than the channel width of the sixth NMOS transistor,
The enable signal is received at the gate of the third NMOS transistor,
The second complementary feedback signal is received at the gate of the fourth NMOS transistor,
The channel width of the third NMOS transistor is larger than the channel width of the fourth NMOS transistor,
The second complementary feedback signal is received at the gate of the seventh NMOS transistor,
The enable signal is received at the gate of the eighth NMOS transistor,
A data receiving circuit wherein the channel width of the seventh NMOS transistor is smaller than the channel width of the eighth NMOS transistor. In claim 2,
The channel width of the fifth NMOS transistor is the same as the channel width of the second NMOS transistor,
The channel width of the sixth NMOS transistor is the same as the channel width of the first NMOS transistor,
The channel length of the first NMOS transistor, the channel length of the second NMOS transistor, the channel length of the fifth NMOS transistor, and the channel length of the sixth NMOS transistor are the same,
The channel width of the seventh NMOS transistor is the same as the channel width of the fourth NMOS transistor,
The channel width of the eighth NMOS transistor is the same as the channel width of the third NMOS transistor,
A data receiving circuit in which the channel length of the third NMOS transistor, the channel length of the fourth NMOS transistor, the channel length of the seventh NMOS transistor, and the channel length of the eighth NMOS transistor are the same. In claim 1,
The sampling clock signal includes a first sampling clock signal and a second sampling clock signal,
The amplifier unit,
a first comparison circuit including the first node and the second node, receiving the data signal and the first reference signal, and performing the first comparison in response to the first sampling clock signal;
The enable signal and the raw sampling clock signal are received and the second sampling clock signal is output, and the phase of the second sampling clock signal and the raw sampling clock signal are generated in a section in which the enable signal has the first level value. A clock generation circuit where the phases are opposite to each other and the second sampling clock signal is a logic high level signal in a section where the enable signal has the second level value; and
It has the third node and the fourth node, receives the data signal and the second reference signal, and responds to the second sampling clock signal in a section where the enable signal has the first level value. 2 A second comparison circuit that performs comparison and in which the connection path between the third node and the ground terminal and the connection path between the fourth node and the ground terminal are conducted in the section where the enable signal has the second level value. Data receiving circuit including ; In claim 5,
The first comparison circuit is,
a first current source connected between a power node and a fifth node and supplying current to the fifth node in response to the first sampling clock signal;
It is connected to the first node, the second node, and the fifth node, receives the data signal and the first reference signal, and makes the first comparison when the first current source supplies current to the fifth node. a first comparison unit that performs and outputs the first signal and the second signal; and
A first reset unit connected to the first node and the second node and resetting the first node and the second node in response to the first sampling clock signal,
The second comparison circuit is,
A second current source connected between the power node and the sixth node and supplying current to the sixth node in response to the second sampling clock signal:
It is connected to the third node, the fourth node, and the sixth node, receives the data signal and the second reference signal, and performs the second comparison when the second current source supplies current to the sixth node. a second comparison unit that performs and outputs the third signal and the fourth signal; and
A data receiving circuit comprising: a second reset unit connected between the third node and the fourth node, and resetting the third node and the fourth node in response to the second sampling clock signal. In claim 6,
The first current source is,
A first PMOS transistor connected between the power node and the fifth node and receiving the first sampling clock signal through a gate,
The second current source is,
A second PMOS transistor connected between the power node and the sixth node and receiving the second sampling clock signal through a gate,
The first comparison unit,
a third PMOS transistor connected between the first node and the fifth node and receiving the data signal through a gate; and
A fourth PMOS transistor connected between the second node and the fifth node and receiving the first reference signal as a gate,
The second comparison unit,
a fifth PMOS transistor connected between the third node and the sixth node and receiving the data signal through a gate; and
It includes a sixth PMOS transistor connected between the fourth node and the sixth node and receiving the second reference signal as a gate,
The first reset unit,
A ninth NMOS transistor connected between the first node and the ground terminal and receiving the first sampling clock signal through a gate; and
A tenth NMOS transistor connected between the second node and the ground terminal and receiving the first sampling clock signal through a gate,
The second reset unit,
an 11th NMOS transistor connected between the third node and the ground terminal and receiving the second sampling clock signal through a gate; and
A data receiving circuit comprising a 12th NMOS transistor connected between the fourth node and the ground terminal and receiving the second sampling clock signal through a gate. In claim 5,
The clock generation circuit is,
A first NAND gate circuit that receives the raw sampling clock signal through one input terminal, connects the other input terminal to a power node, and outputs the first sampling clock signal through an output terminal,
The clock generation circuit is,
A data receiving circuit comprising: a second NAND gate circuit that receives the raw sampling clock signal through one input terminal, receives the enable signal through another input terminal, and outputs the second sampling clock signal through an output terminal. In claim 1,
The second amplification module,
A first node connected to a seventh node and an eighth node, receiving the first signal pair, performing a third comparison, and providing signals to the seventh node and the eighth node as a result of the third comparison, respectively. input unit;
Connected to the seventh node and the eighth node, receiving the second signal pair, performing a fourth comparison, and providing signals to the seventh node and the eighth node as a result of the fourth comparison, respectively. second input unit; and
It is connected to the seventh node and the eighth node, amplifies and latches the signal of the seventh node and the signal of the eighth node, and transmits the first output signal and the signal through the first output node and the second output node, respectively. It includes a latch unit that outputs the second output signal,
The second amplification module,
A data receiving circuit further comprising a third reset unit connected between a power node and an output terminal of the latch unit and resetting the output terminal of the latch unit. In claim 9,
The first input unit,
a thirteenth NMOS transistor whose drain is connected to the seventh node, whose source is connected to the ground terminal, and whose gate receives the first signal; and
A fourteenth NMOS transistor whose drain is connected to the eighth node, whose source is connected to the ground terminal, and whose gate receives the second signal,
The second input unit,
a 15th NMOS transistor whose drain is connected to the seventh node, whose source is connected to the ground terminal, and whose gate receives the third signal; and
It includes a 16th NMOS transistor whose drain is connected to the eighth node, whose source is connected to the ground terminal, and whose gate receives the fourth signal,
The latch part,
a 17th NMOS transistor whose source is connected to the seventh node, a drain connected to the first output node, and a gate connected to the second output node;
a seventh PMOS transistor whose source is connected to a power node, a drain connected to the first output node, and a gate connected to the second output node;
an 18th NMOS transistor whose source is connected to the eighth node, a drain connected to the second output node, and a gate connected to the first output node; and
An eighth PMOS transistor, the source of which is connected to the power node, the drain of which is connected to the second output node, and the gate of which is connected to the first output node,
The third reset unit,
a ninth PMOS transistor connected between the first output node and the power node and receiving a raw sampling clock signal through its gate; and
A tenth PMOS transistor connected between the second output node and the power node and receiving the raw sampling clock signal through a gate. In claim 1,
a first inverting circuit that receives the first feedback signal and outputs the first complementary feedback signal; and
A data receiving circuit comprising: a second inverting circuit that receives the second feedback signal and outputs the second complementary feedback signal. In claim 11,
The first inverting circuit is,
A third NAND gate that receives the first feedback signal and the enable signal through both input terminals and outputs the first complementary feedback signal to an output terminal, respectively,
The second inverting circuit is,
A data receiving circuit including a fourth NAND gate that receives the second feedback signal and the enable signal through both input terminals, respectively, and outputs the second complementary feedback signal to an output terminal. A plurality of data transmission circuits each including the data reception circuit of any one of claims 1 to 12 and a latch circuit connected to the data reception circuit and connected in cascade,
The output signal of the data transmission circuit of the previous stage is the feedback signal of the data transmission circuit of the next stage,
A data receiving system wherein the output signal of the data transmission circuit of the final stage is the feedback signal of the data transmission circuit of the first stage. In claim 13,
The data receiving circuit is,
Receiving data in response to the sampling clock signal,
The data reception system is,
A data reception system comprising four data reception circuits connected in cascade, wherein a phase difference between the sampling clock signals of adjacent data reception circuits is 90°. In claim 13,
The first output signal and the second output signal output by the second amplification module of the data transmission circuit of the previous stage are the feedback signals of the data transmission circuit of the next stage, or the signals output by the latch circuit of the previous stage A data receiving system wherein is the feedback signal of the data transmission circuit of the next stage. Multiple data ports; and
A storage device comprising: the data reception system of claim 13 corresponding to each of the data ports. delete delete delete delete delete delete delete delete delete delete