WO2009122380A1 - Appareil, système et procédé pour une gestion d'énergie dans des communications inter-processeurs - Google Patents

Appareil, système et procédé pour une gestion d'énergie dans des communications inter-processeurs Download PDF

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Publication number
WO2009122380A1
WO2009122380A1 PCT/IB2009/051424 IB2009051424W WO2009122380A1 WO 2009122380 A1 WO2009122380 A1 WO 2009122380A1 IB 2009051424 W IB2009051424 W IB 2009051424W WO 2009122380 A1 WO2009122380 A1 WO 2009122380A1
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WIPO (PCT)
Prior art keywords
processing element
inter
processor communication
power
power save
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PCT/IB2009/051424
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English (en)
Inventor
Parag Garg
Olaf Hirsch
Steve Shearer
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Nxp B.V.
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Publication of WO2009122380A1 publication Critical patent/WO2009122380A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Definitions

  • a typical Wireless Local Area Network (WLAN) enabled cell phone and PDA systems include at least three processor cores.
  • the three processor cores may exist on three separate chips.
  • These processors generally include a host processor, a WLAN processor, and a Global System for Mobile communication (GSM) processor.
  • the WLAN processor typically manages connectivity to a wireless network through a wireless networking protocol such as IEEE 802.11 (g).
  • the GSM processor typically manages connectivity to a cellular voice or data communication network.
  • the host processor typically manages user inputs, system applications, and operations of the cellular telephone system as a whole. In general there is a substantial volume of communication between the host processor and the connectivity processors.
  • the communication generally includes data traffic and system maintenance traffic.
  • the system maintenance traffic commonly includes requests for link quality, beacon scan requests, higher layer routine traffic, etc.
  • Higher layer routine traffic is typically exchanged using higher layer protocols, such as address resolution protocol (ARP) and dynamic host configuration protocol (DHCP), between the peer entities in station (STA) and access point (AP).
  • Link quality queries and beacon scan requests are usually initiated by the host on a periodic basis.
  • the host may send a management information base (MIB) get/media access control (MAC) sublayer management entity (MLME) query to the connectivity processors.
  • MIB management information base
  • MAC media access control sublayer management entity
  • MLME management entity
  • the system facilitates power management during inter-processor communication.
  • the system includes a memory device, a power manager, a first processing element, and a second processing element.
  • the memory device stores a power save policy to indicate a condition to restrict an inter-processor communication that is capable of causing a processing element to wake from a power save state.
  • the power manager manages the inter-processor communication according to the power save policy and provides an indicator to send the inter-processor communication in accordance with the power save policy.
  • the first processing element includes a first inter-processor communication device to send the inter-processor communication to the second processing element in response to the indicator.
  • the destination processing element includes the second processing element.
  • the second processing element includes a second inter-processor communication device to receive the inter-processor communication from the first processing element.
  • Fig. 1 depicts a schematic diagram of one embodiment of a system for power management in inter-processor communications.
  • Fig. 2 depicts a schematic diagram of another embodiment of a system for power management in inter-processor communications.
  • Fig. 3 depicts a schematic diagram of the first processing element of the power management system of Fig. 1.
  • Fig. 4 depicts a schematic diagram of another embodiment the first processing element of Fig. 3.
  • Fig. 5 depicts a schematic flow chart diagram illustrating one embodiment of a method for power management in inter-processor communications.
  • Fig. 6 depicts a schematic timing diagram of an embodiment of a method for power management in inter-processor communications.
  • Fig. 7 depicts a schematic timing diagram of another embodiment of a method for power management in inter-processor communications.
  • Fig. 8 depicts a schematic timing diagram of another embodiment of a method for power management in inter-processor communications.
  • Fig. 9 depicts a schematic timing diagram of another embodiment of a method for power management in inter-processor communications.
  • Fig. 10 depicts a schematic timing diagram of another embodiment of a method for power management in inter-processor communications. Throughout the description, similar reference numbers may be used to identify similar elements.
  • Fig. 1 depicts a schematic diagram of one embodiment of a system 100 for power management in inter-processor communications.
  • the system 100 includes a memory device 110, a power manager 108, a first processing element 102, and a second processing element 104.
  • the memory device 110 stores a power save policy 112.
  • the power save policy 112 restricts an inter-processor communication 106 that causes one of the processing elements 102 and 104 to wake from a power save state.
  • the power manager 108 is coupled to the memory device 110.
  • the power manager 108 manages the inter- processor communication 106 according to the power save policy 112 and provides an indicator to send the inter-processor communication 106.
  • the power manager 110 provides the indicator in accordance with the power save policy 112.
  • the first processing element 102 is a host processor in a WLAN enabled cell phone.
  • the first processing element 102 hosts cell phone applications and manages user interactions.
  • the first processing element 102 is a GSM processor or WLAN processor.
  • the first processing element 102 may be implemented in an individual chip package.
  • the first processing element 102 may be implemented as a processing core in a multi-core processing device.
  • the second processing element 104 also may be a host processor, a
  • the first processing element 102 is a host processor and the second processing element 104 is a WLAN processor.
  • These various embodiments of the first processor 102 and the second processor 104 may perform a variety of processing functions that facilitate communication between the first processing element 102 and the second processing element 104.
  • a host processor may manage user interaction.
  • the host processor may include connections to a graphical user display and user input controls (not shown).
  • the host processor also generally handles processing of cell phone applications.
  • the host processor hosts a cell phone management application for providing a user display that includes a time indicator, a signal strength indicator, and in certain embodiments a customized background display, a user defined message, and other user display elements.
  • the host processor may also initiate routine measurements, such as link statistics, beacon scans, and other cellular and WLAN specific measurements.
  • a WLAN processor may receive Delivery Traffic Identification Message (DTIM) beacon signals. Additionally, a WLAN processor may receive buffered data packets from a wireless Access Point (AP). In an exemplary embodiment, where the first processing element 102 is a host processor and the second processing element 104 is a WLAN processor, the WLAN processor may communicate the data packets to the host processor. In a further embodiment, the host processor communicates a message to the WLAN processor for communication to the wireless AP. The WLAN processor may then transmit the message to the AP via a Radio Frequency (RF) transmitter. Additionally, the WLAN processor may communicate measurement data, including beacon signal strength, to the host processor in response to a measurement request.
  • RF Radio Frequency
  • the second processing element 104 is a GSM processor.
  • the GSM processor may receive cellular beacon signal data via a RF transceiver.
  • the GSM processor may also transmit requests from the host to the cellular network via the RF transceiver.
  • the GSM processor may communicate voice data to the cellular network.
  • the GSM processor may also communicate routine measurement data to the host processor in response to receiving a measurement request.
  • data may be communicated between the first processing element 102 and the second processing element 104. As described herein, these data communications are inter-processor communications 106.
  • An inter-processor communication 106 may be communicated from the first processing element 102 to the second processing element 104.
  • an inter- processor communication 106 may be communicated from the second processing element 104 to the first processing element 102.
  • a host processor may communicate a measurement request to a WLAN processor.
  • the WLAN processor may respond to the host processor with a measurement value corresponding to signal strength of a beacon signal received from a wireless AP.
  • the measurement request and the response are both inter-processor communications 106.
  • Other types of inter-processor communications also may be implemented.
  • the system 100 may also include a power manager 108.
  • the power manager 108 is coupled to the first processing element 102 and the second processing element 104.
  • the power manager 108 retrieves the power save policy 112 that is stored in the memory device 110.
  • the power save policy 112 defines certain preliminary communication restrictions or conditions before an inter-processor communication 106 can take place.
  • the power save policy 112 may specify that the first processing element 102 may not communicate a measurement request to the second processing element 104 when the second processing element 104 is in a power save (i.e., sleep) state.
  • the power save policy 112 may further specify that once the second processing element 104 wakes from the power save state, the inter-processor communication 106 may be sent.
  • power consumption is reduced by allowing the second processing element 104 to remain in its power save state without interference from the first processing element 102 for a longer duration than in conventional systems.
  • the memory device 110 may include a Random Access Memory (RAM) device, a flash memory device, or other types of data storage devices.
  • Fig. 2 depicts a schematic diagram of another embodiment of a system 114 for power management in inter-processor communications.
  • the system 114 includes the first processing element 102, the second processing element 104, the power manager 108, and the memory device 110 for storing the power save policy 112 as described in Fig. 1.
  • the system 114 of Fig. 2 also includes a scratchpad shared memory device 116.
  • the scratchpad shared memory device 116 is a second memory device, separate from the memory device 110, for storing the power save policy 112.
  • the scratchpad shared memory device 116 is a portion of the memory device 110 designated for scratchpad or mailbox communications between the first processing element 102 and the second processing element 104. If both the first processing element 102 and the second processing element 104 are in a wake state, the inter-processor communication 106 may be communicated directly from the first processing element 102 to the second processing element 104. This type of communication is considered synchronous communication.
  • the inter-processor communication 106 may be temporarily stored in the scratchpad shared memory 116 for communication at a time when the destination processing element is in a wake state. This type of communication is considered asynchronous communication. Certain types of data may be transmitted via a synchronous communication, while others may be transmitted via an asynchronous communication. For example, certain high priority communications such as communication of data between a wireless AP or a cellular network and the host processor typically use synchronous communication. Other inter-processor communications 106 may be performed asynchronously because the data involved is low priority. For example, some communication of measurement requests and measurement results may be carried out asynchronously. The asynchronous communications may be accomplished by storing data associated with the inter- processor communication 106 in the scratchpad shared memory 116 until the second processing element 104 wakes from a power save state and retrieves the data from the scratchpad shared memory 116.
  • the first processing element 102 generates a measurement request to send to the second processing element 104. If the power manager 108 determines that the second processing element 104 is in a power save state, the power manager 108 may provide an indicator to the first processing element 102 indicating that the inter-processor communication 106 should be sent to the scratchpad shared memory 116. An asynchronous communication of the request and the results may be possible, since the request is not a high priority communication.
  • the power save policy 112 may include a list of inter-processor communication types that may be carried out asynchronously.
  • the second processing element 104 may retrieve the measurement request when it wakes from the power save state. In one embodiment, the second processing element 104 checks the scratchpad shared memory 116 for saved messages when it wakes from a power save state. Alternatively, the second processing element 104 may check the scratchpad shared memory 116 in response to a flag or other indicator that the first processing element 102 has stored a message in the scratchpad shared memory 116.
  • Fig. 3 depicts a schematic diagram of one embodiment of the first processing element 102 of the power management system 100 of Fig. 1.
  • the first processing element 102 includes a first inter- processor communication device 120.
  • the system 100 of Fig. 1 and the system 114 of Fig. 2 include the power manager 108 and the memory device 110 as separate components, or distinct modules, the power manager 108 and the memory device 110 are shown as components of the first processing element 102 in Fig. 3.
  • the power manager 108 may be a component of the first processing element 102, and the memory 110 may be a separate device or vice versa.
  • the second processing element 104 may include the power manager 108 and/or memory device 110.
  • the first inter-processor communication device 120 sends the inter- processor communication 106 to the second processing element 104 in response to the indicator provided by the power manager 108.
  • the power manager 108 provides an indicator to the first inter-processor communication device 120.
  • the indicator may trigger the first inter-processor communication device 120 to send the inter-processor communication 106 to the second processing element 104.
  • providing the indicator includes setting a bit in a register associated with the power manager 108 and the first inter-processor communication device 120.
  • the power manager 108 may communicate the indicator by setting a high or low potential level on an input pin (not shown) associated with the first inter-processor communication device 120.
  • the power manager 108 may trigger the first inter-processor communication device 120 using another mechanism.
  • the power manager 108 determines that an inter-processor communication cannot be sent because the second processing element 104 is in a power save state, then the power manager 108 indicates that the inter-processor communication 106 should be buffered in the memory device 110.
  • the inter- processor communication 106 may remain buffered in the memory device 110 until the second processing element 104 wakes from the power save state and the power manager 108 provides the indicator to send the inter-processor communication 106.
  • the inter-processor communication 106 is stored in a dedicated message buffer that is separate from the memory device 110.
  • the inter-processor communication may be stored in the scratchpad shared memory 116.
  • Fig. 4 depicts a schematic diagram of another embodiment the first processing element 102 of Fig. 3.
  • the first processing element 102 includes the memory device 110, the power manager 108 and the first inter-processor communication device 120. Additionally, the first processing element 102 includes a data buffer 130.
  • the memory device 110 includes the power save policy 112, as described above.
  • the power manager 108 includes a schedule manager 122, a timing circuit 124, and a power state awareness circuit 126.
  • the first inter-processor communication device 120 includes an asynchronous mail delivery device 128.
  • the schedule manager 122 generates a schedule for the inter-processor communication 106 in response to schedule data provided by the second processing element 104.
  • the second processing element 104 may periodically transmit sleep/wake schedule information to the first processing element 102 to the power manager 108 directly, if the power manager is external to the first processing element 102.
  • the schedule manager 122 may update or maintain the sleep/wake schedule in response to receiving the sleep/wake schedule information from the second processing element 104.
  • the schedule enables the power manager 108 to continuously determine whether the second processing element 104 is in a power save state or a wake state without querying the second processing element 104 each time a determination of its power save state is required.
  • some embodiments may implement or demand power state inquiries for each inter-processor communication 106.
  • the power manager 108 also includes a timing circuit 124 to receive a shared clock signal.
  • the shared clock signal is common between the power manager 108 and the second processing element 104.
  • the timing circuit 124 provides a timing standard for the schedule manager 122. The timing standard is associated with the shared clock signal so that the schedule manager 122 can maintain an accurate reference to the sleep/wake schedule of the second processing element 104.
  • the power manager 108 also includes a power-state awareness circuit 126.
  • the power-state awareness circuit may communicate with the second processing element 104. In one embodiment, the power-state awareness circuit 126 conducts a handshake operation with the second processing element 104 to verify that the second processing element 104 is not in the power save state before providing the indicator to send the inter-processor communication 106.
  • the power manager 108 does not provide the indicator if it determines that the second processing element 104 is in the power save state.
  • the handshake operation includes receiving a first flag from the second processing element 104. The first flag indicates that the second processing element 104 is not in the power save state.
  • the power state awareness circuit 126 may set a second flag on the second processing element 104 to indicate that the first inter-processor communication device 120 has an inter-processor communication 106 to send to the second processing element 104. If the power state awareness circuit 126 receives a response to the second flag from the second processing element 104, indicating that the second processing element 104 is ready to receive the inter-processor communication 106, then the power manager 108 may provide the indicator to send the inter-processor communication 106.
  • the power manager 108 may include the timing circuit 124 and the schedule manager 122, but not the power state awareness circuit 126.
  • the power manager 108 may include the power state awareness circuit 126, but not the schedule manager 122 or the timing circuit 124.
  • the power manager 108 may include any combination of the timing circuit 124, the schedule manager 122, and the power state awareness circuit 126, depending on the functionality of the first processing element 102.
  • the data buffer 130 is coupled to the first inter- processor communication device 120.
  • the data buffer 130 may store data associated with the inter-processor communication 106 until the power manager 108 provides the indicator to send the inter-processor communication 106 to the first inter-processor communication device 120.
  • the first inter-processor communication device 120 receives the indicator from the power manager, it may retrieve the data associated with the inter-processor communication 106 from the data buffer 130 and transmit it to the second processing element 104.
  • the data buffer 130 operates internally, in some instances, similar to the external scratchpad shared memory 1 16 described above.
  • the asynchronous mail delivery device 128 places the inter-processor communication 106 in the scratchpad shared memory 1 16.
  • the second processing element 104 shares the scratchpad shared memory 1 16 with the asynchronous mail delivery device 128.
  • the second processing element 104 retrieves the inter-processor communication 106 from the scratchpad shared memory 116 in response to waking from the power save state.
  • the power manager 108 may trigger the asynchronous mail delivery device 128 to send the inter-processor communication 106 to the scratchpad shared memory 116 in response to a determination by either the schedule manager 122 or the power state awareness circuit 126 that the second processing element 104 is in a power save state.
  • the memory device 1 10 may store the power save policy 1 12.
  • the power manager 108 then manages the inter- processor communication 106 according to the power save policy 1 12.
  • the power manager 108 then provides an indicator to send the inter-processor communication 106.
  • the first processing element 102 sends the inter-processor communication 106 to the second processing element 104.
  • the first inter-processor communication device 120 of the first processing element 102 sends the inter-processor communication 106 to a corresponding inter-processor communication device of the second processing element 104.
  • Fig. 6 depicts a schematic timing diagram 142 of an embodiment of a method for power management in inter-processor communications.
  • the first processing element 102 and the second processing element 104 share a common clock signal provided by a shared clock generator 144.
  • the first processing element 102 may receive the shared clock signal over a first clock signal connection 146
  • the second processing element 104 may receive the shared clock signal over a second clock signal connection 148.
  • Line 150 represents a progression of time with respect to the first processing element 102
  • line 152 represents a progression of time with respect to the second processing element 104.
  • the depicted embodiment assumes that a power manager 108 is integrated with both the first processing element 102 and the second processing element 104.
  • the first processing element 102 sends a first message 154 containing sleep-wake information for the first processing element 102 to the second processing element 104.
  • the second processing element 104 may prepare a wake schedule 158 associated with the first processing element 102.
  • the second processing element 104 may respond to the first processing element 102 with a second message 160 containing sleep-wake information for the second processing element 104.
  • the first processing element 102 may generate a wake schedule 164 associated with the second processing element 104, at block 162.
  • the schedule manager 122 prepares the wake schedule 164.
  • a schedule manager 122 associated with the second processing element 104 may also generate the wake schedule 158 for the first processing element.
  • the first processing element 102 maintains a schedule 164 of when the second processing element 104 will be in a wake state and available to receive inter-processor communications 106.
  • the first processing element 102 may accurately determine the wake schedule of the second processing element 104 because the timing circuits 124 of the processing element 102 and 104 receive a shared clock signal from the shared clock generator 144.
  • Fig. 7 depicts a schematic timing diagram 166 of another embodiment of a method for power management in inter-processor communications.
  • the first processing element 102 and the second processing element 104 do not receive a shared clock signal from a shared clock generator. Instead, the first processing element 102 and the second processing element 104 may communicate timing information to maintain synchronization with the schedules 174 and 182.
  • Line 196 represents a progression of time with reference to the first processing element 102
  • line 198 represents a progression of time with reference to the second processing element 104.
  • the first processing element 102 sends a message 168 containing sleep-wake information to the second processing element 104. Additionally, the first processing element 102 may send a message 170 containing its free running clock counter value to the second processing element 104.
  • a Timing Synchronization Function (TSF) value is one example of a free running clock counter value as implemented in a WLAN system, although other embodiments may use other types of free running clock counter values.
  • TSF Timing Synchronization Function
  • the second processing element 104 then prepares a wake schedule 174 for the first processing element 102 in response to the sleep-wake information and the free running clock counter value.
  • the second processing element 104 may then respond to the first processing element 102 with a message 176 containing sleep-wake information associated with the second processing element 104. Additionally, the second processing element 104 may send a message 178 containing its free running clock counter value to the first processing element 102.
  • the first processing element 102 may prepare a wake schedule 182 associated with the second processing element 104 based on the message 176 containing sleep-wake information and the message 178 containing its free running clock counter value.
  • the second processing element 104 may continue to transmit messages 184 containing its free running clock counter value to the first processing element 102, so that the timing circuit 124 and the schedule manager 122 can continue to synchronize the wake schedule 182 with the actual sleep- wake cycles of the second processing element 104.
  • the first processing element 102 may include the free running clock counter value with messages 186 sent to the second processing element 104 for the same purpose.
  • the two free running clock counter values are piggybacked, or sent together, with standard communication packets, including data packets received from the wireless AP, measurement queries and responses to measurement queries, and other inter-processor communications 106.
  • the first processing element 102 may periodically send messages 186 and 194 containing the free running clock counter value to the second processing element 104.
  • the second processing element 104 may periodically synchronize 188 the schedule 174 for the first processing element 102 based on the free running clock counter value.
  • the first processing element 102 may periodically synchronize 192 its schedule 182 for the second processing element 104 based on its free running clock counter value.
  • Fig. 8 depicts a schematic timing diagram 200 of another embodiment of a method for power management in inter-processor communications. Primarily, this method illustrates the operation of the data buffer 130. The method includes communications between the first processing element 102 and the second processing element 104.
  • Line 202 represents a progression of time with reference to the first processing element 102
  • line 204 represents a progression of time with reference to the second processing element 104.
  • the first processing element 102 includes a schedule 206 associated with the wake schedule of the second processing element 104.
  • the second processing element 104 may also have a schedule 208 associated with the wake schedule of the first processing element 102.
  • the first processing element 102 may be scheduled to wake periodically for Global System for Mobile communications (GSM) related tasks.
  • GSM Global System for Mobile communications
  • the first processing element 102 may wake for a first GSM activity 222, a second GSM activity 224, and a third GSM activity 226.
  • the GSM activities 222-226 may be schedules at periodic intervals.
  • the second processing element 104 may wake at periodic Target Beacon Transition Times (TBTTs) 210-220.
  • the first processing element 102 may receive data from an application hosted by the first processing element 102 at a data input line 228. In the described embodiment, the first processing element 102 communicates the data to the second processing element 104 in an inter-processor communication 232. If the schedule manager 122 determines that the second processing element 104 is in a power save state, the first processing element 102 may buffer 230 the data in the data buffer 130 until the second processing element 104 wakes at the third TBTT 214. When the second processing element 104 wakes at the third TBTT 214, the first inter-processor communication device 120 may send the data in a data message 232 to the second processing element 104.
  • TBTTs Target Beacon Transition Times
  • the second processing element 104 may generate response data and place it on data line 234. If the schedule manager 122 determines that the first processing element 102 is in a power save state, at loop 236, the second processing element 104 may buffer the response data in a data buffer 130 on the second processing element 104 until the first processing element wakes at the third GSM activity 226. A second inter-processor communication device (not shown) on the second processing element 104 may then send a response message 238 to the first processing element 102. As a result of the data buffering 230 and 236, the power save states of the second processing element 104 and the first processing element 102 remain undisturbed by the inter- processor communications 232 and 238, respectively. Fig.
  • Line 242 represents the power save status of the first processing element 102 with respect to time.
  • a peak 244 in the line 242 represents a wake state.
  • a trough 246 in the line 242 represents a power save state.
  • Line 248 represents the power save status of the second processing element 104 with respect to time.
  • a peak 250 in the line 248 represents a wake state, and a trough 252 represents a power save state.
  • lines 254-258 represent GSM wake events
  • lines 260-268 represent WLAN TBTT events.
  • a GSM wake event 254-258 causes the first processing element 102 to enter a wake state 244, and a WLAN TBTT event 260-268 causes the second processing element 104 to enter a wake state 250.
  • the first processing element 102 generates or receives data for communication to the second processing element 104.
  • the first processing element 102 places the data on the data communication line 270.
  • the power manager 108 determines that the second processing element 104 is in a power save state 252 at the time the data is placed on the connection 270.
  • the first processing element 102 may then buffer 272 the data in a data buffer 130.
  • the first processing element 102 may set a flag 274 indicating that the first processing element 102 has an inter-processor communication 106 to send to the second processing element 104.
  • the second processing element 104 after a routine wake, observes the pending transfer (flag 274) and sends a message 276 to initiate an inter- processor communication 106 and obtain the data from the data buffer 130.
  • the first inter-processor communication device 102 may then transmit a message 278 which includes the buffered data to the second processing unit 104.
  • the message 278 includes a measurement request such as a beacon signal level, a connection indicator, or some other measurement query.
  • the second processing element 104 may generate a response and place the response on a data communication line 280.
  • the power manager 108 may trigger the second processing element 104 to buffer the response data, at loop 282, and set a flag 284 indicating that the response is waiting in the data buffer 130.
  • the first processing element 102 after a routine wake, observes the pending transfer (flag 284) and sends a message 286 initiating an inter-processor communication 106, and the second processing element 104 communicates a message 288 containing the buffered response data to the first processing element 102.
  • the second processing element 104 may communicate data received from a wireless AP or some other data received or generated by the second processing element 104.
  • Fig. 10 depicts a schematic timing diagram 290 of another embodiment of a method for power management in inter-processor communications.
  • the depicted embodiment illustrates an asynchronous communication of inter-processor communications 106 using the scratchpad shared memory 116.
  • Line 292 represents the sleep-wake cycle of the first processing element 102
  • line 294 represents the sleep-wake cycle of the second processing element 104.
  • arrow 304 represents data associated with an inter-processor communication 106 that is received or generated by the first processing element 102.
  • the first processing element 102 may communicate the inter- processor communication 106 to the scratchpad shared memory 1 16.
  • Arrow 306 represents this communication.
  • the second processing element 104 When the second processing element 104 is in a wake state 300, it may retrieve the inter-processor communication 106 from the scratchpad shared memory 1 16. This transaction is represented by arrow 308. Similarly, on a subsequent wake state 300, the second processing element 104 may place an inter-processor communication 106 in the scratchpad shared memory 1 16. This transaction is represented by arrow 310. When the first processing element 102 is in a wake state 296 it may retrieve the inter-processor communication 106 from the scratchpad shared memory 1 16. This transaction is represented by arrow 312. Finally, the inter-processor communication 106 may be communicated to an application or to the user. This transaction is represented by arrow 314.
  • embodiments may consume less processing and communication overhead than the other embodiments. For example, embodiments may omit handshaking and schedule maintenance. Each message is simply placed in the scratchpad shared memory 116, and the destination processing element may retrieve it when convenient.
  • the operations of the method(s) herein are shown and described in a particular order, the order of the operations of each method may be altered so that certain operations may be performed in an inverse order or so that certain operations may be performed, at least in part, concurrently with other operations.
  • instructions or sub-operations of distinct operations may be implemented in an intermittent and/or alternating manner.

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  • Power Sources (AREA)

Abstract

L'invention porte sur un système et sur un procédé pour une gestion d'énergie dans des communications inter-processeurs. Le système comprend un dispositif de mémoire, un gestionnaire d'énergie, un premier élément de traitement et un second élément de traitement. Le dispositif mémoire stocke une politique d'économie d'énergie pour indiquer une condition pour limiter une communication inter-processeur qui est capable d'amener un élément de traitement à s'éveiller à partir d'un état d'économie d'énergie. Le gestionnaire d'énergie gère la communication inter-processeur selon la politique d'économie d'énergie et fournit un indicateur pour envoyer la communication inter-processeur conformément à la politique d'économie d'énergie. Le premier élément de traitement comprend un premier dispositif de communication inter-processeur pour envoyer la communication inter-processeur au second élément de traitement en réponse à l'indicateur. L'élément de traitement de destination comprend le second élément de traitement. Le second élément de traitement comprend un second dispositif de communication inter-processeur pour recevoir la communication inter-processeur à partir du premier élément de traitement.
PCT/IB2009/051424 2008-04-03 2009-04-03 Appareil, système et procédé pour une gestion d'énergie dans des communications inter-processeurs WO2009122380A1 (fr)

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USRE49591E1 (en) 2013-12-16 2023-07-25 Qualcomm Incorporated Power saving techniques in computing devices

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JP2001051756A (ja) * 1999-07-28 2001-02-23 Internatl Business Mach Corp <Ibm> コンピュータのパワーオン方法及びコンピュータ
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US20050166077A1 (en) * 2003-12-31 2005-07-28 Olivier Reisacher Method for reactivating an autonomous computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE49591E1 (en) 2013-12-16 2023-07-25 Qualcomm Incorporated Power saving techniques in computing devices
USRE49652E1 (en) 2013-12-16 2023-09-12 Qualcomm Incorporated Power saving techniques in computing devices

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