WO2009118587A1

WO2009118587A1 - Phase lock loop circuit

Info

Publication number: WO2009118587A1
Application number: PCT/IB2008/051095
Authority: WO
Inventors: Niall Kearney; Norman Beamish; Declan Carey; Lawrence Connell; Shane Doyle; Mark Kirschenmann; Michelle Mcsweeney; Aidan Murphy; Mahibur Rahman; Claudio Rey; Curtiss Roberts; Daniel B Schwartz
Original assignee: Freescale Semiconductor, Inc.
Priority date: 2008-03-25
Filing date: 2008-03-25
Publication date: 2009-10-01

Abstract

A Phase Locked Loop (PLL) circuit (2) comprises a phase detector arrangement (8, 10) having a first input for receiving a reference signal, a second input and an output (13) for providing a control signal, and a voltage controlled oscillator (VCO) arrangement (3). The VCO arrangement (3) includes a VCO (4) having a first input (5) for receiving the control signal, a second input (11 ) and an output (7) for providing an output signal having a frequency dependent on the control signal. The output of the VCO (4) is coupled to the second input of the phase detector arrangement (8, 10) via a feedback path. The VCO arrangement (3) further includes a control circuit (6) for receiving the control signal and being coupled to the second input (11 ) of the VCO (4). The control circuit (6) is arranged in operation to provide an adjustment signal to the VCO (4) selectively and in dependence on a level of the control signal such that the level of the control signal is adjusted to maintain the control signal within a predetermined operating range.

Description

PHASE LOCK LOOP CIRCUIT

Field of the Disclosure

This disclosure relates to a Phase Locked Loop (PLL) circuit.

Background

Phase Locked Loop (PLL) circuits are used widely in radio, computers and other electronic applications. For example, PLL circuits are used in radio communication applications for synchronization purposes, to demodulate frequency-modulated signals, FSK modulation and to synthesize new frequencies. PLL circuits are well known, and include a phase detector, loop filter, Voltage Controlled

Oscillator (VCO) and a feedback path often including a frequency divider. The phase detector generates an error signal proportional to the phase difference between the phase of a reference signal and the output of the feedback path. This error signal is applied to the loop filter which generates a voltage signal (Vtune) applied to a tuning port of the VCO. The negative feedback action of the loop forces the error signal to be substantially constant (in the case of an unmodulated or unperturbed steady state). In this state, the loop is said to be "locked", and the frequency of the signal at an output of the VCO will be related to the frequency of the reference signal applied to the phase detector by the feedback factor (in the case of a feedback divider with a division ratio N, the frequency of the VCO output signal (f_Vco) will be N times the frequency of the reference signal (W)).

VCO's may be realised in many forms. A popular topology widely employed in state of the art CMOS System On Chip (SOC) architectures is the LC oscillator, wherein typically inductive and capacitive elements are connected in the feedback path of an amplifier. This type of LC oscillator circuit is typically employed to realise a low cost solution for the operating frequency and stringent phase noise requirements required for Local Oscillator (LO) signal generation in SOC architectures for GSM/UMTS transceivers, for example. The circuit is usually designed to sustain oscillation at a frequency closely approximated by:

1 ω = , =

where L is inductance and C is the effective capacitance of the resonating circuit or "tank" circuit of the LC oscillator circuit.

Due to the difficulties of realising variable inductances in high-Q integrated oscillators, tunability is usually achieved by employing voltage variable capacitance (VVC) devices (otherwise known as varactors) such that they comprise a portion of the total resonating capacitance C in the tank circuit. Several devices are typically available in standard CMOS/BiCMOS processes to function as WCs. Examples of these include p-n junction diodes, MOS capacitors, and MOS transistors. In p- n junction diodes, a depletion region is formed when a reverse bias is applied, resulting in a terminal capacitance which is dependent on the magnitude of the reverse voltage applied. In a MOS capacitor, the terminal capacitance also changes depending on the applied bias, the capacitance being a maximum when the region below the gate region is accumulated, and a minimum when the region is depleted. Similarly, a MOS transistor device may be employed with similar behaviour to the MOS capacitor device, but with the additional option of biasing the device such that the channel beneath the gate region is inverted, resulting in a terminal capacitance usually several times that of when the channel is depleted. Each of these VVC devices exhibit the property that the capacitance between the terminals of the device is responsive to the bias voltage applied, thus providing a mechanism by which the oscillation frequency of an oscillator incorporating a resonating tank circuit having one or more of such WC devices can be electronically tuned. An example capacitance-voltage (C-V) characteristic of a VVC device is shown in FIG. 1.

When a OV bias is applied, the device exhibits a maximum capacitance, and when a high bias voltage (usually limited to supply voltage Vdd) is applied, a minimum capacitance is exhibited. While it is possible to have a VVC device with a characteristic which is opposite in nature, the following description, including the description of the embodiments of the disclosure, will assume the VVC devices have a characteristic as shown in FIG. 1.

It is well known that the terminal capacitance of such VVC devices exhibits temperature dependence, and this in turn induces a temperature sensitivity in the oscillation frequency of a VCO in which they are incorporated. Indeed other factors may additionally contribute to the temperature dependence of the oscillator frequency, such as the temperature dependent behaviour of the amplifier, the load to which the oscillator is connected, as well as other circuit elements present in the design.

In a PLL design, there are usually several factors which combine to limit the range of voltage over which the tuning voltage signal applied to the tuning port of the VCO may operate while maintaining the locked condition of the PLL circuit. The supply voltage usually limits the absolute operating range, and the trend particularly in battery powered mobile devices is for circuitry to operate from increasing lower unipolar voltages.

Furthermore, the phase detector error signal is typically generated and applied to the loop filter by a current mode charge pump or a voltage mode XOR gate. In a charge pump design, for example, the average tuning voltage must be kept within an appropriate range such that sufficient bias voltage is maintained across the devices comprising the switched current sources to maintain operation in the forward active region. Furthermore, in voltage mode designs involving phase detector architectures such as an XOR gate, sufficient linearity of the detector may be guaranteed over only a portion of the available tuning voltage range due to device nonlinearities. Several schemes such as digital or "coarse" tuning a VCO are well known in the literature to guarantee by design that the tuning voltage will lie within the desired operating window when the loop is initially locked. However, in the presence of temperature variations which tend to cause the oscillator frequency to shift, the negative feedback action of the PLL circuit will attempt to compensate by adjusting the tuning voltage signal to maintain lock at the correct frequency. If the temperature changes are sufficiently large to cause the tuning voltage signal to be adjusted beyond the limits for proper circuit operation, phase noise and spurious performance may degrade or catastrophic loss of lock may occur. Thus, in applications such as the third generation of mobile phone standards and technology (3G), which require the PLL to maintain lock for an indefinite period of time, robust temperature compensation is required to ensure that the tuning voltage signal remains in an allowable voltage range.

An article entitled 'A Digitally Temperature Compensated Compact PLL Module' by T Kobayashi, H Iwamoto and T Hara, 1997 IEEE International Frequency Control Symposium (0- 7803-3728-X/97) describes a PLL module with high free-running frequency accuracy over a wide temperature range. The PLL module uses a crystal oscillator VCO and an EEPROM, addressed by a digital temperature sensor, to store a look-up table including an offset voltage in digital form for each digital temperature which offset voltages are then appropriately added to the tuning voltage signal at the input of the VCO via a Digital to Analog Converter (DAC) to compensate for temperature effects. By adding the offset voltages to the tuning voltage signal, the dynamics of the PLL module, for example, the PLL bandwidth, are affected by the offset voltages which is undesirable. In addition, the temperature behaviour of the VCO of the PLL module needs to be pre-characterised and programmed into the VCO (e.g. in the factory) which adds additional complications and cost to manufacturing such a PLL module.

An article entitled 'A Temperature-Compensated CMOS LC-VCO' by T Tanzawa, H. Shibayama, R. Terauchi, K. Hisano, H Ishikuro, S Kousai, H Kobayashi, H Majima, T Takayama, K Agawa, M Koizumi and F. Hatori, IEEE 2004 Custom Integrated Circuits Conference (0-7803-8495- 4/04) describes a LC-VCO arrangement in which a temperature dependent bias voltage is developed within the VCO to reduce the temperature dependence of the tuning characteristics. Resistors coupled to the varactors in the LC tank array are used to provide the inverse temperature dependent bias voltage to compensate for the temperature variations in the VCO. Since this arrangement relies on adding components to introduce an inverse temperature dependent bias voltage, such an arrangement is highly sensitive to the manufacturing process used, the supply voltage and component mismatch. Furthermore, such an arrangement is complex to set up since the required compensating bias voltage has to be determined for the process used. In addition, it can be hard to achieve robust temperature compensation with the arrangement described in this article for VCOs having a wide frequency tuning range of operation (the temperature coefficient of a VCO can vary substantially over wide tuning ranges). Summary

The present invention provides a Phase Lock Loop (PLL) circuit as described in the accompanying claims.

Specific embodiments of the invention are set forth in the dependent claims. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

Brief description of the drawings

Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.A PLL circuit in accordance with the present disclosure will now be described, by way of example only, with reference to the accompanying drawings in which:

FIG. 1 is a graphical representation of a capacitance versus bias voltage characteristic of a voltage variable capacitor device; FIG. 2 is a block schematic diagram of an example of a PLL circuit in accordance with an embodiment of the disclosure;

FIG. 3 is a block schematic diagram of an example of a control circuit suitable for the VCO arrangement of FIG. 2;

FIG. 4 is a schematic circuit diagram of a part of the VCO arrangement of FIG. 2; FIG. 5 is a flow diagram illustrating an example of a method of adjusting the control voltage

Vtune in accordance with an embodiment of the disclosure to provide temperature compensation by varying the capacitance of the compensation array of the VCO arrangement shown in FIG. 4;

FIG. 6 is a graphical representation of the variation of the voltage level of the control signal Vtune with frequency of the signal at the output of the VCO at different temperatures; FIG. 7 is a graphical representation of the control signals applied to different elements of

FIG. 4 during a decrement mode shown in FIG. 5;

FIG. 8 is a graphical representation showing the effects of the temperature compensation process in accordance with an embodiment of the disclosure on the variation of the voltage level of the control signal Vtune with frequency of the signal at the output of the VCO; FIG. 9 is a graphical representation of the control signals applied to different elements of

FIG. 4 during a increment mode shown in FIG. 5; and

FIG. 10 is a graphical representation of the variation of the voltage level of the control signal Vtune over time. Detailed description of the drawings

Referring firstly to FIG. 2, a PLL circuit 2 in accordance with an embodiment of the disclosure comprises a VCO arrangement 3, a phase detector arrangement and a feedback path coupled between an output of the VCO arrangement 3 and the phase detector arrangement. In the embodiment shown in FIG. 2, the phase detector arrangement comprises a phase detector 8 and a loop filter 10 coupled between the output of the phase detector 8 and the VCO arrangement 3 and the feedback path includes a feedback divider 12. The VCO arrangement 3 includes a VCO 4. The

VCO arrangement 3 may have a control circuit 6 for maintaining the voltage level of the control signal Vtune within a predetermined operating range in the presence of changes in ambient temperature and supply voltage and process variations.

The VCO 4 has a first input 5 for receiving a control signal Vtune, a second input 1 1 for receiving an adjustment signal and an output 7 for providing an output signal having a frequency f_out which frequency is dependent on the control signal Vtune. The control circuit 6 has an input 9 coupled to receive the control signal Vtune and is coupled to the second input 1 1 of the VCO 4. The phase detector 8 has a first input for receiving a reference signal having a frequency f_ref, a second input coupled to the output of the feedback divider 12 and an output 13 for providing a phase error signal to the loop filter 10 The loop filter 10 converts the phase error signal into the control signal Vtune.

In an embodiment, the phase detector 8 is a phase/frequency detector (PFD) with a charge pump output. However, the disclosure is not limited to PFD/charge pump phase detectors. Alternatively, the phase detector 8 may for example be an XOR gate or Set-Reset flip flop or equivalent type of phase detector.

The control circuit 6 is arranged to provide selectively an adjustment signal to the VCO 4 in dependence on a level of the control signal Vtune such that in operation the level of the control signal Vtune is adjusted to maintain the level of the control signal within a predetermined operating range and phase/frequency lock is preserved.

In an embodiment, the VCO 4 includes, for example in the resonating tank circuit of the VCO, a compensation array 44 of capacitor elements 46 having a variable capacitance and in operation, the VCO arrangement 3 is arranged to adjust the variable capacitance of the compensation array 44 based on the adjustment signal provided by the control circuit 6 such that the level of the control signal Vtune is adjusted. This allows for the control signal Vtune to be adjusted to compensate for temperature variations. The result is that capacitance is added or subtracted in the resonating tank circuit of the VCO 4 such that the negative feedback action of the PLL circuit 2 will adjust the control signal Vtune in a desired direction. There will be a transient impact on the VCO output signal caused by the action of this change in capacitance. The magnitude of this transient is controlled by limiting the amount of capacitance change that may occur at any one adjustment or compensation event. The transient impact must be controlled closely depending on the target application: for example where the VCO output signal 7 is used in the generation of transmit carrier signal for a 3G mobile device. Specifications exist for the magnitude of phase shift in the carrier signal within given time measurement windows. Details of the compensation array will be provided below.

In an embodiment, the control circuit 6 is arranged to determine when, for example, temperature variations cause the control signal Vtune to reach a predetermined voltage level and to provide an adjustment signal to the VCO 4, in response to determining that the control signal Vtune reaches the predetermined level, by means of input 11 in order to maintain the control signal Vtune within a desired range of operating voltage. For example, the control circuit 6 determines when the level of the control signal Vtune is greater than a first predetermined level and in response provides a first adjustment signal to adjust the level of the control signal Vtune in a first direction (e.g. by subtracting capacitance) and determines when the level of the control signal is less than a second predetermined level and in response provides a second adjustment signal to adjust the level of the control signal Vtune in a second direction, (e.g. by adding capacitance). Thus, the first and second predetermined levels define the predetermined operating range of the control signal Vtune.

In an embodiment, the control circuit 6 additionally determines when the level of the control signal Vtune reaches a third predetermined level. When the level of the control signal Vtune exceeds the first or second predetermined levels due to temperature variations, the control circuit 6 instigates the appropriate corrective adjustment or compensation to be made to the tank capacitance, this adjustment being continued until the level of the control signal Vtune reaches the third predetermined level thereby signalling the completion of the adjustment or compensation process as the control signal Vtune voltage is now at the third predetermined level. The third predetermined level is selected so as to be substantially in the middle of the predetermined operating range as defined by the first and second predetermined levels. By means of example, the different predetermined levels in a CMOS design are set by the positive supply voltage, Vdd, and the bias limits for the current sources comprising a charge pump phase detector output operating between the Vdd potential and ground (OV). With an available supply voltage of 1.4V, 30OmV might typically be allowed as minimum drain-source saturation voltage for sufficiently linear operation. In this example therefore, it is desirable that the control signal Vtune voltage remains between 0.3V and 1.1V, with a nominal operating level in the middle of this range at 0.7V. Allowing for tolerances and margin for robust operation, the second and first predetermined levels might be set to 0.45V and 0.95V respectively, with a mid range level of 0.7V. Thus, the desired operating range for Vtune is 0.7V +/- 0.25V. By limiting the predetermined operating range, the PLL circuit 2 in accordance with the embodiment of the disclosure can avoid issues such as degraded phase detector linearity resulting in increased noise and/or spurious signals at the output of the PLL circuit, or indeed catastrophic loss of lock. In the example given above, the third predetermined level is selected to be Vdd/2 or 0.7V. Thus, the control circuit 6 in accordance with an embodiment of the disclosures provides adjustment signals when the predetermined operating range is exceeded to return the control signal Vtune to 0.7V, substantially the centre of the predetermined operating range, which ensures that the control signal Vtune does not get close to the supply voltages and cause the PLL output to suffer from the above referenced problems.

Referring now also to FIG. 3 which shows more details of the control circuit 6 in accordance with an embodiment of the disclosure.

The control circuit 6 comprises a buffer circuit 20 coupled to the input 9 to receive the control signal Vtune. The purpose of this block 20 is to provide isolation between the subsequent level detector arrangement 22 and the first input 5 of the VCO 4 which is the sensitive VCO tuning input port.

The level detector arrangement 22 is arranged to detect when the voltage level of the control signal Vtune exceeds the predetermined operating range defined by a first and a second predetermined level and comprises at least two comparators 24, 26. A first comparator 24 has a first input coupled to receive the output signal 27 from the buffer circuit 20, which is the buffered control signal, and a second input coupled to receive a first reference voltage signal having the first predetermined level. A second comparator 26 has a first input coupled to receive the output signal 27 from the buffer circuit 20 and a second input coupled to receive a second reference voltage signal having the second predetermined level. The outputs of the first 24 and second 26 comparators are coupled to control logic 30. In the embodiment shown in FIG. 3, the comparator arrangement 22 further comprises a third comparator 28 having a first input coupled to receive the output signal 27 from the buffer circuit 20 and a second input coupled to receive a third reference voltage signal having the third predetermined level. The output of the third comparator 28 is coupled to control logic 30. The third comparator 28 operates to return the control signal Vtune to substantially the centre of the predetermined operating range and is used to implement hysteresis in the level detector arrangement 22. Generation of the reference voltage signals may be achieved with resistive potential dividers between known potentials or by other known means. The digital outputs of the three comparators 24, 26, 28 are latched on the rising edge of a clock signal 29 generated by control logic 30 and provided to control logic 30 which may be implemented as a digital state machine.

The control logic 30 decodes the three bit digital output from the level detector arrangement 22 and implements the steps of the temperature compensation process in accordance with an embodiment of the disclosure which steps are shown in FIG. 5.

The control logic 30 interprets the digital output signals and in response controls the generation of an adjustment signal V_TC via a signal generator 32 to be applied to the second input

11 of the VCO 4. The signal generator 32 is arranged to generate an adjustment signal having one of a plurality of different voltage levels. The voltage level of the generated adjustment signal is determined by the signals on a control bus 35. In an embodiment, the signal generator 32 is a Digital-Analog-Converter (DAC) 32. This will be described in more detail below with reference to FIG. 4 which provides more details as to how the control circuit 6 in accordance with an embodiment of the disclosure generates the adjustment signals at the output 38 of the DAC 32 and applies them to the VCO 4. The control logic 30 further provides switch control signals to the VCO 4 via control bus 33.

As shown in FIG. 4, the DAC 32 comprises a potential divider having a plurality of resistors 34 connected in series between a supply voltage Vdd and ground, and a plurality of switches 36 coupled between nodes 40 positioned along the serially connected resistors 34 and an output 38 of the DAC 32. Each of the plurality of switches 36 comprises a MOSFET device having a gate electrode coupled to the control logic 30 via the control bus 35. By controlling the signals applied to the switches 36 via control bus 35, the voltage level of the signal at the output 38 can be varied by the control logic 30 between 0 and Vdd by coupling different tap positions (nodes 40) to the output 38. In an embodiment, the signals are applied to the switches 36 in sequence along the plurality of resistors 34 so that the voltage level of the adjustment signal at the output 38 is varied (increased or decreased) in steps, the step size being determined by the number of resistors 34 which form the tapped potential divider structure. This arrangement is one example of a simple implementation of a DAC; many alternative implementations are known and may be used.

In an embodiment, VCO 4 is a differential LC oscillator having a compensation array 44 of capacitor elements 46, an inductor element 51 and a block 50 which includes a tuning array of capacitor elements associated with the tuning of the LC oscillator along with the active circuitry required for sustaining oscillation. The compensation array 44 is arranged to adjust the oscillator frequency response in the presence of temperature variations. The compensation array 44 comprises an array of capacitor elements 46 with each capacitor element 46 comprising two voltage variable capacitors VVCs 48 in a differential arrangement. A centre tap or bias control node between the two variable capacitors 48 of each capacitor element 46 is coupled to the output 38 of the DAC 32 via a switching circuit 52 and a filter and pre-charge circuit 42. In another embodiment, the filter and pre-charge circuit 42 may be omitted. Although only three capacitor elements 46 are shown in FIG. 3, it will be appreciated that the compensation array 44 may include a plurality of capacitor elements 46. The capacitor elements 46 in the compensation array 44 are arranged in an array ranging from a capacitor element 46 designated as the Most Significant Bit (MSB) to a capacitor element 46 designated as the Least Significant Bit (LSB). The tuning array of capacitor elements in block 50 includes the variable capacitors coupled to receive the control signal Vtune so as to perform the 'normal' tuning of the VCO 4.

While VCO 4 has been described as a differential LC oscillator, it should be appreciated that the adjustment mechanism or temperature compensation process can equally be applied to a wide range of oscillator topologies, be they differential or single ended. Also, while an inductor element 51 is shown, some other arrangement exhibiting a reactance which is proportional to frequency at the operating frequency could be employed (for example a transmission line stub). Indeed, the adjustment mechanism may be employed in any oscillator wherein a varactor may be coupled in the circuit to tune the oscillating frequency - this would also include "ring" oscillator topologies wherein a varactor can be used to adjust the delay associated with an individual stage comprising the ring topology thereby providing the mechanism for electronically tuning the oscillation frequency. The filter and pre-charge circuit 42 includes an RC filter 54 and associated pre-charge

MOSFET devices 56. The purpose of this circuit 42 is to smooth the switching waveform output signal from the DAC 32 which may otherwise cause disturbance in the PLL circuit 2. The precharge devices 56 may be employed to overcome the time constant associated with the RC filter 54 when setting the DAC 32 to 0 or Full Scale (FS) corresponding to output levels of OV and Vdd respectively. For each capacitor element 46, the switching circuit 52 comprises a transmission gate 58 coupled to the output of the DAC 32 and first 60 and second 62 MOSFET devices. The operation of the MOSFET devices 56, transmission gates 58 and first 60 and second 62 MOSFET devices are controlled by switch control signals from the control logic 30 via control bus 33. In the embodiment shown in FIG. 4, the first device 60 is a PMOS device and the second device 62 is a NMOS device.

When a PMOS device 60 is operated in its ON state (S_Hιgh asserted), it is used to selectively tie the bias control node of the capacitor element 46 to which it is coupled to Vdd. In this condition the capacitor element 46 is operating in its minimum capacitance state. When a PMOS device 60 is operated in its OFF state (S_Hιgh deasserted), it does not control the bias control node of the capacitor element 46 to which it is coupled. When an NMOS device 62 is operated in its ON state (S_LOW asserted), it is used to selectively tie the bias control node of the capacitor element 46 to which it is coupled to Ground. In this condition the capacitor element 46 is operating in its maximum capacitance state. When an NMOS device 62 is operated in its OFF state (S_Lθw deasserted), it does not control the bias control node of the capacitor element 46 to which it is coupled. When a transmission gate 58 of a capacitor element 46 is operated in its ON state (S_Actlve asserted), the signal at the output 38 of the DAC 32 is coupled to the bias control node of the capacitor element 46. When transmission gate 58 is operated in its OFF state (S_Actιve deasserted), the signal at the output 38 of the DAC 32 is decoupled from the bias control node of the capacitor element 46. An example of a method or process for adjusting the level of the control signal Vtune to compensate for temperature variations will now be described with further reference to FIG. 5 which includes details of the operation of the control logic 30. The following description refers to a compensation array 44 of K capacitor elements 46, with each capacitor element being substantially the same. Prior to the start of standard PLL locking, the control logic 30 is in an "Initialise" state, block

500. At this point, the control logic 30 applies appropriate switch control signals to the switching circuit 52 and switches 36 such that the capacitor elements [1 :(K/2)] of the compensation array 44 have a bias voltage of Vdd applied to them, and the capacitor elements [(K/2+1 ):K] have a bias voltage of OV applied to them. Thus, when standard PLL locking is initiated, half of the compensation array 44 of capacitor elements 46 are in C_m,_n state, and half are in C_max state - this is effectively mid scale in a thermometer code as each capacitor element is the same

In an alternative embodiment, each of the capacitor elements 46 of the compensation array 44 of the VCO 4 may be different - for example a binary weighted sizing scheme may be used. However, an advantage of having all the capacitor elements 46 of the compensation array 44 the same is that monotonic tuning behaviour can be obtained by design and large undesired capacitance changes are avoided at major code transitions, as can result from component and parasitic mismatch effects. After standard PLL locking has occurred, the control logic 30 enters an "Idle" state, block

502. The transition into this state may simply be governed by a timeout counter operation based on the known maximum PLL locktime, or for example it may be triggered by a lock detect circuit (not shown) - many examples of which are known. The control logic 30 keeps track of the thermometer code determining how many of the compensation array 44 units are in maximum and minimum capacitance states: the i-th code corresponds to all elements [1 :i] being in minimum capacitance state, and all elements [i+1 :K] being in maximum capacitance state. In other words, the capacitor elements 46 in the compensation array provide a thermometer coded array with the switch control signals on control bus 33 determining the position, along the thermometer coded array, of the capacitor element whose capacitance is to be varied. By means of example, a representation of a VCO voltage-frequency tuning curve 600 for the case of a PLL circuit initially locked to a target frequency f₀ at temperature T₁ is illustrated in FIG. 6, with the control signal Vtune in lock being close to the centre of the desired operating range. Consider a temperature change to T₂, which has the effect of shifting the tuning curve to curve 602 such that the negative feedback action of the feedback path in the PLL circuit causes the control signal voltage to shift lower in value to maintain phase and frequency lock. The control circuit 6 in accordance with an embodiment of the disclosure is arranged to generate an adjustment signal to compensate for this shift in the control signal voltage by adding capacitance into the VCO tank circuit, in response to which the negative feedback action of the PLL will cause the control signal Vtune to increase. In the embodiment shown, this is achieved by decrementing thermometer code i such that more capacitor elements 46 of the compensation array 44are in maximum capacitance state. In order to avoid excessively large transients in the PLL circuit 2 by a Vdd to OV bias adjustment on the i-th capacitor element 46 in the compensation array 44, the DAC 32 is employed to effectively interpolate in a step wise manner between the Vdd and OV. This is achieved by starting at Full Scale (FS) DAC code which corresponds to a voltage of Vdd at the output 38 of the DAC 32 and decrementing it over a period of time to OV.

Thus, if the control signal Vtune shifts enough to reach the second predetermined level, level 2 in FIG. 6, this will be detected by the level detector arrangement 22 (block 504), and the control logic 30 will interpret this, and move to a "Decrement" mode state, block 506. On entering the decrement mode state, the control logic 30 first checks if the present DAC setting value is OV, block 508; if it is not, then the DAC setting will decrement, block 510, by the control logic 30 applying appropriate switch signals sequentially to the switches 36. If the DAC setting is OV, the control logic 30 must move to transitioning the (i-1 )-th capacitor element of the compensation array 44. To do this, a "make before break" operation is performed on i-th capacitor element in order to tie the bias control node to OV so that the DAC output 38 may be removed without causing a disturbance on the i-th capacitor element bias control node. While the DAC 32 is connected to the i-th capacitor element of the compensation array 44, the S_actIVe signal of the transmission gate 58 associated with the i-th capacitor element of array 44 will already be asserted, the signal S_tovι will be deasserted (NMOS device 62 of the switches associated with the i-th capacitor element of compensation array 44 will be OFF) and the signal S_hιgh will also be deasserted (PMOS device 60 of the switches associated with the i-th capacitor element of compensation array 44 will be OFF). To perform the "make before break" transition, the signal S|_0W will be asserted (NMOS device 62 of the switches associated with the i-th capacitor element of compensation array 44 will now be ON). At this point, both the DAC 32 and pull down NMOS device 62 will hold the bias control node of the i-th capacitor element of compensation array 44 at OV or maximum capacitance state, block 512. Now it is possible to deassert the S_actιve signal of the transmission gate 58 associated with the i-th capacitor element of compensation array 44, and the DAC output is now decoupled from the input 11 of the VCO 4 and does not influence VCO tuning. This corresponds to block 514. The thermometer code tracking the state of the capacitor elements in the compensation array 44 can now be decremented to i-1. This corresponds to block 516. While disconnected, the DAC can be set to FS code, or Vdd output level, in preparation for being connected to the (i-1 )-th capacitor element of the compensation array 44, block 518. A make before break connection must again be made to connect the DAC output to the (i-1 )-th capacitor element. Prior to this operation, the signal S_hi_gh of the switches associated with the (i-1 )-th capacitor element of compensation array 44 will be asserted (PMOS device 60 of the switches associated with the (i-1 )-th capacitor element of compensation array 44 will be ON), the signal S|_0W of the switches associated with the (i-1 )-th capacitor element of compensation array 44 will be deasserted (NMOS device 62 of the switches associated with the (i-1 )-th capacitor element of compensation array 44 will be OFF), and the S_actιve signal of the transmission gate 58 associated with the (i-1 )-th capacitor element of array 44 will be deasserted. Thus, prior to this operation, the (i-1 )-th element is held in minimum capacitance state. To perform the make before break connection, the S_actιve signal of the transmission gate 58 associated with the (i-1 )-th capacitor element of array 44 is asserted. At this point both the DAC 32 and pull up PMOS device 60 will hold the bias control node of the i-th capacitor element of compensation array 44 at Vdd or minimum capacitance state. Now it is possible to deassert the S_h._gh signal of the switches associated with the (i-1 )-th capacitor element of compensation array 44, and the DAC output is connected to the bias control node of the (i-1 )-th capacitor element of compensation array 44. This corresponds to block 520. A check is then made by the control logic 30 on the state of the third comparator 28 associated with detection at the third predetermined level, at block 522. If this has changed state, it indicates that the control signal Vtune has reached the third predetermined level within the desired operating range. In this case, the decrement operation is terminated and the adjustment signal is no longer provided to the capacitor elements 46 and the control logic 30 returns to "Idle" state, block 502. If the output of the third comparator 28 has not changed state, then another iteration of the "Decrement Mode" will occur by returning to block 506, further adding capacitance to the tank circuit thereby causing the value of control signal Vtune to continue to rise. The control signalling associated with the "Decrement Mode" is illustrated in FIG. 7. The effect of this adjustment achieved by the method in accordance with an embodiment of the disclosure on the oscillator tuning characteristic is shown in FIG. 8. When the control signal Vtune reaches the second predetermined, level 2, decrement operations as described above are instigated by control logic 30 which cause the frequency tuning characteristic to shift in a step wise manner as indicated by the dashed curves in FIG. 8 in the direction 800 until control signal V_tune reaches the third predetermined level, level 3, at which time adjustments are terminated.

In the opposite case whereby the control signal Vtune reaches the first predetermined, level 1 , as determined by the level detector arrangement 22 (block 524), the control circuit 6 may for example generate an adjustment signal to compensate for this shift in control signal Vtune which results in capacitance being subtracted from the tank circuit with the negative feedback action of the PLL circuit 2 thereby causing the control signal Vtune to lower in value. This will occur according to the "Increment Mode" state flow of FIG. 5, starting at block 526, in a complimentary fashion to the process described for the "Decrement Mode". This involves incrementing the thermometer code i such that more capacitor elements 46 will be in a minimum capacitance state based on the adjustment signal. The control signalling associated with the "Increment Mode" is illustrated in FIG. 9.

When the adjustment process is terminated, the control logic 30 stores the state of the DAC 32 and the compensation array 44: for example, the control logic 30 determines and stores the current setting of the DAC 32 (n.b. the adjustment of the control voltage Vtune based on temperature variations may end at a non-full/zero scale setting in the DAC 32) and the currently selected capacitor element 46 on termination. When the temperature compensation process is triggered next e.g. when the voltage level of the control signal Vtune next reaches the first or second predetermined level, the control logic 30 will continue from the state held since the previous temperature compensation process.

The term "assert" has been used herein to refer to the rendering of a signal into its logically true state which corresponds to a logic level one and the term "deassert" has been used to refer to the rendering of a signal into its logically false state which corresponds to a logic level zero. It will be readily apparent that in alternative embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

FIG. 10 shows how the voltage level of the control signal Vtune varies over time with variations in temperature and once the adjustment process in accordance with the disclosure has been triggered. Initially, it is assumed that the PLL circuit 2 is in lock with the control signal Vtune having a voltage level substantially in the middle of the predetermined operating range around the third predetermined level, level 3. Between times tO and t1 , variations in temperature cause the voltage level of the control signal Vtune to decrease until at time t1 , the voltage level reaches the second predetermined level, level 2. This is detected by the level detector arrangement 22 and in response, the control logic 30 generates adjustment signals to be applied to the compensation array 44 of the VCO 4 such that the voltage level of the control signal Vtune is increased in a step wise manner towards the third predetermined level, level 3. At time t2, the level detector arrangement 22 determines that the voltage level of the control signal Vtune has reached level 3 and in response, the control logic 30 terminates the adjustment process. A simple voltage generator could be used instead of the DAC 32 to generate an adjustment signal having a voltage level to switch the capacitance of the selected capacitor element 46 between maximum and minimum capacitance but such an abrupt change in the capacitance would cause abrupt frequency changes in the VCO 4 which when corrected by the PLL circuit 2 may cause large phase shifts. For applications, such as 3G in which the 3G standard defines small phase change requirements, such large phase shifts may not meet the phase change requirements as defined by the standard. By using a DAC 32 that can provide an adjustment signal to a selected capacitor element 46 whose voltage level can be varied in steps at a slow rate between Ov and Vdd, the VCO arrangement 3 in accordance with an embodiment of the disclosure can control a smooth change in the capacitance of the capacitor element 46 between the maximum and minimum capacitance. By providing a smooth transition between the maximum capacitance to the minimum capacitance at a slow rate, the VCO arrangement 3 in accordance with an embodiment of the disclosure can ensure small phase shifts are introduced when compensating for temperature variations which do not exceed phase change requirements of applications such as 3G. For example, the voltage step size of the output signal provided by the DAC 32 is designed to incur < 30 degree phase change and to bound the peak frequency deviation during the temperature transient. Furthermore, the rate at which the voltage level of the DAC output signal is changed is sufficiently low to have negligible effect on the output power spectrum of the PLL circuit 2 but is high enough to allow the PLL circuit 2 to track an ambient temperature ramp rate of 10 °C/min.

Since the output 38 of the DAC 32 is coupled to the centre tap of the capacitor elements in the compensation array 44 of the VCO 4, the output of the control circuit 6 is applied to the compensation array 44 of the VCO 4 and not the main array 50 of the VCO 4 which is used for the normal tuning of the VCO 4. Thus, the VCO arrangement 3 in accordance with the disclosure implements temperature compensation using the control circuit 6 but since the control circuit 6 is isolated from the main tuning line in a separate loop, the VCO arrangement 3 avoids the introduction of spurious signals from the control circuit 6 into the main tuning line. In fact, since the control circuit 6 for providing temperature compensation to the control signal Vtune is in a separate loop to the main tuning line, the temperature compensation provided by the VCO arrangement 3 in accordance with an embodiment of the disclosure has no impact on some critical parameters of the PLL circuit 2 such as open loop gain, PLL bandwidth, phase margin and has very low impact on the dynamics, such as transient phase error, noise, of the PLL circuit 2. Furthermore, the temperature compensation loop may be independently designed form the main tuning line sensitivity.

The VCO arrangement 3 may provide a closed loop temperature compensation architecture and so is not process dependent and can be applied to any manufacturing process or PLL architecture unlike the open loop arrangements described in the articles in the introduction. Furthermore, since a closed loop temperature compensation architecture is used, the VCO arrangement 3 in accordance with the disclosure is less complex to set up and requires less calibration and is robust for device mismatch and process variations across wide tuning ranges.

The VCO arrangement 3 may be used in any PLL circuit that requires temperature compensation for proper operation. It does however provide particular advantages in PLL circuits used in any continuous time application, such as 3G applications as described above, where there is no dedicated time window to re-lock PLLs and thus avoid temperature drift issues.

An embodiment of the disclosure uses a compensation array composed of small thermometer coded VVC elements, with all but one of the WC units being held at either minimum or maximum capacitance state at any given time during operation. In these operating regions, the slope of the C-V curve is minimised thereby affording maximum noise immunity. Furthermore, the active unit of the VVC compensation array which may be connected to the DAC output voltage can be easily designed such that its noise sensitivity, when combined with the DAC output noise, has a negligible impact on the total VCO sideband noise at all frequency offsets. With high resistivity polysilicon resistors (as are typically available on standard CMOS processes) used in the DAC, the resistor string DAC implementation is readily integrated in a small area, and appropriate sizing of the resistors yields low current drain. The comparators of the level detector arrangement again lend themselves to compact design, and such techniques such as sub-threshold design lead to negligible current drain for the temperature compensation solution (typically less than 1 % of VCO current drain for a state of the art integrated solution for a SAW-less 3G transceiver application).

In an embodiment an XOR type phase detector is used. This allows for an area efficient integration of an all pole loop filter onto the same die as the other PLL components and allows for a single port GMSK modulation which is advantageous for providing a low cost modulator design. For noise and stability reasons, the PLL design including an XOR type phase detector requires relatively low gain values Kv to be used for the main tuning port of the VCO (as compared to traditional charge pump designs). This increases the sensitivity of the tuning voltage signal Vtune to temperature variations which, as described above in the introduction, is an issue particularly for 3G and other systems where the PLL is required to maintain lock for an indefinite period of time. By using the VCO arrangement in accordance with the disclosure, a robust temperature compenstion is provided in which the tuning voltage signal can be maintained within an operating range in the presence of ambient temperature, supply voltage and process variations.

In the above, reference has been made to the frequency drift of the output signal of the VCO which in turn affects the voltage level of the voltage tuning signal by way of the negative feedback action of the PLL has been described above as coming from temperature variations. Other phenomena, such as supply pushing, load pulling, may also cause frequency drift and the PLL to lose lock. However, the disclosure has been described with respect to compensating for temperature effects as these are the dominant effects in the fully integrated environment of CMOS designs and other measures can be taken to reduce other pushing and pulling effects. It should be recognised however that the disclosure equally compensates for these other effects, as they are essentially indistinguishable from temperature drift in terms of the effect on the control voltage

Vtune.

The PLL circuit in accordance with an embodiment of the disclosure has been described having capacitor elements with VVC devices having a C-V characteristic as shown in FIG. 1. It will however be appreciated that the PLL circuit in accordance with the disclosure applies equally when the VCO incorporates WC devices with opposing C-V characteristics to that of FIG. 1 with appropriate inversion of the logic signals from control logic 30.

Furthermore, it will be appreciated that the temperature compensation scheme in accordance with the disclosure could equally be applied to PLL circuit designs where instead of employing variable capacitor elements to introduce the appropriate compensation adjustment, other elements having a variable parameter which is variable according to a voltage adjustment signal may be used. For example, a variable inductor element could additionally or instead be employed. Example of such designs might include the use of active inductor circuits (eg capacitively terminated gyrators) or MEMs devices to implement the variable inductor function.

Thus, the VCO in accordance with the compensation

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader scope of the invention as set forth in the appended claims.

Claims

1. A Phase Locked Loop (PLL) circuit (2) comprising: a phase detector arrangement (8, 10) having a first input for receiving a reference signal, a second input and an output (13) for providing a control signal; and a voltage controlled oscillator (VCO) arrangement (3) including: a VCO (4) having a first input (5) for receiving the control signal, a second input (11 ) and an output (7) for providing an output signal having a frequency dependent on the control signal, the output of the VCO (4) being coupled to the second input of the phase detector arrangement (8, 10) via a feedback path; and a control circuit (6) for receiving the control signal and being coupled to the second input (1 1 ) of the VCO (4), the control circuit being arranged in operation to provide an adjustment signal to the VCO selectively and in dependence on a level of the control signal such that the level of the control signal is adjusted to maintain the control signal within a predetermined operating range.

2. The PLL circuit of claim 1 , wherein the VCO (4) comprises a compensation array (44) of elements (46) having a variable parameter, the compensation array (44) of elements (46) being coupled to the second input (1 1) of the VCO (4), wherein in operation the VCO (4) is arranged to adjust the variable parameter of the compensation array (44) based on the adjustment signal provided by the control circuit (6) such that the level of the control signal is adjusted.

3. The PLL circuit of claim 1 , wherein the VCO (4) comprises a compensation array (44) of capacitor elements (46) having a variable capacitance, the compensation array (44) of capacitor elements (46) being coupled to the second input (11 ) of the VCO (4), wherein in operation the VCO arrangement (3) is arranged to adjust the variable capacitance of the compensation array (44) based on the adjustment signal provided by the control circuit (6) such that the level of the control signal is adjusted.

4. The PLL circuit of claim 3, wherein the VCO (4) further comprises a tuning array of capacitor elements having a variable capacitance, the tuning array of capacitor elements being coupled to the first input (5) of the VCO (4), wherein in operation the VCO (4) is arranged to adjust the variable capacitance of the tuning array based on the control signal.

5. The PLL circuit of claim 3 or 4, wherein in operation the control circuit (6) is arranged to provide the adjustment signal to one or more of the capacitor elements (46) of the compensation array (44) so as to adjust the variable capacitance of the compensation array (44).

6. The PLL circuit of any preceding claim, wherein the control circuit (6) is arranged in operation to determine when the control signal reaches a predetermined level and to provide an adjustment signal to the VCO (4) in response to determining that the control signal reaches the predetermined level.

7. The PLL circuit of claim 6, wherein the control circuit (6) is arranged in operation to determine when the control signal is greater than a first predetermined level and in response to provide a first adjustment signal to adjust the level of the control signal in a first direction and to determine when the control signal is less than a second predetermined level and in response to provides a second adjustment signal to adjust the level of the control signal in a second direction.

8. The PLL circuit of claim 7, wherein the control circuit (6) is arranged in operation to determine when the control signal is at a third predetermined level between the first and second predetermined levels, and to provide the first or second adjustment signal to the VCO (4) until the control circuit determines that the control signal is at the third predetermined level.

9. The PLL circuit of any preceding claim wherein the control circuit (6) comprises: a level detector arrangement (22) for receiving the control signal and for determining when the level of the control signal reaches one or more predetermined levels; control logic (30) coupled to the level detector arrangement (22) for generating control signals in dependence on the detected level of the control signal; and signal generator (32) for receiving the control signals and for generating an adjustment signal in response to the control signals.

10. The PLL circuit of claim 9, wherein the adjustment signal is a voltage signal and wherein the signal generator (32) is arranged to generate an adjustment voltage signal having a voltage level that varies in steps between two supply voltages in dependence on the control signals provided by the control logic (30).

11. The PLL circuit of claim 10, wherein the signal generator (32) comprises a Digital-to-Analog Converter (DAC) (32) for converting the control signals provided by the control logic (30) to adjustment signals having an appropriate voltage level as determined by the control signals.

12. The PLL circuit of claim 11 , wherein the DAC (32) comprises a potential divider having a plurality of resistors (34) connected in series between two supply voltages and a plurality of switches (36) coupled between nodes (40) positioned along the serially connected resistors (34) and an output (38) of the DAC (32), wherein each of the plurality of switches includes a control electrode coupled to the control logic (30) for receiving the control signals, wherein in operation the control logic (30) is arranged to provide control signals to the control electrodes of the plurality of switches (36) to control the voltage level of the adjustment signal at the output (38) of the DAC (32).

13. The PLL circuit of any one of claims 9 to 12, wherein the level detector arrangement (22) comprises a first comparator (24) for determining when the level of the control signal reaches a first predetermined level and a second comparator (26) for determining when the control signal reaches a second predetermined level.

14. The PLL circuit of claim 13, wherein the level detector arrangement (22) further comprises a third comparator (28) for determining when the level of the control signal reaches a third predetermined level, the third predetermined level being between the first and second predetermined levels.

15. The PLL circuit of claim 8 or 14, wherein the third predetermined level is substantially in the middle between the first and second predetermined levels.

16. The PLL circuit of any one of claims 8 to 15, wherein the VCO (4) comprises a compensation array (44) of capacitor elements (46) having a variable capacitance, the compensation array (44) of capacitor elements (46) being coupled to the second input (11 ) of the VCO (4) via a switching circuit (52), and the switching circuit (52) being coupled to the signal generator (32) for receiving the adjustment signal and to the control logic (30) for receiving switch control signals for controlling the switching circuit (52), wherein the switching circuit (52) in operation and in dependence on the switch control signals provides the adjustment signal to selected one or more of the capacitor elements (46) of the compensation array (44) so as to adjust the variable capacitance of the compensation array (44) such that the level of the control signal is adjusted.

17. The PLL circuit of claim 16, wherein the switching circuit (52) comprises a plurality of transmission gates (58), each of the plurality of transmission gates (58) being coupled to a capacitor element (46) of the compensation array (44) and to the second input (11 ) and having a control terminal for receiving the switch control signals from the control logic (30).

18. The PLL circuit of any one of claims 3, 4, 5, 16, and 17, wherein each one of the capacitor elements (46) of the compensation array (44) is substantially the same element (46).

19. The PLL circuit of claim 3, 4, 5, 16, 17 and 18, wherein each of the capacitor elements (46) of the compensation array (44) includes two voltage variable capacitors (48) coupled in a differential arrangement with a bias control node between the two voltage variable capacitors coupled to the second input (11 ) of the VCO (4).

20. The PLL circuit of claim 17 and 19, wherein each of the transmission gates (58) is coupled to the bias control node of a capacitor element (46).

21. The PLL circuit of any preceding claim, wherein the phase detector arrangement comprises: a phase detector (8) having a first input coupled to the first input of the phase detector arrangement for receiving the reference signal and a second input coupled to the second input of the phase detector arrangement and an output; and a loop filter (10) coupled to the output of the phase detector (8) for providing the control signal at the output (13) of the phase detector arrangement, and wherein the PLL circuit further comprises a frequency divider (12) coupled in the feedback path between the output of the VCO (4) and the second input of the phase detector arrangement.