WO2009104851A1

WO2009104851A1 - Device for xor magneto-logic circuit using stt-mtj

Info

Publication number: WO2009104851A1
Application number: PCT/KR2008/005568
Authority: WO
Inventors: Hyungsoon Shin; Seungyeon Lee; Hyunjoo Lee; Gamyoung Lee
Original assignee: Ewha University-Industry Collaboration Foundation
Priority date: 2008-02-18
Filing date: 2008-09-19
Publication date: 2009-08-27
Also published as: KR20090089028A; KR100961723B1

Abstract

The present invention relates to an XOR logic operation apparatus using a spin torque transfer-based MTJ device. The XOR logic operation apparatus includes two parallel-connected magnetic memory cells (100, 200), and a sense amplifier (300) connected to first ends of the two magnetic memory cells. Each of the magnetic memory cells includes an MTJ device (10) and a current control circuit (50). Each magnetic memory cell includes a top electrode (11) and a bottom electrode (13) configured to allow current to flow therethrough, an insulating layer (19) configured to electrically insulate the top electrode from the bottom electrode, and a free magnetic layer (17) and a pinned magnetic layer (15) respectively formed on a top and a bottom of the insulating layer. The current control circuit controls flow of current passing between the top electrode and the bottom electrode, and changes a magnetization direction of the free magnetic layer.

Description

[DESCRIPTION]

[invention Title]

DEVICE FOR XOR MAGNETO-LOGIC CIRCUIT USING STT-MTJ

[Technical Field] The present invention relates, in general, to an XOR logic operation apparatus, and, more particularly, to an XOR logic operation apparatus using a Spin Torque Transfer (STT) -based Magnetic Tunnel Junction (MTJ) device, which does not require an initialization process.

[Background Art]

Generally, in a logic circuit using a Magnetic Tunnel Junction (MTJ) device, the magnetization direction of a free magnetic layer is changed when currents flow through input terminals in the same direction, and is not changed when currents flow through input terminals in different directions . Therefore, the magnetic spin of free magnetic layers within intersecting cells can be arranged in desired directions due to a combined magnetic field formed by respective currents . In contrast, the magnetization direction of a pinned magnetic layer is fixed. Accordingly, a digital signal having logic levels ^Λl' and '0' can be recorded by implementing the magnetization directions of two magnetic layers as two types, that is, a parallel direction and a semi-parallel direction.

Further, when a digital signal having logic levels ' 1 ' and '0' is read, the Tunneling Magneto-Resistance (TMR) of an MTJ device is used. When a sensing voltage is applied to the MTJ device, electron carriers tunnel through a non-magnetic, non- conductive tunneling layer between the magnetic layers, thus passing through the magnetic layers. Resistance relative to a sensing current is minimized when the magnetic vectors of the pair of magnetic layers are parallel in the same direction, thus enabling resistance corresponding to the relative magnetization directions of the two magnetic layers to be measured on the basis of the conductance of electrons, which tunnel through an insulating layer.

Meanwhile, an XOR logic operation apparatus, which is an exclusive OR circuit, is a logic operation apparatus in which, when only one of two input values is true, an output value is true. Such an XOR logic operation apparatus can be implemented using the MTJ device.

FIG. 1 is a diagram showing a conventional XOR logic operation apparatus using an MTJ device (refer to J. of Applied Physics, vol. 97, p.l0D509, 2005). Referring to FIG. 1, the conventional XOR logic operation apparatus using an MTJ device includes an MTJ device and two input layers 7 and 8. The MTJ device includes a top electrode 2 and a bottom electrode 3, which are provided to allow current to flow therethrough, a pinned magnetic layer 4 and a free magnetic layer 6, which are magnetic layers deposited between the top electrode and the bottom electrode, and an insulating layer 5, which is configured to insulate the pinned magnetic layer 4 from the free magnetic layer 6 and is deposited between the pinned magnetic layer 4 and the free magnetic layer 6. The two input layers 7 and 9 are disposed on the top electrode 2 and are configured to receive currents to magnetize both the pinned magnetic layer 4 and the free magnetic layer 6 of the MTJ device. The XOR logic operation apparatus performs an XOR logic operation depending on the directions of the currents input to the input layers 7 and 8. A logic level, obtained when the direction of current flowing through each of the input layers 7 and 8 is -I, as shown in FIG. 1 (a direction from the front to the rear of each input layer of FIG. 1, as indicated by a left arrow) , is defined as '0', whereas a logic level, obtained when the direction is +1 (as indicated by a right arrow), is defined as ^λl' . When the directions of currents flowing through respective input layers are identical to each other, the magnetization direction of the free magnetic layer 6 is changed, whereas when the directions of currents flowing through respective input layers are different from each other, the magnetization direction of the free magnetic layer 6 is not changed.

When current does not flow through the bottom electrode 3, the magnetization direction of the pinned magnetic layer 4 is not changed. In order to change the magnetization direction of the pinned magnetic layer 4, the directions of currents flowing through the input layers 7 and 8 must be identical to each other in the state in which a current of I flows through the bottom electrode 3.

FIG. 2 illustrates the initialization process and the operation process of a conventional XOR logic operation apparatus using an MTJ device. The operation of the MTJ device is divided into an initialization process (refer to ^VSET' of FIG. 2 (a) and an operation process (refer to ^λLogic' of FIGS. 2(b) to 2(e)) .

Referring to FIG. 2 (a) , before the operation of the logic operation apparatus, the magnetization direction of the pinned magnetic layer 4 is set to the left and the magnetization direction of the free magnetic layer 6 is set to the right through a two-step initialization process, and thus a high-level resistance value R_H is formed. Next, when a current of -I (logic level 0) or +1 (logic level 1) is input to the respective input layers 7 and 8, as shown in FIGS. 2 (b) to 2 (d) after a current of I has been applied to the bottom electrode 3, the resistance value of the MTJ device is determined, as shown in FIGS. 2 (b) to 2 (d) . As shown in FIGS. 2 (b) to 2 (d) , when the logic levels of respective input layers 7 and 8 are identical to each other, the resistance value of the MTJ device is set to R_L having a low level, whereas when the logic levels are different from each other, the resistance value of the MTJ device is set to R_H as in the case of an initialization state.

When the resistance value of the MTJ device is compared with R_L using a sense amplifier (AMP) , as shown in FIG. 3, the MTJ device is operated as an XOR logic operation apparatus, as indicated in Table 1.

Table 1

In this case, in order to make the output of the sense AMP a logic level ^λ0' when the resistance value of the MTJ device is R_L, the offset voltage V_Os of the sense AMP must satisfy the following equation.

-Ise_nse*£&< V_os<0(AR= R_H~ R_∑) The conventional XOR logic operation apparatus using an MTJ device is disadvantageous in that, after the operation thereof, the magnetization directions of the free magnetic layer and the pinned magnetic layer of the MTJ device must always be initialized. That is, as shown in FIGS. 2 (a) to 2 (e) , since the magnetization directions of the free magnetic layer and the pinned magnetic layer are changed according to the logic levels of the input layers 7 and 8, the two-step initialization process of recovering the magnetization directions to original directions and performing initialization for a subsequent logic operation is required. Due thereto, there is a problem in that the operating speed of the XOR logic operation apparatus is decreased.

[Disclosure] [Technical Problem]

Accordingly, the present invention has been made keeping in mind the above problem in that the operating speed of the conventional XOR logic operation apparatus is decreased, and an object of the present invention is to provide an XOR logic operation apparatus, which does not require an initialization process .

[Technical Solution]

In order to accomplish the above object, the present invention provides an XOR logic operation apparatus using a Magnetic Tunnel Junction (MTJ) device, comprising two magnetic memory cells connected in parallel with each other; and a sense amplifier connected to first ends of the two respective magnetic memory cells, wherein each of the magnetic memory cells comprises an MTJ device including a top electrode and a bottom electrode configured to allow current to flow therethrough, an insulating layer configured to electrically insulate the top electrode from the bottom electrode, and a free magnetic layer and a pinned magnetic layer respectively formed on a top and a bottom of the insulating layer, and a current control circuit configured to control flow of current passing between the top electrode and the bottom electrode, and change a magnetization direction of the free magnetic layer according to an input logic level .

Further, the magnetization direction of the pinned magnetic layer is fixed. Further, the current control circuit is configured such that a logic level is formed by changing a signal input to a gate of the current control circuit.

Further, when current applied to the MTJ device flows in a direction from the top electrode to the bottom electrode, the magnetization direction of the free magnetic layer is identical to that of the pinned magnetic layer.

Further, when magnetization directions of the free magnetic layer and the pinned magnetic layer are identical to each other, a magnetic resistance of the MTJ device has a logic level ^λ0' .

Further, when current applied to the MTJ device flows in a direction from the bottom electrode to the top electrode, the magnetization direction of the free magnetic layer is opposite that of the pinned magnetic layer. Further, when magnetization directions of the free magnetic layer and the pinned magnetic layer are opposite each other, resistance of the MTJ device has a logic level ^λl' .

Further, the current control circuit comprises a first current driving unit, a source of which is connected to the top electrode; a second current driving unit, a drain of which is connected to a drain of the first current driving unit; a third current driving unit, a drain of which is connected to the bottom electrode; and a fourth current driving unit, a source of which is connected to a source of the third current driving unit. Preferably, each of the first to fourth current driving units comprises three MOSFETs connected in parallel with each other. Preferably, the source of the first current driving unit is connected to the drain of the fourth current driving unit, and a source of the second current driving unit is connected to the drain of the third current driving unit.

Further, the current control circuit may further comprise a first enable MOSFET, a first end of which is connected to a node to which the first current driving unit and the second current driving unit are connected; and a second enable MOSFET, a first end of which is connected to a node to which the third current driving unit and the fourth current driving unit are connected.

Further, each of the first to fourth current driving units comprises a first MOSFET having a gate to which a first logic input signal is applied; a second MOSFET having a gate to which a second logic input signal is applied; and a third MOSFET having a gate to which a third logic input signal is applied. In this case, signals applied to gates of the MOSFETs constituting the first current driving unit are identical to signals applied to gates of the MOSFETs constituting the third current driving unit, respectively, and signals applied to gates of the MOSFETs constituting the second current driving unit are identical to signals applied to gates of the MOSFETs constituting the fourth current driving unit, respectively, wherein the signals applied to the first current driving unit and the signals applied to the second current driving unit have an inverted relationship with each other.

Further, the sense amplifier is operated to compare resistance values of MTJ devices provided in the two magnetic memory cells with each other, to output a logic level ^λl' when a resistance value sensed at a terminal V₊ is greater than a resistance value sensed at a terminal V-, and to output a logic level ^λ0' when a resistance value sensed at a terminal V₊ is equal to or less than a resistance value sensed at a terminal V-.

[Advantageous Effects] Accordingly, the XOR logic operation apparatus using an MTJ device according to the present invention is advantageous in that, unlike the conventional XOR logic operation apparatus, an initialization process is not required, thus improving the operating speed of the XOR logic operation apparatus .

[Description of Drawings]

FIG. 1 is a diagram showing a conventional XOR logic operation apparatus using an MTJ device;

FIG. 2 is a diagram showing the initialization process and the operation process of a conventional XOR logic operation apparatus using an MTJ device;

FIG. 3 is a diagram showing a conventional XOR logic operation apparatus using an MTJ device;

FIG. 4 is a diagram showing an MTJ device used in an XOR logic operation apparatus according to the present invention;

FIG. 5 is a circuit diagram showing a magnetic memory cell composed of an MTJ device and a current control circuit and used in an XOR logic operation apparatus according to the present invention; FIG. 6 is a diagram schematically showing the current direction and the magnetization direction of an MTJ device based on the operation of the magnetic memory cell of FIG. 5;

FIG. 7 is a diagram conceptually showing the magnetic memory cell of FIG. 5; and FIG. 8 is a diagram conceptually showing an XOR logic operation apparatus according to the present invention.

100, 200: magnetic memory cell 300: sense AMP

10: MTJ device 11: top electrode 13: bottom electrode

15: pinned magnetic layer 17: free magnetic layer

19: insulating layer 20a: second current driving unit

21a: first MOSFET 23a: second MOSFET

25a: third MOSFET 20b: fourth current driving unit 21b: first MOSFET 23b: second MOSFET

25b: third MOSFET 30a: first current driving unit 31a: first MOSFET 33a: second MOSFET 35a: third MOSFET 30b: third current driving unit 31b: first MOSFET 33b: second MOSFET 35b: third MOSFET 41: second enable MOSFET 43: first enable MOSFET 50: current control circuit

[Best Mode]

An XOR logic operation apparatus using a Magnetic Tunnel Junction (MTJ) device according to the present invention comprises two magnetic memory cells connected in parallel with each other; and a sense amplifier connected to first ends of the two respective magnetic memory cells, wherein each of the magnetic memory cells comprises an MTJ device including a top electrode and a bottom electrode configured to allow current to flow therethrough, an insulating layer configured to electrically insulate the top electrode from the bottom electrode, and a free magnetic layer and a pinned magnetic layer respectively formed on a top and a bottom of the insulating layer, and a current control circuit configured to control flow of current passing between the top electrode and the bottom electrode, and change a magnetization direction of the free magnetic layer according to an input logic level .

Further, the magnetization direction of the pinned magnetic layer is fixed, and the current control circuit is configured such that a logic level is formed by changing a signal input to a gate of the current control circuit. Further, when current applied to the MTJ device flows in a direction from the top electrode to the bottom electrode, the magnetization direction of the free magnetic layer is identical to that of the pinned magnetic layer. Further, when magnetization directions of the free magnetic layer and the pinned magnetic layer are identical to each other, a magnetic resistance of the MTJ device has a logic level ^Λ0' .

Further, when current applied to the MTJ device flows in a direction from the bottom electrode to the top electrode, the magnetization direction of the free magnetic layer is opposite that of the pinned magnetic layer.

Further, when magnetization directions of the free magnetic layer and the pinned magnetic layer are opposite each other, resistance of the MTJ device has a logic level ^Λl' .

Further, the current control circuit comprises a first current driving unit, a source of which is connected to the top electrode; a second current driving unit, a drain of which is connected to a drain of the first current driving unit; a third current driving unit, a drain of which is connected to the bottom electrode; and a fourth current driving unit, a source of which is connected to a source of the third current driving unit.

Preferably, each of the first to fourth current driving units comprises three MOSFETs connected in parallel with each other. Preferably, the source of the first current driving unit is connected to the drain of the fourth current driving unit, and a source of the second current driving unit is connected to the drain of the third current driving unit .

Further, each of the first to fourth current driving units in the current control circuit comprises a first MOSFET having a gate to which a first logic input signal is applied; a second MOSFET having a gate to which a second logic input signal is applied; and a third MOSFET having a gate to which a third logic input signal is applied. In this case, signals applied to gates of the MOSFETs constituting the first current driving unit are identical to signals applied to gates of the MOSFETs constituting the third current driving unit, respectively, and signals applied to gates of the MOSFETs constituting the second current driving unit are identical to signals applied to gates of the MOSFETs constituting the fourth current driving unit, respectively, wherein the signals applied to the first current driving unit and the signals applied to the second current driving unit have an inverted relationship with each other.

[Mode for Invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. Reference should now be made to the drawings, in which the same reference numerals are used throughout the different drawings to designate the same or similar components. It should be noted that, in the following description of the present invention, detailed descriptions may be omitted if it is determined that the detailed descriptions of related well-known functions and construction may make the gist of the present invention unclear.

FIG. 4 is a diagram showing an MTJ device used in an XOR logic operation apparatus according to the present invention, FIG. 5 is a circuit diagram showing a magnetic memory cell composed of an MTJ device and a current control circuit and used in an XOR logic operation apparatus according to the present invention, FIG. 6 is a diagram schematically showing the current direction and the magnetization direction of an MTJ device based on the operation of the magnetic memory cell of FIG. 5, FIG. 7 is a diagram conceptually showing the magnetic memory cell of FIG. 5, and FIG. 8 is a diagram conceptually showing an XOR logic operation apparatus according to the present invention.

As shown in FIG. 8, an XOR logic operation apparatus according to the present invention includes two magnetic memory cells 100 and 200 connected in parallel with each other, and a sense amplifier (AMP) 300 connected to the first ends of two respective magnetic memory cells. Each of the two magnetic memory cells 100 and 200 includes an MTJ device 10 (refer to FIG. 4) and a current control circuit 50 (refer to FIG. 5) . First, before the XOR logic operation apparatus of the present invention is described, an MTJ device used in the XOR logic operation apparatus is described below with reference to FIGS. 4 to 6.

As shown in FIG. 4, an MTJ device 10 used in the XOR logic operation apparatus of the present invention includes a top electrode 11 and a bottom electrode 13 configured to allow current to flow therethrough, an insulating layer 19 configured to electrically insulate the top electrode from the bottom electrode, and a free magnetic layer 17 and a pinned magnetic layer 15 respectively formed on the top and the bottom of the insulating layer.

Further, the magnetization direction of the pinned magnetic layer 15 is fixed to the right direction, and is continuously maintained in the right direction regardless of the direction of current applied by the current control circuit 50 (refer to FIG. 5) , which will be described later. Here, the MTJ device 10 is a component constituting

Magnetoresistive Random Access Memory (MRAM) , and is configured to store data and information using a magnetoresistance effect in which the resistance of an electric conductor is changing according to a surrounding magnetic field.

The term ^Λmagnetoresistance effect' means a phenomenon in which the electrical resistance of material is changed due to a magnetic field. When a magnetic field is applied to metal or a semiconductor, electrical resistance thereof increases, and an increase in the electrical resistance is proportional to the square of the intensity of the magnetic field with respect to a weak electric field. The case where the direction of current is perpendicular to the direction of a magnetic field is called a transverse effect. In a ferromagnetic substance, variation in resistance occurs according to variation in the direction of spontaneous magnetization.

Accordingly, in the MTJ device 10, the current control circuit 50 (refer to FIG. 5) controls the magnetization direction of the free magnetic layer 17 by applying current in a vertical direction, and the magnetic resistance of the MTJ device 10 is changed to the changed magnetization direction, and thus data can be recorded in memory, or a logic circuit can be implemented, using the magnetic resistance.

Further, the magnetization direction of the free magnetic layer 17 is changed according to the direction of current. When the direction of current applied by the current control circuit 50 is a direction from the top electrode 11 to the bottom electrode 13 of the MTJ device 10, the magnetization direction of the free magnetic layer 17 is changed to the direction identical to that of the pinned magnetic layer 15. When the direction of current applied by the current control circuit 50 is a direction from the bottom electrode 13 to the top electrode 11 of the MTJ device 10, the magnetization direction of the free magnetic layer 17 is changed to a direction opposite that of the pinned magnetic layer 15. Here, when the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are parallel in opposite directions (anti-parallel), the magnetic resistance is maximized, and thus a logic level '1' can be output. When the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are parallel in the same direction (parallel), the magnetic resistance is minimized, and thus a logic level '0' can be output.

In an embodiment of the present invention, when the direction of current applied by the current control circuit 50 is a top to bottom direction in the case where the magnetization direction of the pinned magnetic layer 15 is assumed to be a right direction, the magnetization direction of the free magnetic layer 17 is changed to the right direction, so that the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are parallel in the same direction, and the magnetic resistance is minimized, and thus a logic level '0' is obtained.

In contrast, when the direction of current applied by the current control circuit 50 is in the bottom to top direction, the magnetization direction of the free magnetic layer 17 is changed to a left direction, so that the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are anti-parallel with each other, and the magnetic resistance is maximized, and thus a logic level '1' is obtained.

FIG. 5 is a circuit diagram showing a magnetic memory cell composed of an MTJ device and a current control circuit, and used in an XOR logic operation apparatus according to the present invention.

The current control circuit 50 includes a first current driving unit 30a, a second current driving unit 20a, a third current driving unit 30b, a fourth current driving unit 20b, a first enable Metal Oxide Semiconductor Field Effect Transistor

(MOSFET), and a second enable MOSFET.

Here, the first current driving unit 30a includes a first MOSFET 31a, a second MOSFET 33a and a third MOSFET 35a. One end of the first current driving unit 30a is connected both to the top electrode 11 of the MTJ device 10 and to the fourth current driving unit 20b, and the other end is connected to the second current driving unit 20a.

Further, the first MOSFET 31a, the second MOSFET 33a, and the third MOSFET 35a are preferably implemented as NMOS transistors and are connected in parallel, and the sources thereof are connected both to the top electrode 11 and to the fourth current driving unit 20b.

Further, the second current driving unit 20a includes a first MOSFET 21a, a second MOSFET 23a and a third MOSFET 25a. One end of the second current driving unit 20a is connected to the first current driving unit 30a, and the other end is connected to the third current driving unit 30b.

In this case, the first MOSFET 21a, the second MOSFET 23a, and the third MOSFET 25a are preferably implemented as NMOS transistors, and are connected in parallel with each other. The sources of respective MOSFETs 21a, 23a and 25a are connected to the drain of the third current driving unit 30b, and the drains of the MOSFETs 21a, 23a and 25a are connected to the drains of respective MOSFETs 31a, 33a and 35a of the first current driving unit 30a.

Furthermore, the third current driving unit 30b includes a first MOSFET 31b, a second MOSFET 33b, and a third MOSFET 35b. The drains of respective MOSFETs 31b, 33b, and 35b of the third current driving unit 30b are connected both to the bottom electrode 13 of the MTJ device 10 and to the sources of MOSFETs 21a, 23a, and 25a of the second current driving unit 20a.

The first MOSFET 31b, the second MOSFET 33b, and the third MOSFET 35b are preferably implemented as NMOS transistors, and are connected in parallel with each other. The sources of respective MOSFETs 31b, 33b, and 35b are connected to one end of the fourth current driving unit 20b. Further, the fourth current driving unit 20b includes a first MOSFET 21b, a second MOSFET 23b and a third MOSFET 25b. The drains of respective MOSFETs 21b, 23b, and 25b are connected to the sources of respective MOSFETs 31a, 33a, and 35a of the first current driving unit 30a, and the sources thereof are connected to the sources of respective MOSFETs 31b, 33b, and 35b of the third current driving unit 30b.

Further, normal signals are input to respective gates of the second current driving unit 20a and the fourth current driving unit 20b, and inverted signals, obtained by inverting the signals input to the gates of the second current driving unit 20a and the fourth current driving unit 20b, are input to respective gates of the first current driving unit 30a and the third current driving unit 30b. That is, a first logic input signal, input to the first MOSFETs 21a and 21b, is inverted and input to the first MOSFETs 31a and 31b. For example, when the first logic input signal, input to the first MOSFETs 21a and 21b, is A, the first logic input signal, input to the first MOSFETs 31a and 31b, is A . In this way, a second logic input signal B, input to the second MOSFETs 23a and 23b, is input in an inverted relationship with a second logic input signal B , input to the second MOSFETs 33a and 33b. A second logic input signal C, input to the third MOSFETs 25a and 25b, is input in an inverted relationship with a second logic input signal C , input to the second MOSFETs 35a and 35b. In addition, the first enable MOSFET 43 is connected to a node connected both to the drains of respective MOSFETs 31a, 33a, and 35a of the first current driving unit 30a and to the drains of respective MOSFETs 21a, 23a, and 25a of the second current driving unit 20a. In particular, the source of the first enable MOSFET 43 is connected to that node.

Further, the second enable MOSFET 41 is connected to a node connected both to the sources of respective MOSFETs 31b, 33b and 35b of the third current driving unit 30b and to the sources of respective MOSFETs 21b, 23b, and 25b of the fourth current driving unit 20b. In particular, the drain of the second enable MOSFET 41 is connected to that node.

The reason for this is that, since current flows through the first and second enable MOSFETs 43 and 41 only during a write period in which ^λWE' is maintained in a logic level ^λl', current is supplied from the current driving circuit 50 to the

MTJ device 10, and thus a write operation can be performed.

Furthermore, voltages input to the gates of the first enable MOSFET 43 and the second enable MOSFET 41 are input in an inverted relationship with each other. For example, when the signal ^λWE' is input to the second enable MOSFET 41, a signal

WE is input to the first enable MOSFET 43. That is, a normal signal is input to the second enable MOSFET 41, and an inverted signal is input to the first enable MOSFET 43. Further, all MOSFETs used in the magnetic memory cell 100 used for the XOR logic operation apparatus according to the present invention, except the second enable MOSFET 41, are preferably implemented as NMOS transistors, while the first enable MOSFET 43 is preferably implemented as a PMOS transistor.

In this case, a MOSFET, which is a Field Effect Transistor (FET) provided with an oxide insulating layer, is formed such that a gate is insulated from a source-drain conduction channel in a semiconductor by an oxide insulating layer, and such that a gate input voltage corresponding to a pulse sufficient to charge or eliminate an amount of input charge is required. Therefore, when a certain voltage is not applied to the gates of each MOSFET, it is impossible to allow a drain - source current to flow through the MOSFET.

Hereinafter, a process for driving the magnetic memory cell used in an XOR logic operation apparatus according to the present invention is described below.

Certain voltages are applied to respective gates WE and

WE of the second enable MOSFET 41 and the first enable MOSFET

43 so that current flows between the drain and the source of each of the MOSFETs 41 and 43. Only in a write period during which data is written in the magnetic memory cell 100 of the present invention, an input signal having a logic level ^Λl' is applied to the gate WE.

Further, when the direction of current flowing through the

MTJ device 10 is a top to bottom direction, that is, the direction from the top electrode 11 to the bottom electrode 13, this current direction is defined as -I. When the direction of current flowing through the MTJ device 10 is a bottom to top direction, that is, the direction from the bottom electrode 13 to the top electrode 11, this current direction is defined as +1.

Table 2

As indicated in Table 2, when it is assumed that a logic input signal applied to the first MOSFETs 21a and 21b is A, a logic input signal applied to the second MOSFETs 23a and 23b is B, current applied to the third MOSFETs 25a and 25b is C, current applied to the MTJ device 10 based on the input signals A, B and C is ^current' , and magnetic resistance generated by controlling a magnetization direction using the current is R, the operation process of the logic circuit is described below.

The first row of Table 2 corresponds to the case of FIG. 6 (a), and, here, the operation performed when ^λ0' is input to all of A, B, and C is described below.

In this case, a logic level ^Λ0' is input to the gates A of the first MOSFETs 21a and 21b of the second and fourth current driving units 20a and 20b, a logic level '0' is input to the gates B of the second MOSFETs 23a and 23b, and a logic level '0' is input to the gates C of the third MOSFETs 25a and 25b. Meanwhile, a logic level ^Λl' , an inverted signal, is input to the gates A of the first MOSFETs 31a and 31b of the first and third current driving units 30a and 30b, a logic level ^Λl' , an inverted signal, is input to the gates B of the second MOSFETs 33a and 33b, and a logic level ^Λ0' , an inverted signal, is input to the gates C of the third MOSFETs 35a and 35b.

That is, a voltage corresponding to the logic level ^λl' is applied to the gates of the first, second and third MOSFETs 31a,

33a and 35a of the first current driving unit 30a, so that the first MOSFETs 31a, 33a and 35a are operated to allow current to flow between the drain and source of each thereof.

Further, when the amount of current output from each

MOSFET is assumed to be I, a current of I is output from each of the sources of the first, second and third MOSFETs 31a, 33a and 35a of the first current driving unit 30a. Since the MOSFETs

31a, 33a and 35a are connected in parallel with each other, a current of a total of 31 is output from the first current driving unit 30a.

Further, since the sources of the first, second and third MOSFETs 31a, 33a, and 35a of the first current driving unit 30a are connected to the top electrode 11 of the MTJ device 10, a current of I is applied to the MTJ device 10 in a top to bottom direction.

Therefore, since current flowing in the top to bottom direction is defined as -I, and current flowing in the bottom to top direction is defined as +1, a current of - 31 is applied to the MTJ device 10. The magnetization direction of the free magnetic layer 17 is changed to a right direction, and the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are parallel in the same direction, and thus the magnetic resistance of the MTJ device 10 is ^λ0' indicative of a logic level ^λlow' (R_L = 0) .

The second row of Table 2 corresponds to the case of FIG. 6(b), and, here, the operation performed when ^Λ0' is input both to A and to B, and ^Λl' is input to C is described below. Here, a logic level ^λ0' is input to the gates A of the first MOSFETs 21a and 21b of the second and fourth current driving units 20a and 20b, a logic level '0' is input to the gates B of the second MOSFETs 23a and 23b, and a logic level ^Λl' is input to the gates C of the third MOSFETs 25a and 25b. Meanwhile, a logic level ^Λl^f , an inverted signal, is input to the gates A of the first MOSFETs 31a and 31b of the first and third current driving units 30a and 30b, a logic level ^λl' , an inverted signal, is input to the gates B of the second MOSFETs 33a and 33b, and a logic level ^λ0' , an inverted signal, is input to the gates C of the third MOSFETs 35a and 35b.

That is, a voltage corresponding to the logic level ^Λl' is applied to the gate of the third MOSFET 25a of the second current driving unit 20a and to the gates of the first and second MOSFETs 31a and 33a of the first current driving unit 30a, so that current may flow between the drain and source of each of the MOSFETs 25a, 31a and 33a. Further, when the amount of current output from each MOSFET is assumed to be I, a current of I is output from the source of the third MOSFET 25a of the second current driving unit 201, and a current of I is output from each of the sources of the first and second MOSFETs 31a and 33a of the first current driving unit 30a. Since the MOSFETs 25a, 31a and 33a are connected in parallel, a current of 21 is output therefrom.

Further, the source of the third MOSFET 25a of the second current driving unit 20a is connected to the drain of the third current driving unit 30b, and the drain of the third current driving unit 30b is connected to the bottom electrode of the MTJ device 10. Accordingly, a current of I is applied to the MTJ device in a bottom to top direction. Since the sources of the first and second MOSFETs 31a and 33a of the first current driving unit 30a are connected to the top electrode 11 of the MTJ device 10, a current of 21 is applied to the MTJ device 10 in a top to bottom direction.

Current flowing in the top to bottom direction is defined as -I, and current flowing in the bottom to top direction is defined as +1, so that a current of I + (- 21) = - I is applied to the MTJ device 10. The magnetization direction of the free magnetic layer 17 is changed to a right direction, and the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are parallel in the same direction, and thus the magnetic resistance of the MTJ device 10 is ^Λ0' indicative of a logic level ^Λlow' (R_L =0) . The third row of Table 2 corresponds to the case of FIG. 6(c), and, here, the operation performed when ^λ0' is input to A, ^λl' is input to B, and ^λ0' is input to C is described below.

Here, a logic level ^Λ0' is input to the gates A of the first MOSFETs 21a and 21b of the second and fourth current driving units 20a and 20b, a logic level ^λl' is input to the gates B of the second MOSFETs 23a and 23b, and a logic level ^Λ0' is input to the gates C of the third MOSFETs 25a and 25b.

Meanwhile, a logic level ^Λl' , an inverted signal, is input to the gates A of the first MOSFETs 31a and 31b of the first and third current driving units 30a, 30b, a logic level ^λ0' , an inverted signal, is input to the gates B of the second MOSFETs 33a and 33b, and a logic level ^λl', an inverted signal, is input to the gates C of the third MOSFETs 35a and 35b. That is, a voltage corresponding to the logic level ^Λl' is applied to the gate of the second MOSFET 23a of the second current driving unit 20a and to the gates of the first and third MOSFETs 31a and 35a of the first current driving unit 30a, so that current may flow between the drain and source of each of the MOSFETs 23a, 31a and 35a.

Further, when the amount of current output from each MOSFET is assumed to be I, a current of I is output from the source of the second MOSFET 23a of the second current driving unit 20a, and a current of I is output from each of the sources of the first and third MOSFETs 31a and 35a of the first current driving unit 30a. Since the MOSFETs 23a, 31a and 35a are connected in parallel with each other, a current of 21 is output therefrom.

Further, since the source of the second MOSFET 23a of the second current driving unit 20a is connected to the drain of the third current driving unit 30b, and the drain of the third current driving unit 30b is connected to the bottom electrode of the MTJ device 10, a current of I is applied to the MTJ device 10 in a bottom to top direction. Since the sources of the first and third MOSFETs 31a and 35a of the first current driving unit 30a are connected to the top electrode 11 of the MTJ device 10, a current of 21 is applied to the MTJ device in the top to bottom direction.

Therefore, current flowing in the top to bottom direction is defined as - I and current flowing in the bottom to top direction is defined as + I, so that a current of I + (- 21) = - I is applied to the MTJ device 10. The magnetization direction of the free magnetic layer 17 is changed to a right direction, and the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are parallel in the same direction, and thus the magnetic resistance of the MTJ device 10 is ^Λ0' indicative of a logic level ^Λlow' (R_L = 0) .

The fourth row of Table 2 corresponds to the case of FIG. 6 (d) , and, here, the operation performed when ^Λl' is applied to A, and ^λ0' is applied both to B and to C is described below. In this case, a logic level ^λl' is input to the gates A of the first MOSFETs 21a and 21b of the second and fourth current driving units 20a and 20b, a logic level ^Λ0' is input to the gates B of the second MOSFETs 23a and 23b, and a logic level ^λ0' is input to the gates C of the third MOSFETs 25a and 25b.

Meanwhile, a logic level ^Λ0' , an inverted signal, is input to the gates A of the first MOSFETs 31a and 31b of the first and third current driving units 30a and 30b, a logic level ^Λl' , an inverted signal, is input to the gates B of the second MOSFETs 33a and 33b, and a logic level ^λl' is input to the gates C of the third MOSFETs 35a and 35b. That is, a voltage corresponding to a logic level ^Λl' is applied to the gate of the first MOSFET 21a of the second current driving unit 20a and to the gates of the second and third MOSFETs 33a and 35a of the first current driving unit 30a, so that current may flow between the drain and source of each of the MOSFETs 21a, 33a and 35a.

Further, when the amount of current output from each MOSFET is assumed to be I, a current of I is output from the source of the second MOSFET 23a of the second current driving unit 20a, and current of 21 is output from the sources of the second and third MOSFETs 33a and 35a of the first current driving unit 30a.

Further, since the source of the second MOSFET 23a of the second current driving unit 20a is connected to the drain of the third current driving unit 30b, and the drain of the third current driving unit 30b is connected to the bottom electrode of the MTJ device 10, a current of I is applied to the MTJ device 10 in a bottom to top direction. Since the sources of the second and third MOSFETs 33a and 35a of the first current driving unit 30a are connected to the top electrode 11 of the MTJ device 10, a current of 21 is applied to the MTJ device in a top to bottom direction.

Therefore, current flowing in the top to bottom direction is defined as -I, and current flowing in the bottom to top direction is defined as +1, so that current of I + (- 21) = - I is applied to the MTJ device 10. The magnetization direction of the free magnetic layer 17 is changed to a right direction, and the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are parallel in the same direction, and thus the magnetic resistance of the MTJ device 10 is ^Λ0' indicative of a logic level ^λlow' (R_L = 0) . The fifth row of Table 2 corresponds to the case of FIG. 6(e), and, here, the operation performed when ^y0' is applied to A, and ^λl' is applied both to B and to C is described below.

Here, a logic level ^λ0' is input to the gates A of the first MOSFETs 21a and 21b of the second and fourth current driving units 20a and 20b, a logic level ^Λl' is input to the gates B of the second MOSFETs 23a and 23b, and a logic level ^λl' is input to the gates C of the third MOSFETs 25a and 25b.

Meanwhile, a logic level ^yl' , an inverted signal, is input to the gates A of the first MOSFETs 31a and 31b of the first and third current driving units 30a and 30b, a logic level ^λ0' , an inverted signal, is input to the gates B of the second MOSFETs 33a and 33, and a logic level ^Λ0' , an inverted signal, is input to the gates C of the third MOSFETs 35a and 35b.

That is, a voltage corresponding to a logic level ^Λl' is applied to the gates of the second and third MOSFETs 23a and 25a of the second current driving unit 20a and to the gate of the first MOSFET 31a of the first current driving unit 30a, so that current may flow between the drain and source of each of the MOSFETs 23a, 25a and 31a.

Further, when the amount of current output from each MOSFET is assumed to be I, a current of 21 is output from the sources of the second and third MOSFETs 23a and 25a of the second current driving unit 20a, and a current of I is output from the source of the first MOSFET 31a of the first current driving unit 30a. Further, since the sources of the second and third MOSFETs 23a and 25a of the second current driving unit 20a are connected to the drain of the third current driving unit 30b, and the drain of the third current driving unit 30b is connected to the bottom electrode of the MTJ device 10, a current of 21 is applied to the MTJ device in a bottom to top direction. The source of the first MOSFET 31a of the first current driving unit 30a is connected to the top electrode 11 of the MTJ device 10, and thus a current of I is applied to the MTJ device 10 in the top to bottom direction. Therefore, current flowing in the top to bottom direction is defined as -I and current flowing in the bottom to top direction is defined as +1, so that a current of 21 + (-1) = I is applied to the MTJ device 10. The magnetization direction of the free magnetic layer 17 is changed to a left direction, and the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are parallel in opposite directions (anti-parallel) , so that the magnetic resistance of the MTJ device 10 is ^Λl' indicative of a logic level ^Λhigh' (R_H =1) .

The sixth row of Table 2 corresponds to the case of FIG. 6(f), and, here, the operation performed when ^λl' is applied to A, ^Λ0' is applied to B, and ^λl' is applied to C is described below.

In this case, a logic level ^Λl' is input to the gates A of the first MOSFETs 21a and 21b of the second and fourth current driving units 20a and 20b, a logic level ^λ0' is input to the gates B of the second MOSFETs 23a and 23b, and a logic level ^λl' is input to the gates C of the third MOSFETs 25a and 25b.

Meanwhile, a logic level ^λ0' , an inverted signal, is input to the gates A of the first MOSFETs 31a and 31b of the first and third current driving units 30a and 30b, a logic level '1', an inverted signal, is input to the gates B of the second MOSFETs 33a and 33b, and a logic level *0' , an inverted signal, is input to the gates C of the third MOSFETs 35a and 35b.

That is, a voltage corresponding to the logic level ^Λl' is applied to the gates of the first and third MOSFETs 21a and 25a of the second current driving unit 20a and to the gate of the second MOSFET 33a of the first current driving unit 30a, so that current may flow between the drain and source of each of the MOSFETs 21a, 25a and 33a.

Further, when the amount of current output from each MOSFET is assumed to be I, a current of 21 is output from each of the sources of the first and third MOSFETs 21a and 25a of the second current driving unit 20a, and a current of I is output from the source of the second MOSFET 33a of the first current driving unit 30a.

Further, since the sources of the first and third MOSFETs 21a and 25a of the second current driving unit 20a are connected to the drain of the third current driving unit 30b, and the drain of the third current driving unit 30b is connected to the bottom electrode of the MTJ device 10, a current of 21 is applied to the MTJ device 10 in a bottom to top direction. Since the source of the second MOSFET 33a of the first current driving unit 30a is connected to the top electrode 11 of the MTJ device 10, a current of I is applied to the MTJ device 10 in a top to bottom direction.

Therefore, current flowing in the top to bottom direction is defined as -I, and current flowing in the bottom to top direction is defined as +1, so that a current of 21 + (-1) = I is applied to the MTJ device 10. The magnetization direction of the free magnetic layer 17 is changed to a left direction, and the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are anti-parallel, and thus the magnetic resistance of the MTJ device 10 is ^Λl' indicative of a logic level ^Λhigh' (R_H = 1) .

The seventh row of Table 2 corresponds to the case of FIG. 6(g), and, here, the operation performed when '1' is applied to A, ^Λl^f is applied to B, and ^λ0' is applied to C is described below.

Here, a logic level ^λl' is input to the gates A of first

MOSFETs 21a and 21b of the second and fourth current driving units 20a and 20b, a logic level '1' is input to the gates B of the second MOSFETs 23a and 23b, and a logic level ^λ0' is input to the gates C of the third MOSFETs 25a and 25b.

Meanwhile, a logic level ^λ0' , an inverted signal, is input to the gates A of the first MOSFETs 31a and 31b of the first and third current driving units 30a and 30b, a logic level ^λ0' , an inverted signal, is input to the gates B of the second MOSFETs 33a and 33b, and a logic level ^Λl' , an inverted signal, is input to the gates C of the third MOSFETs 35a and 35b.

That is, a voltage corresponding to a logic level ^Λl' is applied to the gates of the first and second MOSFETs 21a and 23a of the second current driving unit 20a and to the gate of the third MOSFET 35a of the first current driving unit 30a, so that current may flow between the drain and source of each of the

MOSFETs 21a, 23a and 35a.

Further, when the amount of current output from each

MOSFET is assumed to be I, a current of 21 is output from each of the sources of the first and second MOSFETs 21a and 23a of the second current driving unit 20a, and a current of I is output from the source of the third MOSFET 35a of the first current driving unit 30a.

Further, since the sources of the first and second MOSFETs 21a and 23a of the second current driving unit 20a are connected to the drain of the third current driving unit 30b, and the drain of the third current driving unit 30b is connected to the bottom electrode of the MTJ device 10, a current of 21 is applied to the MTJ device in a bottom to top direction. Since the source of the third MOSFET 35a of the first current driving unit 30a is connected to the top electrode 11 of the MTJ device 10, a current of I is applied to the MTJ device in a top to bottom direction.

Therefore, current flowing in the top to bottom direction is defined as -I, and current flowing in the bottom to top direction is defined as +1, so that a current of 21 + (-1) = I is applied to the MTJ device 10. The magnetization direction of the free magnetic layer 17 is changed to a left direction, and the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are anti-parallel, and thus the magnetic resistance of the MTJ device 10 is ^xl' indicative of a logic level ^Λhigh' (R₁₁ = 1) .

The eighth row of Table 2 corresponds to the case of FIG. 6 (h) , and, here, the operation performed when ^Λl' is applied to A, B and C is described below. Here, a logic level ^λl' is input to the gates A of the first MOSFETs 21a and 21b of the second and fourth current driving units 20a and 20b, to the gates B of the second MOSFETs

23a and 23b, and to the gates C of the third MOSFETs 25a and

25b.

Meanwhile, a logic level ^Λ0, an inverted signal, is input to the gates A of the first MOSFETs 31a and 31b of the first and third current driving units 30a and 30b, to the gates B of the second MOSFETs 33a and 33b, and to the gates C of the third

MOSFETs 35a and 35b.

That is, a voltage corresponding to the logic level ^yl' is input to the gates of the first, second and third MOSFETs 21a,

23a, and 25a of the second current driving unit 20a, so that current may flow between the drain and source of each of the

MOSFETs 21a, 23a and 25a.

Further, when the amount of current output from each MOSFET is assumed to be I, a current of 31 is output from the sources of the first, second and third MOSFETs 21a, 23a, and 25a of the second current driving unit 20a.

Further, since the sources of the first, second and third

MOSFETs 21a, 23a and 25a of the second current driving unit 20a are connected to the drain of the third current driving unit

30b, and the drain of the third current driving unit 30b is connected of the bottom electrode of the MTJ device 10, a current of 31 is applied to the MTJ device 10 in a bottom to top direction. Therefore, the amount of current flowing in the top to bottom direction is defined as -I, and the amount of current flowing in the bottom to top direction is defined as +1, so that a current of 31 is applied to the MTJ device 10. The magnetization direction of the free magnetic layer 17 is changed to a left direction, and the magnetization directions of the free magnetic layer 17 and the pinned magnetic layer 15 are anti-parallel, and thus the magnetic resistance of the MTJ device 10 is ^Λl' indicative of a logic level ^λhigh' (R_H = 1) .

That is, the logic circuit is implemented to perform the logic operation given by the following Equation 1. [Equation 1]

R-A ^• B+B ^• C+C ^• A

FIG. 7 is a diagram conceptually showing the magnetic memory cell of FIG. 5, and FIG. 8 is a diagram conceptually showing an XOR logic operation apparatus according to the present invention.

As shown in FIG. 8, the XOR logic operation apparatus of the present invention includes two magnetic memory cells 100 and 200 connected in parallel with each other, and a sense AMP 300 connected to the first ends of the two respective memory cells . Each of the two magnetic memory cells 100 and 200 includes an MTJ device 10 (refer to FIG. 4) and a current control circuit 50 (refer to FIG. 5) .

The sense AMP 300 compares the resistances of MTJ devices provided in the two magnetic memory cells 100 and 200 with each other. When the resistance sensed at a terminal V₊ is greater than that sensed at a terminal V-, the output of the sense AMP 300 is a logic level '1', whereas when the resistance sensed at the terminal V₊ is equal to or less than that sensed at the terminal V-, the output of the sense AMP 300 is a logic level 'O¹.

For this operation, the offset voltage V_os of the terminal V- of the sense AMP 300 must satisfy the following equation.

0< V_OS< I _SSNS* AR(AR= R _JΓ R ₁)

The logic levels of resistances that are output according to logic levels input to the magnetic memory cell 100 are given by the following Table 3 (refer to Table 2) .

Table 3

Referring to Table 3, the magnetic memory cell 100 is operated as A OR B.

Further, the logic levels of resistances that are output according to logic levels input to the magnetic memory cell 200 are given by the following Table 4 (refer to Table 2) .

Table 4

Referring to Table 4, it can be seen that the magnetic memory cell 200 is operated as A AND B .

The logic levels obtained by comparing the resistance values at the terminal V₊ and the terminal V_ of the sense AMP 300 with each other are given by the following Table 5.

Table 5

Therefore, it can be seen that, in the XOR logic operation apparatus of the present invention, including the two parallel- connected magnetic memory cells 100 and 200, each composed of the MTJ device 10 and the current control circuit 50, and the sense AMP 300 connected to the two magnetic memory cells, the output value of the sense AMP (S/A OUT) is operated as an XOR logic value given by the following equation.

SlA OUT = V₊ + AND V

-(A OR By (A AND B) =(A+B) _ - (A+B) =A ^• B+A ^• B -A XOR B

Although the preferred embodiments of an XOR logic operation apparatus according to the present invention have has been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

[industrial Applicability]

As described above, an XOR logic operation apparatus according to the present invention can be variously applied to fields for micro-operation devices or memory devices because logic circuits operated at high speed can be constructed using MTJ devices.

Claims

[CLAIMS]

[Claim l]

An XOR logic operation apparatus using a Magnetic Tunnel Junction (MTJ) device, comprising: two magnetic memory cells connected in parallel with each other; and a sense amplifier connected to first ends of the two respective magnetic memory cells, wherein each of the magnetic memory cells comprises: an MTJ device including a top electrode and a bottom electrode configured to allow current to flow therethrough, an insulating layer configured to electrically insulate the top electrode from the bottom electrode, and a free magnetic layer and a pinned magnetic layer respectively formed on a top and a bottom of the insulating layer, and a current control circuit configured to control flow of current passing between the top electrode and the bottom electrode, and change a magnetization direction of the free magnetic layer according to an input logic level .

[Claim 2]

The XOR logic operation apparatus according to claim 1, wherein the magnetization direction of the pinned magnetic layer is fixed.

[Claim 3] The XOR logic operation apparatus according to claim 1, wherein the current control circuit is configured such that a logic level is formed by changing a signal input to a gate of the current control circuit.

[Claim 4]

The XOR logic operation apparatus according to claim 1, wherein, when current applied to the MTJ device flows in a direction from the top electrode to the bottom electrode, the magnetization direction of the free magnetic layer is identical to that of the pinned magnetic layer.

[Claim 5]

The XOR logic operation apparatus according to claim 1, wherein, when magnetization directions of the free magnetic layer and the pinned magnetic layer are identical to each other, a magnetic resistance of the MTJ device has a logic level ^λ0' .

[Claim β]

The XOR logic operation apparatus according to claim 1, wherein, when current applied to the MTJ device flows in a direction from the bottom electrode to the top electrode, the magnetization direction of the free magnetic layer is opposite that of the pinned magnetic layer.

[Claim 7] The XOR logic operation apparatus according to claim 1, wherein, when magnetization directions of the free magnetic layer and the pinned magnetic layer are opposite each other, resistance of the MTJ device has a logic level ^yl' .

[Claim 8]

The XOR logic operation apparatus according to claim 1, wherein the current control circuit comprises: a first current driving unit, a source of which is connected to the top electrode; a second current driving unit, a drain of which is connected to a drain of the first current driving unit; a third current driving unit, a drain of which is connected to the bottom electrode; and a fourth current driving unit, a source of which is connected to a source of the third current driving unit.

[Claim 9]

The XOR logic operation apparatus according to claim 8, wherein each of the first to fourth current driving units comprises three MOSFETs connected in parallel with each other.

[Claim 10]

The XOR logic operation apparatus according to claim 9, wherein the source of the first current driving unit is connected to the drain of the fourth current driving unit, and a source of the second current driving unit is connected to the drain of the third current driving unit.

[Claim ll]

The XOR logic operation apparatus according to claim 8, wherein the current control circuit further comprises : a first enable MOSFET, a first end of which is connected to a node to which the first current driving unit and the second current driving unit are connected; and a second enable MOSFET, a first end of which is connected to a node to which the third current driving unit and the fourth current driving unit are connected.

[Claim 12]

The XOR logic operation apparatus according to claim 8, wherein each of the first to fourth current driving units comprises: a first MOSFET having a gate to which a first logic input signal is applied; a second MOSFET having a gate to which a second logic input signal is applied; and a third MOSFET having a gate to which a third logic input signal is applied.

[Claim 13]

The XOR logic operation apparatus according to claim 12, wherein signals applied to gates of the MOSFETs constituting the first current driving unit are identical to signals applied to gates of the MOSFETs constituting the third current driving unit, respectively, and signals applied to gates of the MOSFETs constituting the second current driving unit are identical to signals applied to gates of the MOSFETs constituting the fourth current driving unit, respectively, wherein the signals applied to the first current driving unit and the signals applied to the second current driving unit have an inverted relationship with each other.

[Claim 14]

The XOR logic operation apparatus according to claim 1, wherein the sense amplifier is operated to compare resistance values of MTJ devices provided in the two magnetic memory cells with each other, and to output a logic level ^Λl' when a resistance value sensed at a terminal V₊ is greater than a resistance value sensed at a terminal V_.

[Claim 15]

The XOR logic operation apparatus according to claim 1, wherein the sense amplifier is operated to compare resistance values of MTJ devices provided in the two magnetic memory cells with each other, and to output a logic level ^λ0' when a resistance value sensed at a terminal V₊ is equal to or less than a resistance value sensed at a terminal V-.