WO2009104824A1

WO2009104824A1 - Device and method of demodulating signal

Info

Publication number: WO2009104824A1
Application number: PCT/KR2008/000951
Authority: WO
Inventors: Woo-Young Choi; Du-Ho Kim
Original assignee: Industry-Academic Cooperation Foundation, Yonsei University
Priority date: 2008-02-18
Filing date: 2008-02-18
Publication date: 2009-08-27
Also published as: KR100928611B1; KR20090089099A

Abstract

A method and device of demodulating a signal is provided. A device for demodulating a signal, the device including: a phase detection unit to detect phase information of an input signal based on a sampling result with respect to the input signal modulated into a carrier wave having a first frequency; a clock generation unit to generate a clock signal having a demodulation frequency synchronized with the input signal using the phase information; a sampling performing unit to perform sampling of the input signal in response to the generated clock signal; and a demodulation unit to demodulate the input signal based on a sampling result of the sampling performing unit, wherein the first frequency is an integral multiple of the demodulation frequency.

Description

DEVICE AND METHOD OF DEMODULATING SIGNAL

Technical Field

The present invention relates to a technology of demodulating a signal received from various communication environments including a wireless communication environment.

Background Art

Interests in an ultrahigh frequency band such as a frequency band higher than or equal to 60 GHz have recently increased. Research with respect to designing a wireless circuit to receive a signal of the ultrahigh frequency band and to process the received signal is actively conducted.

A wireless receiver for the signal of the ultrahigh frequency band generally receives the signal using a superheterodyne scheme, and demodulates the received signal. Specifically, the wireless receiver according to the superheterodyne scheme converts the received signal into a signal of an intermediate frequency, and demodulates the converted signal. In this instance, the intermediate frequency may be adjusted.

Since an operation frequency of a phase synchronization loop used for converting a wireless signal into the intermediate frequency increases as the intermediate frequency decreases, designing the wireless receiver having low phase noise is difficult. As the intermediate frequency decreases, designing a band pass filter for a wide band signal is difficult. Conversely, since a demodulator needs to demodulate a signal of a high frequency as the intermediate frequency increases, designing the demodulator is difficult.

Disclosure of Invention

Technical Goals

The present invention provides a device and method of demodulating a signal which can demodulate an input signal of a high frequency even when a demodulator uses a low demodulation frequency, thereby reducing burden generated when designing a circuit of a receiver.

The present invention also provides a device and method of demodulating a signal which can demodulate a received signal having a high frequency using a demodulator using a low demodulation frequency a need for converting the received signal into a signal of an intermediate frequency.

The present invention also provides a device and method of demodulating a signal which can demodulate an input signal having a high frequency using a demodulator with a simple structure, thereby miniaturizing a receiver and reducing power consumption of the receiver.

Technical solutions According to an aspect of the present invention, there is provided a device for demodulating a signal, the device including: a phase detection unit to detect phase information of an input signal based on a sampling result with respect to the input signal modulated into a carrier wave having a first frequency; a clock generation unit to generate a clock signal having a demodulation frequency synchronized with the input signal using the phase information; a sampling performing unit to perform sampling of the input signal in response to the generated clock signal; and a demodulation unit to demodulate the input signal based on a sampling result of the sampling performing unit, wherein the first frequency is an integral multiple of the demodulation frequency.

According to another aspect of the present invention, there is provided a receiver including: at least one antenna to receive a modulated transmission signal; an amplifier to amplify a power of the received transmission signal; a mixer to be connected with the amplifier, to convert a frequency of the transmission signal, and to generate an input signal having a first frequency; and a signal demodulation unit to demodulate the input signal having the first frequency using a clock signal having a second frequency, wherein the first frequency is an integral multiple of the second frequency.

According to still another aspect of the present invention, there is provided a method of demodulating a signal, the method including: detecting phase information of an input signal based on a sampling result with respect to the input signal modulated into a carrier wave having a first frequency; generating a clock signal having a demodulation frequency synchronized with the input signal using the phase information; performing sampling of the input signal in response to the generated clock signal; and demodulating the input signal based on a sampling result generated from the performed sampling of the input signal.

According to yet another aspect of the present invention, there is provided a method of receiving a signal, the method including: receiving a modulated transmission signal using at least one antenna; amplifying a power of the received transmission signal using an amplifier; converting a frequency of the transmission signal and generating an input signal having a first frequency using a mixer connected with the amplifier; and demodulating the input signal having the first frequency using a clock signal having a second frequency.

Brief Description of Drawings

FIG. 1 illustrates a general Costas loop;

FIG. 2 is a block diagram illustrating a wireless receiver using a low intermediate frequency and using a demodulation frequency equal to an intermediate frequency;

FIG. 3 is a block diagram illustrating a demodulator of FIG. 2;

FIG. 4 is a timing diagram illustrating an operation of the demodulator of FIG. 2;

FIG. 5 is a block diagram illustrating a wireless receiver using a high intermediate frequency and using a demodulation frequency lower than an intermediate frequency according to an exemplary embodiment of the present invention;

FIG. 6 is a block diagram illustrating a demodulator of FIG. 5;

FIG. 7 is a timing diagram illustrating an operation of the demodulator of FIG. 5; and FIG. 8 is a flowchart illustrating a method of demodulating a signal according to an exemplary embodiment of the present invention.

Best Mode for Carrying Out the Invention

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures. FIG. 1 illustrates a general Costas loop.

Referring to FIG. 1, the Costas loop includes three mixers 110, 130, and 160, two Low Pass Filters (LPFs) 120 and 170, a loop filter 140, and a Voltage Controlled Oscillator (VCO) 150. The mixer 110 mixes a modulated signal (m(t)cos(wt)) inputted from an outside and a sine wave signal (cos(wt+θ)) outputted from the VCO 150. Similarly, the mixer 160 mixes the modulated signal (m(t)cos(wt)) inputted from the outside and a sine wave signal (sin(wt+θ)). The two LPFs 120 and 170 filter a signal inputted from the mixers 110 and 160. Here, θ denotes a phase difference between a transmitter and a receiver. The signal inputted into the LPF 120 corresponds to m(t)cos(wt)*cos(wt+θ)=m(t){cosθ + cos(2wt+θ)}/2, and the signal inputted into the LPF 170 corresponds to m(t)cos(wt)*sin(wt+θ)= m(t){sinθ + sin(2wt+θ)}/2. Each LPF 120 and 170 outputs m(t)cosθ and m(t)sinθ. Since θ converges at '0', m(t) may be restored. The mixer 130 mixes signals outputted from the LPFs 120 and 170, and outputs the mixed signal (sin(θ)) to the loop filter 140. The mixed signal (sin(θ)) is outputted to the VCO 150 through the loop filter 140. The VCO 150 generates an oscillation signal using the signal outputted from the loop filter 140.

Designing the LPF to restore a carrier wave including a high frequency using the Costas loop is difficult. In particular, an analog filter has a low flatness of a frequency response in a high frequency band, and has a large circuit area.

FIG. 2 is a block diagram illustrating a wireless receiver using a low intermediate frequency and using a demodulation frequency equal to an intermediate frequency. Referring to FIG. 2, the wireless receiver includes an antenna 210, an amplifier

220, a mixer 230, a phase synchronization loop 240, and a demodulator 250.

The antenna 210 receives a transmission signal having a transmission frequency of f_RF transmitted from a transmitter. The amplifier 220 amplifies a power of the received transmission signal. The mixer 230 converts a frequency of the received signal into an input signal with respect to the demodulator 250 having a frequency of fø using a signal having a frequency of f_RF-fiF inputted from the phase synchronization loop 240. Here, fip is an intermediate frequency, and is equal to a demodulation frequency operated by the demodulator 250.

The demodulator 250 demodulates the received signal converted into the signal having the intermediate frequency fjp. Accordingly, since the received signal is converted into the signal having the intermediate frequency ftp and is subsequently demodulated, the received signal certainly needs to be converted into the signal having the intermediate frequency fø using the mixer 230 in the wireless receiver illustrated in FIG. 2.

Since a frequency used by the phase synchronization loop 240 increases as the intermediate frequency f^ decreases, a problem that phase noise of the phase synchronization loop 240 increases occurs. As the intermediate frequency f^ decreases, designing a band pass filter operated in a high frequency band becomes more difficult. Conversely, as the demodulation frequency operated by the demodulator 250 increases when the intermediate frequency fjp increases, designing the demodulator 250 becomes more difficult.

FIG. 3 is a block diagram illustrating the demodulator 250 of FIG. 2 Referring to FIG. 3, the demodulator 250 includes a phase detection unit 310, a clock generation unit 320, a sampling performing unit 330, a demodulation unit 340, a filter 350, and a Clock Data Recovery (CDR) 360. The phase detection unit 310 detects phase information of the input signal based on a sampling result with respect to the input signal with respect to the demodulator 250. Here, the input signal is a signal of passing through a mixer and having an intermediate frequency fjp.

The clock generation unit 320 generates the clock signal synchronized with the input signal using the phase information. Here, the clock signal has a demodulation frequency being a unique operation frequency of the demodulator 250, and the demodulation frequency in the demodulator 250 illustrated in FIG. 3 is equal to the intermediate frequency fiF-

The sampling performing unit 330 performs sampling of the input signal in response to the clock signal having the intermediate frequency fjp. Specifically, the sampling performing unit 330 performs sampling of the input signal in response to the clock signal rising or falling based on the demodulation frequency. The sampling performing unit 330 performs the sampling of the input signal when a rising edge and a falling edge of the clock signal occur.

The demodulation unit 340 demodulates the input signal using the sampling result of the sampling performing unit 330. The filter 350 eliminates noise of the demodulated input signal, and the CDR

360 restores a clock and data from the demodulated input signal. The filter 350 and the CDR 360 may be omitted as required.

The demodulator 250 illustrated in FIG. 3 demodulates the input signal having the intermediate frequency fi_F using the demodulation frequency equal to the intermediate frequency ftp. The demodulator 250 illustrated in FIG. 3 may efficiently demodulate the input signal without using an analog LPF and the like as described with reference to FIG. 1. Since the intermediate frequency fjp and the demodulation frequency operated by the demodulator 250 are equal in the demodulator 250 illustrated in FIG. 3, the mixer is absolutely required. The input signal certainly needs to be converted into the signal having the intermediate frequency fiF. In particular, when the intermediate frequency ftp is high, designing the demodulator 250 having the high demodulation frequency is difficult.

FIG. 4 is a timing diagram illustrating an operation of the demodulator 250 of FIG. 2. Referring to FIG. 4, an original signal is illustrated in (a), and when the original signal is modulated based on a Binary Phase Shift Keying (BPSK) scheme using a carrier wave illustrated in (b), the modulated signal is illustrated in (c). The modulated signal is inputted into the demodulator 250 as an input signal, and it is assumed for convenience of descriptions that the modulated signal has an intermediate frequency. The demodulator 250 generates a clock signal having the intermediate frequency. As illustrated in (d), the demodulator 250 may generate the clock signal rising or falling when the modulated signal corresponds to a peak, using phase information of the input signal.

Since it is assumed that the modulated signal is modulated by BPSK with reference to FIG. 4, a clock signal (a dotted line) having the same phase as a phase of a carrier wave and a clock signal having a phase difference of π/2 from the phase of the carrier wave are illustrated. The modulated signal may be modulated by an N-PSK scheme, N denoting a natural number. In this case, the demodulator 250 may generate N clock signals, and each of the N clock signals has a phase difference of π/N.

The demodulator 250 performs sampling of the modulated signal when a rising edge and a falling edge of the clock signal occur. Accordingly, the sampled level may be illustrated in (e).

The demodulator 250 non-inverts the sampling result generated when the rising edge of the clock signal occurs, inverts the sampling result generated when the falling edge of the clock signal occurs, and demodulates the modulated signal. Accordingly, the demodulated level may be illustrated in (f), and the original signal may be demodulated similar to (g).

An operation of the demodulator 250 when the demodulation frequency of the demodulator 250 and the intermediate frequency are equal is described with reference to

FIG. 4, and operations of an exemplary embodiment of the present invention when the intermediate frequency does not exist or the intermediate frequency is higher than the demodulation frequency are described with reference to FIGS. 5 through 8.

FIG. 5 is a block diagram illustrating a wireless receiver using a high intermediate frequency and using a demodulation frequency lower than an intermediate frequency according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the receiver according to an exemplary embodiment of the present invention includes an antenna 510, an amplifier 520, a mixer 530, a phase synchronization loop 540, and a demodulator 550. Here, the mixer 530 and the phase synchronization loop 540 may be omitted when a frequency of a received signal f_RF and a frequency of an input signal Nf_dem with respect to the demodulator 550 are equal. Here, N denotes an integer. The antenna 510 receives a transmission signal having a transmission frequency of f_RF transmitted from a transmitter. The amplifier 520 amplifies a power of the received transmission signal.

The mixer 530 converts the frequency of the received signal into the input signal with respect to the demodulator 550 having the frequency of Nfd_em using a signal having a frequency of f_RF-Nf_dem inputted from the phase synchronization loop 540.

Since the phase synchronization loop 540 may use a frequency relatively lower than a frequency used by the phase synchronization loop 240 illustrated in FIG. 2, the phase synchronization loop 540 may be designed to be robust against phase noise.

The demodulator 550 demodulates the input signal having the frequency of

Nf_dem using the demodulation frequency f_dem. Specifically, even when the frequency of the input signal Nf_dem is higher than the demodulation frequency f_dem, the demodulator 550 may demodulate the input signal without increasing the demodulation frequency f_dem- Accordingly, designing the demodulator 550 may be simplified.

FIG. 6 is a block diagram illustrating the demodulator 550 of FIG. 5.

Referring to FIG. 6, the demodulator 550 includes a phase detection unit 610, a clock generation unit 620, a sampling performing unit 630, a demodulation unit 640, a filter 650, and a CDR 660.

The phase detection unit 610 detects phase information of the input signal based on a sampling result with respect to the input signal with respect to the demodulator 550. Here, the input signal may be a signal of passing through a band pass filter and eliminating noise, and may be a signal of passing through a mixer as required. Specifically, when a transmission frequency of a transmitter corresponds to Nf_dem, the mixer may be unnecessary, however, when the transmission frequency is different from Nf_dem, the input signal may be the signal of passing through the mixer. The input signal is a signal of being modulated according to a PSK, and may have a frequency included in a range from 57 GHz to 66 GHz. The clock generation unit 620 generates the clock signal synchronized with the input signal using the phase information. Here, the clock signal has a demodulation frequency f_dem being a unique operation frequency of the demodulator 550. The clock generation unit 620 generates the clock signal having a phase difference corresponding to a modulation scheme of the input signal and rising or falling. The sampling performing unit 630 performs sampling of the input signal in response to the clock signal having the demodulation frequency f_dem- Specifically, the sampling performing unit 630 performs sampling of the input signal in response to the clock signal rising or falling based on the demodulation frequency f_dem- The sampling performing unit 630 performs the sampling of the input signal when a rising edge and a falling edge of the clock signal occur.

The demodulation unit 640 demodulates the input signal based on a sampling result of the sampling performing unit 630. Specifically, the demodulation unit 640 non-inverts the sampling result generated when the rising edge of the clock signal occurs, inverts the sampling result generated when the falling edge of the clock signal occurs, and demodulates the input signal.

The filter 650 eliminates noise of the demodulated input signal, and the CDR 660 restores a clock and data from the demodulated input signal. The filter 650 and the CDR 660 may be omitted as required.

A specific operation of the demodulator 550 illustrated in FIG. 5 and FIG. 6 is described in detail with reference to FIG. 7.

FIG. 7 is a timing diagram illustrating an operation of the demodulator 550 of FIG. 5.

Referring to FIG. 7, an original signal is illustrated in (a), and items illustrated (a) through (g) of FIG. 4 are similarly illustrated in (a) through (g) of FIG. 7. Hereinafter, it is assumed that N denotes 5 and a frequency of an input signal Nf_dem is five times higher than a demodulation frequency of the demodulator 550. Referring to a modulated signal illustrated in (c), a signal modulated into a frequency of 5f_dem may be illustrated in (h). The demodulator 550 may perform sampling of the signal modulated into the frequency of 5f_dem using a clock signal having a frequency of f_dem illustrated in (d). Sampled levels may be illustrated in (i).

With respect to the sampled levels illustrated in (i), the demodulator 550 non- inverts the sampling result generated when a rising edge of the clock signal occurs, inverts the sampling result generated when a falling edge of the clock signal occurs, and acquires the demodulated level. The demodulated level may be illustrated in (j), and a demodulated signal illustrated in (k) may be acquired.

Referring to FIG. 7, the demodulator 550 may accurately demodulate the input signal using the demodulation frequency f_dem lower than the frequency of the input signal 5f_dem. Therefore, according to an exemplary embodiment of the present invention, efforts to convert the frequency of the input signal into an intermediate frequency may be reduced, and the demodulation frequency increased no further than need be. FIG. 8 is a flowchart illustrating a method of demodulating a signal according to an exemplary embodiment of the present invention.

Referring to FIG. 8, in operation S810, the method of demodulating the signal according to an exemplary embodiment of the present invention detects phase information of an input signal based on a sampling result with respect to the input signal modulated into a carrier wave having a first frequency.

In operation S820, the method of demodulating the signal according to an exemplary embodiment of the present invention generates a clock signal having a demodulation frequency synchronized with the input signal using the phase information.

In operation S830, the method of demodulating the signal according to an exemplary embodiment of the present invention performs sampling of the input signal in response to the generated clock signal. In operation S 840, the method of demodulating the signal according to an exemplary embodiment of the present invention demodulates the input signal based on a sampling result generated from the performed sampling of the input signal in operation S830.

Descriptions referring to FIGS. 1 through 7 may be applied to the method of demodulating the signal according to an exemplary embodiment of the present invention, and detailed descriptions with respect to the method of demodulating the signal according to an exemplary embodiment of the present invention are omitted.

The method of demodulating the signal and the method of receiving the signal according to the exemplary embodiments of the present invention may be recorded in computer-readable media including program instructions to implement various operations embodied by a computer. The media may also include, alone or in combination with the program instructions, data files, data structures, and the like. The media and program instructions may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer- readable media include magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD ROM disks and DVD; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and perform program instructions, such as read-only memory (ROM), random access memory (RAM), flash memory, and the like. Examples of program instructions include both machine code, such as produced by a compiler, and files containing higher level code that may be executed by the computer using an interpreter. The described hardware devices may be configured to act as one or more software modules in order to perform the operations of the above-described embodiments of the present invention.

According to the present invention, there is provided a device and method of demodulating a signal which can demodulate an input signal of a high frequency even when a demodulator uses a low demodulation frequency, thereby reducing burden generated when designing a circuit of a receiver.

Also, according to the present invention, there is provided a device and method of demodulating a signal which can demodulate a received signal having a high frequency using a demodulator using a low demodulation frequency eliminating a need for converting the received signal into a signal of an intermediate frequency.

Also, according to the present invention, there is provided a device and method of demodulating a signal which can demodulate an input signal having a high frequency using a demodulator with a simple structure, thereby miniaturizing a receiver and reducing power consumption of the receiver. Although a few embodiments of the present invention have been shown and described, the present invention is not limited to the described embodiments. Instead, it would be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A device for demodulating a signal, the device comprising: a phase detection unit to detect phase information of an input signal based on a sampling result with respect to the input signal modulated into a carrier wave having a first frequency; a clock generation unit to generate a clock signal having a demodulation frequency synchronized with the input signal using the phase information; a sampling performing unit to perform sampling of the input signal in response to the generated clock signal; and a demodulation unit to demodulate the input signal based on a sampling result of the sampling performing unit, wherein the first frequency is an integral multiple of the demodulation frequency.

2. The device of claim 1, wherein the sampling performing unit performs the sampling of the input signal when a rising edge and a falling edge of the clock signal occur.

3. The device of claim 1, wherein the clock generation unit generates the clock signal having a phase difference corresponding to a modulation scheme of the input signal and rising or falling.

4. The device of claim 1, wherein the demodulation unit non-inverts the sampling result generated when a rising edge of the clock signal occurs, inverts the sampling result generated when a falling edge of the clock signal occurs, and demodulates the input signal.

5. The device of claim 1, wherein the input signal is a signal of being modulated according to a Phase Shift Keying (PSK).

6. The device of claim 1 , wherein the first frequency is a frequency included in a range from 57 GHz to 66 GHz.

7. A receiver comprising: at least one antenna to receive a modulated transmission signal; an amplifier to amplify a power of the received transmission signal; a mixer to be connected with the amplifier, to convert a frequency of the transmission signal, and to generate an input signal having a first frequency; and a signal demodulation unit to demodulate the input signal having the first frequency using a clock signal having a second frequency, wherein the first frequency is an integral multiple of the second frequency.

8. The receiver of claim 7, wherein the signal demodulation unit comprises: a phase detection unit to detect phase information of the input signal based on a sampling result with respect to the input signal having the first frequency; a clock generation unit to generate the clock signal having the second frequency synchronized with the input signal using the phase information; a sampling performing unit to perform sampling of the input signal in response to the generated clock signal; and a demodulation unit to demodulate the input signal based on the sampling result of the sampling performing unit.

9. The receiver of claim 8, wherein the demodulation unit non- inverts the sampling result generated when a rising edge of the clock signal occurs, inverts the sampling result generated when a falling edge of the clock signal occurs, and demodulates the input signal.

10. A method of demodulating a signal, the method comprising: detecting phase information of an input signal based on a sampling result with respect to the input signal modulated into a carrier wave having a first frequency; generating a clock signal having a demodulation frequency synchronized with the input signal using the phase information; performing sampling of the input signal in response to the generated clock signal; and demodulating the input signal based on a sampling result generated from the performed sampling of the input signal, wherein the first frequency is an integral multiple of the demodulation frequency.

11. The method of claim 10, wherein the demodulating non-inverts the sampling result generated when a rising edge of the clock signal occurs, inverts the sampling result generated when a falling edge of the clock signal occurs, and demodulates the input signal.

12. The method of claim 10, wherein the performing performs the sampling of the input signal when a rising edge and a falling edge of the clock signal occur.

13. A method of receiving a signal, the method comprising: receiving a modulated transmission signal using at least one antenna; amplifying a power of the received transmission signal using an amplifier; converting a frequency of the transmission signal and generating an input signal having a first frequency using a mixer connected with the amplifier; and demodulating the input signal having the first frequency using a clock signal having a second frequency, wherein the first frequency is an integral multiple of the second frequency.

14. The method of claim 13 , wherein the demodulating comprises : detecting phase information of the input signal based on a sampling result with respect to the input signal having the first frequency; generating the clock signal having the second frequency synchronized with the input signal using the phase information; performing sampling of the input signal in response to the generated clock signal; and demodulating the input signal based on the sampling result generated from the performed sampling of the input signal.