KR20090089099A - Device and method of demodulating signal - Google Patents

Abstract

A method and an apparatus for demodulating a signal are provided to reduce power consumption of a receiver by demodulating an input signal having a high frequency through a demodulator having a simple structure. A phase detecting part(610) detects phase information of an input signal based on a sampling result about the input signal modulated as a carrier wave having a first frequency. A clock generating part(620) generates a clock signal having a demodulation frequency which is synchronized with the input signal by the phase information. A sampling part(630) samples the input signal in response to the generated clock signal. The sampling part samples the input signal in a time in which a rising edge and a falling edge of the clock signal are generated. A demodulating part(640) demodulates the input signal based on a sampling result of the sampling part.

Description

Signal demodulation method and apparatus therefor {DEVICE AND METHOD OF DEMODULATING SIGNAL}

The present invention relates to techniques for demodulating received signals in various communication environments, including wireless communication environments.

Recently, interest in ultra-high frequency bands such as the frequency band of 60 GHz or more is increasing. In addition, research on the design of a radio circuit for receiving signals in the ultra-high frequency band and processing the received signals has been actively conducted.

Wireless receivers for signals in the ultra-high frequency band generally receive signals using a superheterodyne scheme and demodulate the received signals. That is, the wireless receiver according to the superheterodyne scheme converts the received signal into a signal of intermediate frequency and demodulates the converted signal. At this time, the intermediate frequency can be adjusted.

The lower the intermediate frequency, the higher the operating frequency of the phase locked loop used to convert the radio signal to the intermediate frequency, making it difficult to design a wireless receiver with low phase noise. In addition, the lower the intermediate frequency, the more difficult it is to design a band pass filter for a wide band signal. On the contrary, as the intermediate frequency is higher, the demodulator must demodulate a high frequency signal, which makes it difficult to design the demodulator.

The present invention provides a signal demodulation device and method which can reduce the burden incurred in designing a circuit of a receiver by demodulating a high frequency input signal even when the demodulator uses a low demodulation frequency.

The present invention also provides a signal demodulation device and method for demodulating a received signal having a high frequency using a demodulator using a low demodulation frequency without converting the received signal into a signal of an intermediate frequency.

In addition, the present invention provides a signal demodulation apparatus and method capable of miniaturizing a receiver and reducing power consumption of the receiver by demodulating an input signal having a high frequency using a demodulator having a simple structure.

A signal demodulation device according to an embodiment of the present invention is a phase detector for detecting phase information of the input signal based on a sampling result of an input signal modulated with a carrier having a first frequency, the input using the phase information A clock generator for generating a clock signal having a demodulation frequency synchronized with the signal, a sampling processor for sampling the input signal in response to the generated clock signal, and a demodulation of the input signal based on a sampling result of the sampling processor; And a demodulation section, wherein the first frequency is an integer multiple of the demodulation frequency.

In addition, the receiver according to an embodiment of the present invention is connected to at least one antenna for receiving a modulated transmission signal, an amplifier for amplifying the power of the received transmission signal, the amplifier, and converts the frequency of the transmission signal A signal demodulator for demodulating the input signal having the first frequency by using a mixer for generating an input signal having a first frequency and a clock signal having a second frequency, wherein the first frequency is an integer multiple of the second frequency. to be.

In addition, the signal demodulation method according to an embodiment of the present invention detects the phase information of the input signal based on the sampling result of the input signal modulated with a carrier having a first frequency, the phase information using the phase information Generating a clock signal having a demodulation frequency synchronized with an input signal, sampling the input signal in response to the generated clock signal, and sampling the input signal according to a sampling result generated from the sampling of the input signal. Demodulating.

In addition, according to an embodiment of the present invention, a signal receiving method includes receiving a modulated transmission signal through at least one antenna, amplifying the power of the received transmission signal using an amplifier, and a mixer connected to the amplifier Converting the frequency of the transmission signal to generate an input signal having a first frequency and demodulating the input signal having the first frequency using a clock signal having a second frequency.

The present invention can provide a signal demodulation device and a method for reducing the burden incurred in designing a circuit of a receiver by demodulating a high frequency input signal even when the demodulator uses a low demodulation frequency.

Further, the present invention can provide a signal demodulation device and method for demodulating a received signal having a high frequency using a demodulator using a low demodulation frequency without converting the received signal into a signal of an intermediate frequency.

In addition, the present invention can provide a signal demodulation device and method for miniaturizing a receiver by reducing the power consumption of the receiver by demodulating an input signal having a high frequency by using a demodulator having a simple structure.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a typical Costas loop.

Referring to FIG. 1, the Costas loop includes three mixers 110, 130 and 160, two low pass filters 120 and 170, a loop filter 140 and a voltage controlled oscillator 150. .

The mixer 110 mixes the modulated signal m (t) cos (wt) input from the outside and the sinusoidal signal cos (wt + θ) output from the VCO 150. Similarly, the mixer 160 mixes the modulated signal m (t) cos (wt) input from the outside and the sinusoidal signal sin (wt + θ). The two low pass filters 120 and 170 filter the signal input from the mixers 110 and 160. Where θ is the phase difference between the transmitter and the receiver.

The signal input to the low pass filter 120 is m (t) cos (wt) * cos (wt + θ) = m (t) {cos θ + cos (2wt + θ)} / 2, and the low pass filter ( Signal input to 170 is m (t) cos (wt) * sin (wt + θ) = m (t) {sinθ + sin (2wt + θ)} / 2. At this time, each of the low pass filters 120 and 170 outputs m (t) cosθ and m (t) sinθ. At this time, since θ converges to '0', m (t) can be finally restored.

Meanwhile, the mixer 130 mixes signals output from the low pass filters 120 and 170, and outputs the mixed signal sin (θ) to the loop filter 140. The mixed signal sin (θ) is output to the VCO 150 via the loop filter 140. The VCO 150 generates an oscillation signal using the signal output from the loop filter 140.

However, there is a difficulty in designing an LPF to recover a carrier having a high frequency using a Costas loop. In particular, the analog filter has poor flatness of the frequency response in the high frequency band and has a large circuit area.

2 is a block diagram illustrating a wireless receiver using a low intermediate frequency and using the same demodulation frequency as the intermediate frequency.

Referring to FIG. 2, the wireless receiver includes an antenna 210, an amplifier 220, a mixer 230, a phase locked loop 240, and a demodulator 250.

The antenna 210 receives a transmission signal having a transmission frequency of f _RF transmitted from the transmitter. At this time, the amplifier 220 amplifies the power of the received signal.

In addition, the mixer 230 converts the frequency of the received signal into an input signal to the demodulator 250 having a frequency of f _IF using a signal having a frequency of f _RF -f _IF input from the phase locked loop 240. To convert. Here, f _IF is an intermediate frequency and is equal to the demodulation frequency at which the demodulator 250 operates.

Demodulator 250 demodulates the received signal converted into a signal having an intermediate frequency f _IF . Thus, since the received signal is converted to a signal having an intermediate frequency f _IF and then demodulated, in the wireless receiver shown in FIG. 2, the received signal must have an intermediate frequency f _IF through the mixer 230. Must be converted into a signal.

However, since the lower the intermediate frequency f _IF , the higher the frequency used in the phase locked loop 240, the phase noise of the phase locked loop 240 increases. In addition, the lower the intermediate frequency f _IF , the more difficult it is to design a band pass filter that operates in the higher frequency band. On the contrary, when the intermediate frequency f _IF is high, since the demodulation frequency at which the demodulator 250 operates is increased, the design of the demodulator 250 becomes difficult.

3 is a block diagram illustrating the demodulator 250 shown in FIG. 2.

2, the demodulator 250 includes a phase detector 310, a clock generator 320, a sampling performer 330, a demodulator 340, a filter 350, and a clock data recovery (CDR) 360. It includes.

The phase detector 310 detects phase information of the input signal based on a sampling result of the input signal to the demodulator 250. Here, the input signal is a signal having an intermediate frequency f _IF as a signal passed through the mixer.

In addition, the clock generator 320 generates a clock signal synchronized with the input signal using the phase information. Here, the clock signal has a demodulation frequency which is an operating frequency inherent to the demodulator 250. In the demodulator 250 shown in FIG. 3, the demodulation frequency is equal to the intermediate frequency f _IF .

In addition, the sampling performing unit 330 samples the input signal in response to the clock signal having the intermediate frequency f _IF . That is, the sampling performer 330 samples the input signal in response to the clock signal rising or falling according to the demodulation frequency. In this case, the sampling performing unit 330 may sample the input signal at the time when the rising edge and the falling edge of the clock signal occur.

In addition, the demodulator 340 demodulates the input signal using the sampling result of the sampling performer 330.

In addition, filter 350 removes noise in the demodulated input signal, and CDR 360 recovers clock and data from the demodulated input signal. In this case, the filter 350 and the CDR 360 may be omitted in some cases.

Consequently, the demodulator 250 shown in Figure 3, an input signal having an intermediate frequency (f _IF) is demodulated using the same demodulator frequency and intermediate frequency (f _IF). The demodulator 250 illustrated in FIG. 3 may efficiently demodulate an input signal without using an analog low pass filter as described with reference to FIG. 1. However, since the demodulator 250 illustrated in FIG. 3 has the same demodulation frequency at which the intermediate frequency f _IF and the demodulator 250 operate, a mixer is required. Further, the input and the signal must be converted into a signal having an intermediate frequency (f _IF), in particular, if the intermediate frequency (f _IF) is high, it is difficult to design the demodulator 250 with a high demodulation frequency.

4 is a timing diagram illustrating an example of an operation of the demodulator 250 illustrated in FIG. 2.

Referring to FIG. 4, when the original signal is as shown in (a), and the original signal is modulated according to the BPSK scheme using a carrier wave as shown in (b), the modulated signal is (c) Can be expressed as: At this time, the modulated signal is input to the demodulator 250 as an input signal, for the convenience of description it is assumed that the modulated signal has an intermediate frequency.

The demodulator 250 generates a clock signal having an intermediate frequency. In this case, as shown in (d), the demodulator 250 may generate a clock signal that rises or falls at a time when the modulated signal peaks using the phase information of the input signal.

At this time, since it is assumed that the modulated signal is modulated by BPSK in relation to FIG. have. However, the modulated signal may be modulated according to the N-PSK (N is a natural number) scheme. In this case, the demodulator 250 may generate N clock signals, and each of the N clock signals is π /. Has a phase difference of N.

Demodulator 250 samples the modulated signal at the time that the rising and falling edges of the clock signal occur. Thus, the sampled level can be shown as (e).

The demodulator also demodulates the modulated signal by non-inverting the sampling result generated at the time when the rising edge of the clock signal occurs, and inverting the sampling result generated at the time when the falling edge of the clock signal occurs. do. As a result, the demodulated level can be shown as (f), and the original signal can be demodulated as (G).

Referring to FIG. 4, when the demodulation frequency of the demodulator 250 and the intermediate frequency are the same, an example of the operation of the demodulator 250 has been described. With reference to FIGS. If higher, the operation of the present invention will be described.

5 is a block diagram illustrating a wireless receiver using a high intermediate frequency and using a demodulation frequency lower than the intermediate frequency.

Referring to FIG. 5, a receiver according to an embodiment of the present invention includes an antenna 510, an amplifier 520, a mixer 530, a phase locked loop 540, and a demodulator 550. Here, the mixer 530 and the phase locked loop 540 may be omitted when the frequency f _RF of the received signal and the frequency Nf _dem of the input signal to the demodulator 550 are the same. Where N is an integer.

Antenna 510 receives a transmission signal having a transmission frequency of f _RF transmitted from a transmitter. At this time, the amplifier 220 amplifies the power of the received signal.

In addition, the mixer 530 uses a signal having a frequency of f _RF -Nf _dem input from the phase locked loop 540 as the input signal to the demodulator 250 having a frequency of Nf _dem . To convert. In this case, since the phase locked loop 540 may use a frequency lower than the frequency used by the phase locked loop 240 shown in FIG. 2, the phase locked loop 540 may be designed to be robust to phase noise.

The demodulator 550 demodulates an input signal having a frequency of Nf _dem using a demodulation frequency of f _dem . That is, even if the frequency Nf _dem of the input signal is higher than the demodulation frequency f _dem , the demodulator 550 can demodulate the input signal without increasing the demodulation frequency f _dem . Thus, the design of the demodulator 550 can be facilitated.

FIG. 6 is a block diagram illustrating a demodulator shown in FIG. 5.

Referring to FIG. 6, the demodulator 550 includes a phase detector 610, a clock generator 620, a sampling performer 630, a demodulator 640, a filter 650, and a clock data recovery (CDR) 660. It includes.

The phase detector 610 detects phase information of the input signal based on a sampling result of the input signal to the demodulator 550. Here, the input signal may be a signal from which noise is removed by passing through a band pass filter, and in some cases, may be a signal passed through a mixer. That is, when the transmitter frequency of the transmitter is Nf _dem , the mixer may not be necessary, but if the transmitter frequency is not Nf _dem , the input signal may be a signal passed through the mixer. The input signal is a signal modulated according to a phase shift keying (PSK) and may have a frequency in a range of 57 GHz to 66 GHz.

In addition, the clock generator 620 generates a clock signal synchronized with the input signal using the phase information. Here, the clock signal has a demodulation frequency f _{dem which} is an operating frequency inherent to the demodulator 550. In this case, the clock generator 620 may generate the clock signal that rises or falls with a phase difference corresponding to the modulation method of the input signal.

In addition, the sampling performing unit 630 samples an input signal in response to a clock signal having a demodulation frequency f _dem . That is, the sampling performing unit 630 samples the input signal in response to the clock signal rising or falling in accordance with the demodulation frequency f _dem . In this case, the sampling performing unit 630 may sample the input signal at the time when the rising edge and the falling edge of the clock signal occur.

In addition, the demodulator 640 demodulates the input signal based on the sampling result of the sampling performer 630. That is, the demodulator 640 non-inverts the sampling result generated at the time when the rising edge of the clock signal occurs, and inverts the sampling result generated at the time when the falling edge of the clock signal occurs. Can be demodulated.

Filter 650 also removes noise in the demodulated input signal, and CDR 660 recovers clock and data from the demodulated input signal. In this case, the filter 650 and the CDR 660 may be omitted in some cases.

Detailed operations of the demodulator 550 illustrated in FIGS. 5 and 6 will be described in detail with reference to FIG. 7.

FIG. 7 is a timing diagram illustrating an example of the operation of the demodulator 550 shown in FIG. 5.

Referring to FIG. 7, the original signal is as shown in (a), and the items shown in (a) to (g) of FIG. 4 are shown to be the same in (a) to (g) of FIG. have. Hereinafter, it is assumed that N is 5, and the frequency Nf _dem of the input signal is five times higher than the demodulation frequency of the demodulator 550.

Referring to the modulated signal shown in (c), a signal modulated at a frequency of 5f _dem may be shown as (h). At this time, the demodulator 550 may be sampling the modulated signal at a frequency of 5f _dem using a clock signal having a frequency of f _dem shown in (d). At this time, the sampled level may be shown as (i).

In addition, the demodulator 550 non-inverts the sampling result generated at the time when the rising edge of the clock signal occurs with respect to the sampling levels shown in (i), and the falling edge of the clock signal The demodulated level can be obtained by inverting the sampling result generated at the time of occurrence. That is, the demodulated level can be represented as (j), and thus a demodulated signal can be obtained as shown in (k).

As a result, referring to FIG. 7, the demodulator 550 can demodulate the input signal well using a demodulation frequency f _dem lower than the frequency 5f _{dem of} the input signal. Therefore, according to the present invention, efforts for converting the frequency of the input signal to the intermediate frequency can be saved, and there is no need to increase the demodulation frequency more than necessary.

8 is a flowchart illustrating a signal demodulation method according to an embodiment of the present invention.

Referring to FIG. 8, the signal demodulation method according to an embodiment of the present invention detects phase information of the input signal based on a sampling result of an input signal modulated with a carrier having a first frequency (S810).

In addition, the signal demodulation method according to an embodiment of the present invention generates a clock signal having a demodulation frequency synchronized with the input signal using the phase information (S820).

In addition, the signal demodulation method according to an embodiment of the present invention samples the input signal in response to the generated clock signal (S830).

In addition, the signal demodulation method according to an embodiment of the present invention demodulates the input signal according to the sampling result generated from the step (S830) of sampling the input signal (S840).

1 to 7 may be applied to the signal demodulation method of the present invention as it is, and a detailed description of the signal demodulation method of the present invention will be omitted.

The signal demodulation method and the signal reception method according to the present invention can be implemented in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

1 is a diagram illustrating a typical Costas loop.

2 is a block diagram illustrating a wireless receiver using a low intermediate frequency and using the same demodulation frequency as the intermediate frequency.

3 is a block diagram illustrating a demodulator shown in FIG. 2.

4 is a timing diagram illustrating an example of an operation of the demodulator shown in FIG. 2.

5 is a block diagram illustrating a wireless receiver using a high intermediate frequency and using a demodulation frequency lower than the intermediate frequency.

FIG. 6 is a block diagram illustrating a demodulator shown in FIG. 5.

FIG. 7 is a timing diagram illustrating an example of the operation of the demodulator shown in FIG. 5.

8 is a flowchart illustrating a signal demodulation method according to an embodiment of the present invention.

Claims (14)

A phase detector for detecting phase information of the input signal based on a sampling result of the input signal modulated with a carrier having a first frequency; A clock generator configured to generate a clock signal having a demodulation frequency synchronized with the input signal using the phase information; A sampling performer configured to sample the input signal in response to the generated clock signal; And A demodulator for demodulating the input signal based on a sampling result of the sampling performer; Including, And the first frequency is an integer multiple of the demodulation frequency. The method of claim 1, The sampling performing unit And sampling the input signal at a time when a rising edge and a falling edge of the clock signal occur. The method of claim 1, The clock generator And generating the clock signal that rises or falls with a phase difference corresponding to the modulation method of the input signal. The method of claim 1, The demodulation unit Demodulating the input signal by non-inverting the sampling result generated at the time when the rising edge of the clock signal occurs, and inverting the sampling result generated at the time when the falling edge of the clock signal occurs. Characterized in that the signal demodulation device. The method of claim 1, And the input signal is a signal modulated according to a phase shift keying (PSK). The method of claim 1, And the first frequency is a frequency in a range of 57 GHz to 66 GHz. At least one antenna for receiving a modulated transmission signal; An amplifier for amplifying the power of the received transmission signal; A mixer coupled to the amplifier for converting a frequency of the transmission signal to generate an input signal having a first frequency; And A signal demodulator for demodulating the input signal having the first frequency by using a clock signal having a second frequency Including, And the first frequency is an integer multiple of the second frequency. The method of claim 7, wherein The signal demodulation unit A phase detector detecting phase information of the input signal based on a sampling result of the input signal having the first frequency; A clock generator configured to generate a clock signal having the second frequency synchronized with the input signal by using the phase information; A sampling performer configured to sample the input signal in response to the generated clock signal; And A demodulator for demodulating the input signal according to a sampling result of the sampling performer Receiver comprising a. The method of claim 8, The demodulation unit Demodulating the input signal by non-inverting the sampling result generated at the time when the rising edge of the clock signal occurs, and inverting the sampling result generated at the time when the falling edge of the clock signal occurs. Receiver. Detecting the input signal phase information based on a sampling result of an input signal modulated with a carrier having a first frequency; Generating a clock signal having a demodulation frequency synchronized with the input signal using the phase information; Sampling the input signal in response to the generated clock signal; And Demodulating the input signal in accordance with a sampling result generated from sampling the input signal. Including, And the first frequency is an integer multiple of the demodulation frequency. The method of claim 10, Demodulating the input signal Demodulating the input signal by non-inverting the sampling result generated at the time when the rising edge of the clock signal occurs, and inverting the sampling result generated at the time when the falling edge of the clock signal occurs. A signal demodulation method, characterized in that. The method of claim 10, Sampling the input signal And sampling the input signal at a time when a rising edge and a falling edge of the clock signal occur. Receiving a modulated transmission signal through at least one antenna; Amplifying the power of the received transmission signal using an amplifier; Generating an input signal having a first frequency by converting a frequency of the transmission signal using a mixer connected to the amplifier; And Demodulating an input signal having the first frequency using a clock signal having a second frequency Including, And wherein the first frequency is an integer multiple of the second frequency. The method of claim 13, Demodulating the input signal having the first frequency Detecting phase information of the input signal based on a sampling result of the input signal having the first frequency; Generating a clock signal having the second frequency in synchronization with the input signal using the phase information; Sampling the input signal in response to the generated clock signal; And Demodulating the input signal in accordance with a sampling result generated from sampling the input signal. Signal receiving method comprising a.

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