WO2009089869A1 - Method for transmitting messages in a bus system, bus device and bus system - Google Patents

Method for transmitting messages in a bus system, bus device and bus system Download PDF

Info

Publication number
WO2009089869A1
WO2009089869A1 PCT/EP2008/010072 EP2008010072W WO2009089869A1 WO 2009089869 A1 WO2009089869 A1 WO 2009089869A1 EP 2008010072 W EP2008010072 W EP 2008010072W WO 2009089869 A1 WO2009089869 A1 WO 2009089869A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus
device
transmission signals
time
processing device
Prior art date
Application number
PCT/EP2008/010072
Other languages
German (de)
French (fr)
Inventor
Paul Milbredt
Original Assignee
Audi Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE102008004854.2A priority Critical patent/DE102008004854B4/en
Priority to DE102008004854.2 priority
Application filed by Audi Ag filed Critical Audi Ag
Publication of WO2009089869A1 publication Critical patent/WO2009089869A1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H04L12/46Interconnection of networks
    • H04L12/4604LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H04L12/462LAN interconnection over a bridge based backbone
    • H04L12/4625Single bridge functionality, e.g. connection of two networks over a single bridge
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H04L12/40Bus networks
    • H04L12/407Bus networks with decentralised control
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H04L12/40Bus networks
    • H04L2012/40208Bus networks characterized by the use of a particular bus standard
    • H04L2012/40241Flexray
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H04L12/40Bus networks
    • H04L2012/40267Bus for use in transportation systems
    • H04L2012/40273Bus for use in transportation systems the transportation system being a vehicle

Abstract

It is to be enabled that in a time-controlled communication system, particularly when connecting a plurality of bus devices (10, 12, 14) to one and the same bus, messages emitted by a transmitter (10) can be processed by a processing device (14) before they reach a receiver (12). This is enabled in that the processing device (14) re-emits transmission signals it has received and processed whenever possible in the same time slot in which it received them, specifically with a delay (32).

Description


  AUDI AG P7005

  
Patent application

  
Method for transmitting messages in a bus system, bus device and bus system

  
DESCRIPTION:

  
The invention relates to the field of time-triggered communication systems, namely those in which the time is divided into a plurality of time slots. The individual subscribers of the communication system are assigned to certain of these time slots, so that said subscribers can then deliver in the time slots assigned to them transmit signals. Usually, the time slots are assigned to the individual subscribers in a cyclical sequence. The communication method requires that the individual subscribers, also referred to as "nodes", must synchronize. Known protocols for data transmission in such communication systems are FlexRay, TTP / C and TTCAN.

  
In particular, the invention is concerned with the transmission of messages which are transmitted by a transmitting device and processed in a processing device before they reach a receiving device.

  
If one wants to process signals from another bus subscriber in a bus subscriber, this necessitates a separation of a bus into two branches in the prior art. For example, when using the FlexRay protocol, at least two nodes (bus users) are required for synchronization within a branch. So is lost when disconnecting the bus synchronization. Namely, the bus subscribers from one of the branches receive only signals via the bus subscribers handling these signals and separating the branches from each other. In order not to violate the protocol, for each branch the remaining bus must be simulated, and in such a simulation the time bases drift apart.

   In the prior art, the processing bus device (the processing device) receives the signals from the sending device in a first time slot and retransmits them in the corresponding time slot of the other branch after processing. This second time slot must be a time slot associated with the transmitter. It is usually the next time slot in the sequence of time slots associated with the predetermined time slots defined for the transmitter.

  
Because of the separation of a bus into two branches by editing the communication system must be very complex overall. Due to the transmission of the signals in the respective next time slot belonging to the transmitter, the messages from the transmitter arrive with considerable delay only at the receiving device, which in the worst case is as large as the cycle time of the time slots.

  
It is an object of the invention to eliminate these disadvantages of the prior art.

  
The object is achieved by a method having the features according to claim 1 and a method enabling this bus device having the features according to claim 4. By the inventive method or when using the inventive bus device and a bus system with the features according to claim 6 is possible.

  
In the method according to the invention, the processing device thus at least partially (in particular if possible according to predetermined criteria) transmits transmission signals received and processed by it again in the same time slot (of course with delay) in which it received it.

  
The invention consists in using a buffer time usually defined in the timeslot. The length of a time slot is usually greater than the length of a message (a so-called frame). The transmission of the message is started only after a buffer time has elapsed, and a buffer time remains after the transmission of the frame in the time slot has ended. The buffer times are defined because the individual devices are not perfectly synchronized with each other. Usually, however, the buffer times are very generous. Therefore, it makes sense if the processing device (in advance, ie before receiving the transmission signals) detects how exactly a related clock (timer) with a clock (a timer) of the transmitter is synchronized.

   In addition, it should (in advance in particular) estimate or calculate how long the processing of the transmission signals takes. Based on the first information, the processing device can determine how much of the buffer time is actually required due to the imperfect synchronization of the two clocks (minimum remainder buffer time). Based on the second information, the time delay with which the processing device can send out the processed transmission signals again can be estimated. It can thus be estimated how much the buffer time is shortened. Thus it can be deduced whether the minimum remainder buffer time remains from a buffer time in the time slot.

   For this purpose, a residual buffer time of greater than a certain microsecond number can be specified, but the minimum residual buffer time can also be equal to 0 microseconds if perfect synchronization has been assumed. If the minimum remaining buffer time remains, then the transmitted transmission signals are transmitted in the same time slot in which they were received.

  
Due to the time delay of sending the processed transmission signals through the processing unit, errors in the synchronization could occur. This would be the case in particular if the transmission signals comprise a synchronization signal which is transmitted unchanged with time delay. Therefore, the processing apparatus should disable (cancel) a sync signal included in the transmit signal, for example, reset (to 0) a sync bit set to (1).

  
The bus device according to the invention is designed to retransmit processed transmission signals in the same time slot with delay in which it receives them. It is preferably designed to determine a remaining buffer time remaining from a buffer time after receiving and processing until retransmission of the transmission signals and to retransmit the processed transmission signals in the same time slot with delay, in which it has received them, if the residual buffer time has a minimum value exceeds. Should the residual buffer time not be sufficiently large, the prior art method may be followed, meaning that the transmission signals are forwarded in the next time slot allocated to the transmitter from which they originate.

  
The invention includes the first-time provision of a bus system, which may be configured in particular as a FlexRay bus system, wherein a plurality of bus devices belongs to the bus system, a transmitting device transmits the transmission signals, which are processed by a processing device, before they are sent to a receiving device, In contrast to the prior art, all bus devices are connected to the same one (FlexRay) bus and therefore can also be synchronized.

  
It thus eliminates the effort required by the division of the bus into two branches in the prior art. Due to the synchronizability of all bus devices a good functioning of the communication in the bus system, in particular without time delay is guaranteed.

  
A bus system according to claim 6 is in particular provided when the processing device is a bus device of the inventive type.

  
Hereinafter, a preferred embodiment of the invention will be described with reference to the drawings, wherein

  
Fig. 1 illustrates a communication system according to the prior art,

  
FIG. 2 illustrates a communication system according to the invention, which is designed as a coherent bus system, FIG.

  
Fig. 3A shows the time course of the transmission of signals in a time slot by a transmitting device and

  
FIG. 3B illustrates the time profile of the transmission of signals by a processing apparatus which has received and processed the signals illustrated in FIG. 3A using the method according to the invention.

  
A transmitter 10 sends in a timed communication system transmission signals in predetermined, namely exactly the transmitter 10 associated, time slots. Before the transmission signals arrive at a residual bus 12, in particular at a receiving device, they are to be processed by a processing device 14. The processing unit 14 typically operates to receive and process the transmit signals in the one time slot and then retransmit them in the next time slot associated with the transmitter 10. This results in a delay in the transmission of the transmission signals, which corresponds to the time interval between two time slots that belong to the same device, that is defined by the so-called transmission frequency.

   The prior art approach requires that the communications system be divided into two parts by the processing device 14, namely a first FlexRay cluster 16 and a second FlexRay cluster 18. The two FlexRay clusters are each branches of a FlexRay bus. The two FlexRay clusters no longer have a common time base. Rather, the first FlexRay cluster 16 has a first time base and the second FlexRay cluster 18 has a second time base, transmitter 10 on the one hand and residual bus 12 with the receiver on the other hand are no longer synchronized.

  
The method according to the invention now makes it possible to provide a bus system 20 in which the transmitting device 10, processing device 14 and residual bus 12 are connected to the receiving device on a single FlexRay bus, so there is only one more FlexRay cluster, whereby all bus users (bus devices) one common timebase received.

  
The method according to the invention, which is used by the processing device 14, will now be explained on the basis of a temporal signal curve. FIG. 3A shows the signal curve in a time slot designated as a whole by 22. The time slot 22 is divided into a first section 24, a second section 26 and a third section 28. The sections 24 and 28 are buffers. In section 26, the actual message or message is sent, ie a so-called frame. A frame has a predetermined length, and this is shorter than a time slot. For example, the duration of a frame is 65 [mu] s. Buffer 1 (section 24) has a duration of 5 [mu] s, and buffer 2 (section 28) has a duration of 7 [mu] s. Overall, the time slot 22 thus has a duration of 77 [mu] s with a duration of a frame of 65 [mu] s.

   By way of example, in FIG. 3A, a signal 30 is shown in the frame

  
26 is transmitted. The processing device 14 now more or less receives the ideal signal shown in FIG. 3A: If the transmitting device 10 transmits the frame 26 in the time slot 22 exactly as shown in FIG. 3A, the processing device 14 also receives the signals accordingly when the clock of the Processing unit 14 is perfectly synchronized with that of the transmitter 10. The processing unit 14 can now determine, in the context of a constant data flow, how well its clock is synchronized with that of the transmitting device. The error in the synchronization causes the minimum remainder buffer time, which may remain in the time slot 22 after completion of the transmission of the frame 26. The processing device 14 needs a certain time for receiving and processing until the re-transmission can be started. This also takes into account the processing device 14.

   The processing device 14 may detect whether a minimum remainder buffer time has been defined by the buffer 2 (section 28) defined in view of the synchronization error between the clock of the processing device 14 and the clock of the transmitting device 10, in view of the time required by the receiving, processing and re-broadcasting remains. If this is the case, the processing device 14 sends, for example, in a time slot 22, the frame 26 'as shown in Fig. 3B, namely with a predetermined delay 32. The duration of the section 28 is shortened by the same delay 32, so that a shorter Section 28 'results. The processing device 14 has determined here that the duration of the section 28 'is sufficiently large to take account of the synchronization error.

  
The invention makes use of the use of the buffers, in particular that there is the buffer 2, ie a buffer which is provided after termination of a frame 26. Because of the presence of this buffer 2, it is possible to send out the frame after processing as frame 26 'with delay 32 (unless the delay 32 is too large).

  
It may, when the processing unit 14 only processes the signal 30, already started with the retransmission with the delay 32 before the frame 26 has been completely received, including before the signal 30 has been received. The reception time, which is assumed when calculating the delay 32, is merely the time required for the pure electronic process of receiving in the processing device 14 and does not include a waiting time from the start of the frame 26 to the signal to be processed 30.

Claims

1. A method for transmitting messages from a transmitting device (10) via a processing device (14), in which the messages are processed, to a receiving device (12), wherein in a communication system a sequence of time slots (22) is defined and transmission signals ( 26, 26 ') from the transmitter (10) in predetermined time slots (22) are transmitted from this sequence, characterized in that the processing device (14) received and processed by him transmitting signals at least partially in the same
Timeslot (22) again, in which it has received them.
2. The method according to claim 1, characterized in that the processing device (14) detects exactly how a belonging to him clock with a clock of the transmitting device (10) is synchronized, and that it estimates or calculates how long the receiving and processing until for redirecting the transmission signals, and that it derives from these two pieces of information whether a minimum remaining buffer time (28 ') remains in the time slot (22) from a buffer time (28) and in this case transmits the transmission signals it has processed in the same time slot, in which she received it.
3. The method of claim 1 or 2, wherein the processing device (14) suppresses a synchronization signal contained in the transmission signals.
4. Bus device (14) which is designed to receive and process transmission signals from another bus device (10) when both bus devices (10, 14) are connected to a bus in which a sequence of time slots is defined and the transmission signals from the other bus device (10) are transmitted in predetermined time slots, characterized in that the bus device (14) is adapted to retransmit processed transmission signals in the same time slot (22) with delay (32) in which it receives them.
5. Bus device (14) according to claim 4, characterized in that it is designed to determine a remaining of a buffer time after receiving and processing and retransmission of transmission signals remaining buffer time (28 ') and the processed transmission signals only in the same time slot ( 22) with delay, in which it has received it, if the residual buffer time (28 ') exceeds a minimum value.
6. Bus system (20), in particular FlexRay bus system with a plurality of bus devices (10, 12, 14), wherein a processing device (14) of the bus devices for processing by a transmitting device (10) of the bus devices emitted transmission signals is designed before the edited transmission signals to a receiving device (12) of the bus devices are forwarded, characterized in that all the bus devices (10, 12, 14) connected to the same bus and synchronized.
7. bus system (20) according to claim 6, characterized in that the processing device (14) is a bus device according to claim 4 or 5.
PCT/EP2008/010072 2008-01-17 2008-11-27 Method for transmitting messages in a bus system, bus device and bus system WO2009089869A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE102008004854.2A DE102008004854B4 (en) 2008-01-17 2008-01-17 Method for transmitting messages in a bus system, bus device and bus system
DE102008004854.2 2008-01-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AT94002008A AT512449B1 (en) 2008-01-17 2008-11-27 Method for transmitting messages in a bus system, bus device and bus system

Publications (1)

Publication Number Publication Date
WO2009089869A1 true WO2009089869A1 (en) 2009-07-23

Family

ID=40756553

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/010072 WO2009089869A1 (en) 2008-01-17 2008-11-27 Method for transmitting messages in a bus system, bus device and bus system

Country Status (3)

Country Link
AT (1) AT512449B1 (en)
DE (1) DE102008004854B4 (en)
WO (1) WO2009089869A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004111859A2 (en) * 2003-06-18 2004-12-23 Robert Bosch Gmbh Method, device and system for the exchange of data via a bus system
GB2404121A (en) * 2003-07-18 2005-01-19 Motorola Inc Inter-network synchronisation
DE102005018837A1 (en) * 2005-04-22 2006-10-26 Robert Bosch Gmbh Method and device for synchronizing two bus systems and arrangement of two bus systems
WO2008029318A2 (en) * 2006-09-06 2008-03-13 Nxp B.V. Cluster coupler in a time triggered network
WO2008053039A1 (en) * 2006-11-03 2008-05-08 Robert Bosch Gmbh Device and method for manipulating communication messages

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE524201C2 (en) * 2002-12-17 2004-07-06 Lars-Berno Fredriksson Device for distributed control and monitoring systems
DE102004063213B4 (en) * 2004-12-24 2006-11-23 Pilz Gmbh & Co. Kg Control system with a plurality of spatially distributed stations and method for transmitting data in such a control system
US7406555B2 (en) * 2005-04-29 2008-07-29 The Boeing Company Systems and methods for multiple input instrumentation buses
DE102005060085B9 (en) * 2005-12-15 2010-09-30 Beckhoff Automation Gmbh Method, communication network and control unit for the cyclic transmission of data

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004111859A2 (en) * 2003-06-18 2004-12-23 Robert Bosch Gmbh Method, device and system for the exchange of data via a bus system
GB2404121A (en) * 2003-07-18 2005-01-19 Motorola Inc Inter-network synchronisation
DE102005018837A1 (en) * 2005-04-22 2006-10-26 Robert Bosch Gmbh Method and device for synchronizing two bus systems and arrangement of two bus systems
WO2008029318A2 (en) * 2006-09-06 2008-03-13 Nxp B.V. Cluster coupler in a time triggered network
WO2008053039A1 (en) * 2006-11-03 2008-05-08 Robert Bosch Gmbh Device and method for manipulating communication messages

Also Published As

Publication number Publication date
DE102008004854A1 (en) 2009-07-23
AT512449B1 (en) 2013-09-15
DE102008004854B4 (en) 2015-06-18

Similar Documents

Publication Publication Date Title
DE69930806T2 (en) Improvements in time synchronization in distributed systems
CN100559741C (en) Clock synchronizing method over fault-tolerant Ethernet
US20040010729A1 (en) Multi-media jitter removal in an asynchronous digital home network
US8364875B2 (en) Time and event based message transmission
Gergeleit et al. Implementing a distributed high-resolution real-time clock using the CAN-bus
EP2039568B1 (en) Method and device for data exchange between at least two subscribers connected by a bus system
EP1512254B1 (en) Communication method and system for transmitting timed and event-driven ethernet messages
JP4856382B2 (en) Method and system for network terminal clock synchronization
US5621895A (en) Frame-structured bus system for transmitting both synchronous and asynchronous data over a star-coupled local operation network
US4495617A (en) Signal generation and synchronizing circuit for a decentralized ring network
CA1172719A (en) Distributed-structure message switching system on random-access channel for message dialogue among processing units
US7573914B2 (en) Systems and methods for synchronizing time across networks
US8126333B2 (en) Optical transmission system and synchronization method using time reference pulse
CN102027699B (en) Data transfer method and system for loudspeakers in a digital sound reproduction system
US20100054244A1 (en) Time sychronization method and relay apparatus
US20090100189A1 (en) Data network with a time synchronization system
TW498649B (en) Method of and apparatus for communicating isochronous data
US6928126B2 (en) Reception interface unit in transmission system
US7860125B2 (en) Flexible time stamping
US20060251046A1 (en) Master-slave synchronization communication method
US9893827B2 (en) High speed embedded protocol for distributed control system
CN100359956C (en) Method for implementing synchronization and distance finding in wireless communication system and implementing apparatus thereof
US20030142696A1 (en) Method for ensuring access to a transmission medium
JP2004505497A (en) Multimedia Jitter Removal in Asynchronous Digital Home Network
EP0835566B1 (en) Synchronisation in digital communications networks

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08870738

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase in:

Ref document number: 94002009

Country of ref document: AT

Kind code of ref document: A

122 Ep: pct app. not ent. europ. phase

Ref document number: 08870738

Country of ref document: EP

Kind code of ref document: A1