WO2009086692A1 - Procédé de traitement pour système intégré utilisant une mémoire flash non-et pour mémorisation et démarrage - Google Patents

Procédé de traitement pour système intégré utilisant une mémoire flash non-et pour mémorisation et démarrage Download PDF

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Publication number
WO2009086692A1
WO2009086692A1 PCT/CN2008/000038 CN2008000038W WO2009086692A1 WO 2009086692 A1 WO2009086692 A1 WO 2009086692A1 CN 2008000038 W CN2008000038 W CN 2008000038W WO 2009086692 A1 WO2009086692 A1 WO 2009086692A1
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WO
WIPO (PCT)
Prior art keywords
flash memory
nand flash
nand
operating system
controller
Prior art date
Application number
PCT/CN2008/000038
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English (en)
Chinese (zh)
Inventor
Chingyi Lin
Original Assignee
Fortune Spring Technology (Shenzhen) Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fortune Spring Technology (Shenzhen) Corporation filed Critical Fortune Spring Technology (Shenzhen) Corporation
Priority to PCT/CN2008/000038 priority Critical patent/WO2009086692A1/fr
Publication of WO2009086692A1 publication Critical patent/WO2009086692A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping

Definitions

  • the present invention relates to the field of flash memory storage, and is particularly suitable for an embedded operating system that utilizes flash memory as a code storage space and is booted by the flash memory boot system. (Embedded System) field.
  • an embedded operating system that utilizes flash memory as a code storage space and is booted by the flash memory boot system. (Embedded System) field.
  • flash memory can be divided into NOR Flash memory and NAND Flash memory.
  • the NOR flash memory is generally called Code Flash. Since NOR Flash is a non-volatile memory belonging to linear addressing, the microprocessor can directly execute the program in the flash memory. It is not necessary to first read the program into the system memory, and it is quite easy to use. Therefore, most of the embedded operating systems on the market currently use NOR Flash as the medium for booting the boot system. However, in contrast, NOR flash memory is less dense than NAND flash memory and expensive, so it is not economical to use NOR to store large amounts of user data. NAND flash memory is generally called Data Flash, which is characterized by high unit density, high storage density and economical profitability, and NAND read and write speed is also quite fast.
  • NAND flash memory Since the unit size of the NAND flash memory is much smaller than that of the NOR Flash, and the production process is simpler, the target is also relatively low. In terms of capacity, the capacity of NAND Flash currently on the market has reached a high capacity of 1 to 4 Gbytes, and will continue to increase in the future. Among all portable products, NAND flash memory has the largest market share, which shows that it has considerable competitiveness. However, NAND flash memory is similar to a mechanical hard disk and belongs to Block Addressing. It is necessary to read the program on the NAND flash memory to the random access memory before it can be executed by the microprocessor. The processing of this part is not very easy, so the storage medium of the embedded system on the market (especially the storage medium of the program) is still dominated by NOR flash memory. Considering the new demand in the market, we hope to use NAND flash memory. Replaces NOR flash memory in embedded systems.
  • the object of the present invention is to enable NAND flash memory to provide both NOR and NAND functions, and to implement analog hard disk drive functions using built-in drivers.
  • the system consists of a Micro Controller. SRAM, Dynamic Random Access Memory (DRAM), NAND Flash Memory (NAND Flash), and NAND Flash Memory Controller (NAND Flash Controller) IC) and other components.
  • DRAM Dynamic Random Access Memory
  • NAND Flash NAND Flash Memory
  • NAND Flash Controller NAND Flash Controller
  • the invention replaces NOR flash memory with NAND flash memory. Its architecture is shown in Figure 1. It can utilize NAND flash memory and specifically boot and data storage functions. The system uses two phases of reset to complete the start-up action of a single unit.
  • the reset signal (170) of the first stage is generated by the external (user).
  • a second stage reset signal is generated (180). ), the CPU is notified to execute the program in the SRAM.
  • the present invention uses NAND flash memory to replace NOR flash memory and provides analog hard disk function for increasing the simulation in terms of unit cost and data storage capacity.
  • the life of the hard disk is added with the functions of the Wear leveling mechanism and the Error Correction Code. Therefore, the invention has the advantages of low cost, high reliability and high read/write efficiency, which can effectively improve the efficiency and reliability of the system and reduce the system cost.
  • the invention can be applied to any system that needs to have a data storage function, reducing the cost of the system and providing a higher storage capacity. And you can use a variety of different NAND flash memory. When a manufacturer's NAND flash memory is out of stock or defective, you can quickly replace it with another NAND flash memory, and the production management and quality are almost no. There will be any changes.
  • This architecture can also be used with a variety of different microprocessors. Simply assign the address 0 of the SRAM to the power-on address of the microprocessor, and you can select any microprocessor.
  • the NAND flash memory controller (110), DMA controller (130), and SRAM (150) can be integrated into one IC, reducing cost without affecting system scalability, as shown in Figure 2.
  • Figure 1 Basic diagram of the flash memory.
  • FIG. 1 Single IC schematic.
  • FIG. 4 Internal data configuration for NAND flash memory.
  • FIG. 5 The process of reading the boot code.
  • Microcontroller The processing unit of the system, the instructions of the execution system and the access of peripheral devices.
  • NAND flash memory controller The command to access the flash memory and the data to enable the DMA to transfer the flash memory to the SRAM (150) or DRAM (140).
  • NAND flash memory i memory store data and start program code.
  • DMA Controller Direct memory access controller, control memory and move data in NAND flash memory.
  • DRAM Dynamic Random Access Memory, because the capacity of static random access memory is usually small, so dynamic random access memory is required, and a large amount of system information and data to be written to the flash memory are stored here.
  • RAM Static random access memory.
  • External reset signal When the system restarts, this signal will be triggered to inform the NAND Flash Controller to move the program code on the NAND Flash to the SRAM. .
  • System Address Bus Microprocessor internal address bus.
  • System Data Bus Microprocessor internal data bus. In the case of an 8-bit microprocessor, there will be 8 data buses.
  • Flash Memory Control Bus Controls the flash memory signal, such as CLE (Command Latch)
  • ALE Address Latch Enable
  • R/B Ready/Busy
  • Flash Memory Data Bus The DMA controller reads or writes data to this data bus.
  • NAND flash memory is a memory.
  • the invention utilizes a microprocessor (Micro Controller), a static random access memory (SRAM), a dynamic random access memory (DRAM), a NAND flash memory controller (NAND Flash Controller), and NAND.
  • a microprocessor Micro Controller
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • NAND Flash Controller NAND flash memory controller
  • Components such as NAND Flash build the entire device.
  • the process of reading data is as shown in Fig. 5.
  • the information of all the bad blocks of the NAND Flash and the starting block and length of the booting program are obtained, and then the starting blocks are read one by one.
  • the block read is a bad block, the block is skipped.
  • the boot code of the block is read into the SRAM. Repeat the above read operation until the length of the read block is equal to the length of the program block.
  • the storage method of NAND Flash is a block (BS) as the main storage unit
  • the block will inevitably be encountered for a long time.
  • Techniques such as Error Correction Code (ECC) and Electric Leveling (Wear Leveling).
  • ECC Error Correction Code
  • W Leveling Electric Leveling
  • the Wear leveling technology data can be evenly distributed in each block of NAND Flash, and is not confined to certain blocks, resulting in regional damage. Therefore, the purpose of adding the above two technologies is mainly to extend the service life and enhance the NAND flash memory. Reliability. Industrial applicability
  • the present invention uses NAND flash memory to replace NOR flash memory and provides analog hard disk function for the purpose of increasing the simulation in terms of unit cost and data storage capacity.
  • the life of the hard disk adding the Electric leveling mechanism and the Error Correction Code. Therefore, the invention has the advantages of low cost, high reliability and high read/write efficiency, which can effectively improve the efficiency and reliability of the system and reduce the system cost.
  • the present invention can be applied to any system that needs to have a data storage function, reducing the cost of the system and providing a higher storage capacity.
  • NAND flash memory when a manufacturer's NAND flash memory is out of stock or defective, you can quickly replace it with another NAND flash memory, and the production management and quality are almost no There will be any changes.
  • This architecture can also be used with a variety of different processors: as long as the address 0 of the SRAM is mapped to the power-on address of the microprocessor, any processor can be selected.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

L'invention concerne un procédé utilisant une mémoire flash NON-ET pour mémoriser et démarrer des programmes. Ce procédé est le suivant : le système comprend un microprocesseur, une mémoire vive statique, une mémoire vive dynamique, une mémoire flash NON-ET et un contrôleur de mémoire flash NON-ET. Par une transmission en deux phases du signal de remise à zéro, le système confère simultanément à la mémoire flash NON-ET les fonctions NON-OU et NON-ET. Lors de l'amorçage d'un système d'exploitation intégré pour démarrer, la mémoire flash NON-ET peut également avoir la fonction de mémoire flash interne. Ce procédé permet d'accroître considérablement l'intégrité du système intégré et de faire des économies en termes de coût pour le système, et a ainsi une application d'avant-plan élargie.
PCT/CN2008/000038 2008-01-07 2008-01-07 Procédé de traitement pour système intégré utilisant une mémoire flash non-et pour mémorisation et démarrage WO2009086692A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2008/000038 WO2009086692A1 (fr) 2008-01-07 2008-01-07 Procédé de traitement pour système intégré utilisant une mémoire flash non-et pour mémorisation et démarrage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2008/000038 WO2009086692A1 (fr) 2008-01-07 2008-01-07 Procédé de traitement pour système intégré utilisant une mémoire flash non-et pour mémorisation et démarrage

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WO2009086692A1 true WO2009086692A1 (fr) 2009-07-16

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102541579A (zh) * 2010-12-17 2012-07-04 沈阳新邮通信设备有限公司 嵌入式系统应用程序动态加载的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956743A (en) * 1997-08-25 1999-09-21 Bit Microsystems, Inc. Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations
CN1470991A (zh) * 2002-07-25 2004-01-28 联想(北京)有限公司 一种采用与非闪存作系统存储器的方法及装置
CN1521634A (zh) * 2003-02-11 2004-08-18 连邦科技股份有限公司 虚拟nor型闪存
CN1996496A (zh) * 2006-08-11 2007-07-11 福昭科技（深圳）有限公司 单一ecc电路并行处理多组数据的方法
CN101105752A (zh) * 2006-10-26 2008-01-16 福昭科技（深圳）有限公司 嵌入式系统利用nand闪存记忆体储存及启动的处理方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956743A (en) * 1997-08-25 1999-09-21 Bit Microsystems, Inc. Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations
CN1470991A (zh) * 2002-07-25 2004-01-28 联想(北京)有限公司 一种采用与非闪存作系统存储器的方法及装置
CN1521634A (zh) * 2003-02-11 2004-08-18 连邦科技股份有限公司 虚拟nor型闪存
CN1996496A (zh) * 2006-08-11 2007-07-11 福昭科技（深圳）有限公司 单一ecc电路并行处理多组数据的方法
CN101105752A (zh) * 2006-10-26 2008-01-16 福昭科技（深圳）有限公司 嵌入式系统利用nand闪存记忆体储存及启动的处理方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102541579A (zh) * 2010-12-17 2012-07-04 沈阳新邮通信设备有限公司 嵌入式系统应用程序动态加载的方法

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