WO2009083498A1

WO2009083498A1 - A phase locked loop

Info

Publication number: WO2009083498A1
Application number: PCT/EP2008/068032
Authority: WO
Inventors: Niko Juhani Mikkola; Petri Antero HEILÖ; Paavo Sakari VÄÄNÄNEN; Petri Juhani Kotilainen; Tomi-Pekka Takalo
Original assignee: Nokia Corporation
Priority date: 2007-12-28
Filing date: 2008-12-19
Publication date: 2009-07-09
Also published as: GB0725319D0

Abstract

A phase locked loop (PLL) comprising an oscillator (107) configured to generate an adjustable frequency signal; and a loop filter (203) including am low drop out circuit comprising at least one capacitor (LDO) configured to be connected to the oscillator The low drop out circuit further comprises an operational amplifier (301) configured to output a switching signal, a pass transistor (303) configured to receivee the switching signal to control a received power supply to be output, and a filter (309) including said capacitor (C LDO) and configured to provide aFeedback signal to the operational amplifier. Al lows to reduce the loop filter size for ICimplementation. The PLL may be used in a base sdtation or user equipment.

Description

A PHASE LOCKED LOOP

Field of the Invention

The present invention is related to a phase locked loop, and more particularly but not exclusively a phase locked loop incorporating a low drop out circuit to improve an oscillator.

Background

One of the key building blocks found in most electronic equipment is the frequency synthesizer. The frequency synthesizer outputs an oscillator output which may be used for signal generation or signal mixing. Signal mixing may be used for example in a receiver to down convert a received radio frequency signal to a baseband frequency signal in order that the modulating/information signal, in the received signal may be separated from the carrier signal. Similarly signal mixing may be used in a transmitter to up convert the information/modulating signal to the carrier frequency.

In a transmitter the modulating signal is formed in the base band frequency (i.e. around zero frequency). For example a phase of certain selected pulse form is modulated depending on the information that is to be transmitted. In a communication system using a radio channel to transmit the information, the base band signal is then up-converted to a radio frequency of the radio channel by mixing it with a local oscillator (LO) signal. In a direct conversion transmitter the mixing is carried out in one stage and the base band signal is therefore multiplied with a local oscillator signal which has a frequency determined by the radio channel used in that particular communication system. In a frequency domain representation this can be described as the base band signal being transferred from a zero frequency to the local oscillator frequency which in the case of the direct conversion transmitter is in the middle of the transmitted channel. !n a receiver the local oscillator is used to convert the received signal down in frequency from the received signal radio frequency to the base band (zero frequency) or intermediate frequency. In case of a direct conversion receiver the received signal is mixed to the zero frequency in a single stage. In this way the carrier component (i.e. the frequency component in the LO frequency band) of the received signal is removed and the synchronization to the modulated base band signal is possible

Frequency synthesizers have traditionally been created using crystal oscillators, phase locked loops (PLL) using voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO).

Phase locked loops (PLL) which use voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO) are configured to be controllable and tuneable. An example of a DCO frequency synthesizer is Golten "Analog-Input Digital Phase Locked Loops for Precise Frequency and Phase Modulation", IEEE transactions on Circuits and Systems - II; Analog and Digital Signal Processing, Volume 42, No 10, October 1995.

The control of these VCO and DCO components may be configured with a respective loop filter and digital filter so to reject high frequency fluctuations in the loop which may lead to loop instability. The loop filters in analogue systems are difficult to implement on an integrated circuit (IC) as they require significant IC area for capacitor layout. In digital systems the required IC area is mainly defined by the number of stages of a digital filter. The Infinite impulse response (MR) filter typically used in a Digital Phase Locked Loop (DPLL) to filter out the quantization noise of a Time to Digital Converter (TDC).

Furthermore the digital filter implementation requires further control circuitry to be implemented in order to maintain loop signal consistency caused in part by the delay chains of the digital filter. Summary of the Invention

It is an object of the present invention to provide a more efficient filter implementation for controlling frequency synthesizers and overcomes the disadvantages of the prior art, or at least provides a useful alternative.

According to a first aspect of the present invention there is provided a phase locked loop comprising an oscillator configured to generate an adjustable frequency signal; a low drop out circuit comprising at least one capacitor configured to be connected to the oscillator.

According to a second aspect of the present invention there is provided the method for operating a phase locked loop comprising generating at an adjustable oscillator an adjustable frequency signal; connecting a low drop out circuit comprising at least one capacitor to the oscillator.

According to a third aspect of the present invention there is provided a computer program product configured to perform a method for operating a phase locked loop comprising generating at an adjustable oscillator an adjustable frequency signal; connecting a low drop out circuit comprising at least one capacitor to the oscillator.

According to a fourth aspect of the present invention there is provided a phase locked loop comprising oscillator means configured to generate an adjustable frequency signal; signal processing means for generating a low drop out circuit comprising at least one capacitor configured to be connected to the oscillator.

The phase-locked loop as described above may be incorporated into a mixer.

The phase-locked ioop as described above may be incorporated into a transmitter. The phase-locked loop as described above may be incorporated into a receiver.

The phase-locked loop as described above may be incorporated into a user equipment.

The phase-locked loop as described above may be incorporated into a base station.

Brief Description of the Drawings

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

Figure 1 shows a schematic diagram of an electronic device capable of implementing embodiments of the invention;

Figure 2 shows a schematic diagram of a conventional phase locked loop voltage controlled oscillator frequency synthesizer;

Figure 3 shows a schematic diagram of a phase locked loop voltage controlled oscillator frequency synthesizer incorporating an embodiment of the invention;

Figure 4 shows a schematic diagram of the embodiment of the invention in further detail;

Figure 5 shows a schematic diagram of a P-MOS transistor as shown in figure 4; and

Figure 6 shows a schematic diagram of an embodiment of the invention as implemented within a digitally controlled oscillator phase locked loop.

Detailed Description of Preferred Embodiments

Figure 1 shows a schematic partially sectioned view of a possible electronic device capable of implementing embodiments of the invention. The electronic device may be a user equipment as shown in Figure 1 used for various tasks such as making and receiving phone calls, for receiving and sending data to and from a data network and for receiving and transmitting the data in the form of multimedia content. Although an electronic device is shown in the form of user equipment and specifically the implementation of the oscillator for communication purposes embodiments of the invention may be implemented in any electronic device requiring a stable but tuneable osciilator.

An appropriate electronic device may be any device capable of sending or receiving radio signals. Non-limiting examples include mobile stations (MS), user equipment (UE), portable computer equipment provided with a wireless interface card or other wireless interface facility, personal data assistants (PDA) provided with wireless communication capabilities, or any combinations of these or the like.

The electronic device may communicate via an appropriate radio interface arrangement of the mobile device. The interface arrangement may be provided by means of a radio frequency and associated antenna arrangement 7. The antenna arrangement may be arranged internally or externally to the electronic device. The radio part may comprise at least one mixer configured to down-convert or up-convert signals to and from the mobile station. The mixer device may comprise a tuneable frequency synthesiser according to the embodiments of the invention. The term frequency synthesiser may also be known as a frequency oscillator. The frequency synthesiser/frequency oscillator may be capable of supplying an oscillation signal of various predetermined or defined frequencies.

The electronic device is typically provided with at least one data processor 3 and at least one memory 4 for storing data and instructions used by the data processor 3. The data processor 3 and memory 4 may be provided on an appropriate circuit board and/or in chip sets 6.

The user may controi the operation of the electronic device by means of a suitable user interface such as a keypad 2, voice command, touch-sensitive screen or pad, or a combination thereof or the like. A display 5, a speaker and a microphone are also typically provided. Furthermore, an electronic device may comprise appropriate connectors (either wired or wireless) to other electronic devices and/or for connecting external accessories, for example hands-free equipment, thereto.

The remainder of the parts of the electronic device are known generally and do not assist in the understanding of the invention and will not be described in further detail hereafter.

Figure 2 shows a schematic view of a conventional frequency synthesiser as may be implemented within the radio part 7 of Figure 1.

The frequency synthesiser 101 may be considered to comprise a series of interconnected functional blocks.

The loop filter 105 receives a detected phase difference signal from a phase detector 103 and outputs a filtered phase difference to the voltage controlled oscillator 107. The filter 105 is typically configured to fitter the input signal so to prevent the loop from being unstable and to output a signal, which is during normal operation of the synthesizer, to overcome any fluctuations of the VCO caused by environmental conditions such as temperature and output loading.

The loop filter 105 shown in figure 2, shows a analogue component filter bank of capacitors and resistors configured to produce a low pass filter. The first capacitor C1 121 has one terminal connected to the loop filter 105 input and the second terminal connected to ground (or earth).

The first resistor R1 123 and second capacitor 125 are connected in series. A first terminal of the first resistor R1 123 is connected to the loop filter input. A second terminal of the first resistor R1 123 is connected to a first terminal of the second capacitor C2 125. A second terminal of the second capacitor C2 125 is connected to ground.

A first terminal of a second resistor R2 127 is connected to the loop fiiter input. A second terminal the second resistor R2 127 is connected to a first terminal of a third capacitor C3 129 and a first terminal of a third resistor R3 131. A second terminal of the third capacitor C3 129 is connected to ground. A second terminal of the third resistor R3 131 is connected to a first terminal of a fourth capacitor C4 133 and to the loop filter 105 output. A second terminal of the fourth capacitor C4 133 is connected to ground.

The resistor/capacitor network shown in figure 2 produces a clearly defined low pass filter with a low frequency gain defined largely by the second resistor 127 R2 and the fourth resistor 131 R4 and a high frequency gain defined by the first resistor 123 R1.

The loop filter may be considered to be a transimpedance network. The loop filter converts output current from the charge pump to a voltage signal. The loop filter as presented in figure 2 is a fourth order low pass filter. The first pole of this example of a loop filter is at the origin. The values of the capacitors C1 , and C2 and the resistor R1 define the second pole of the loop filter. The value of the resistor R2 and the capacitor C3 define the third pole and the resistor value R3 and capacitor value C4 set the fourth pole. Furthermore, R1 and C2 form one zero to the transfer function of the loop filter.

The voltage controlled oscillator (VCO) 107 outputs a VCO output which is proportional to the signal received from the output of the loop filter 105. The VCO outputs a frequency output signal which is proportional to the voltage input to the VCO. The output of the VCO 107 is passed to the frequency divider 109.

The frequency divider 109 receives the output of the VCO 107 and is configured to output a frequency divided output. Typical frequency dividers may be counters configured to output a pulse on the counter reaching a predetermined number count.

The frequency divider 109 shown in figure 2 has a sigma-delta modulator 111 providing a further input. The sigma-deita modulator 11 1 may modulate the frequency divider so that it is configured to output an output which is on average not a whole number divisor ratio.

The output of the frequency divider 109 is connected to a phase detector 103 input. A further input to the phase detector 103 is provided by the reference frequency input, which typically is a stable and accurate oscillation input such as a crystal oscillator.

As has been discussed the loop filter requires a significant amount of IC area to implement. In particular the implementation of capacitors on the 1C requires significantly large amounts of 1C space.

With respect to figure 3, a phase locked loop incorporating an embodiment of the invention is shown which may use less IC area.

The PLL 201 shown in figure 3, is similar to the PLL 101 shown in figure 2. Where similar or the same components are shown the same reference numbers as shown in figure 2 are used.

As per figure 2 the loop has a phase detector 103 which compares the phase between the reference frequency input F_ref and the output of the frequency divider. The phase detector 103 output is connected to the input of the embodiment loop filter 203. The output of the embodiment loop filter 203 is connected to the voltage controlled oscillator 107. The output frequency of the VCO 107, which is dependent on the signal input to the VCO 107, is output to the frequency divider 109. The frequency divider 109 is furthermore connected to the input of the phase detector 103. The frequency divider 109 may furthermore have a delta-sigma modulator 1 1 1 input to enable a non- whole number frequency division.

The difference between the PLL 201 and the PLL 101 may be shown in the difference between the loop filter 105 and the embodiment loop filter 203. The loop filter 203 shown in figure 3, shows a analogue component filter bank of capacitors and resistors and a low drop out (LDO) 205 configured to produce an advantageous low pass filter.

The first capacitor C1 121 has one terminal connected to the loop filter 105 input and the second terminal connected to ground (or earth).

The low drop out has a reference input 207 connected to the loop filter 203 input (and to the first capacitor C1 121 first terminal). The low drop out 205 further has a power supply input 209 connected to a power supply. In some embodiments of the invention the power supply may be unregulated power supply, for example from a battery or from a cell. In other embodiments of the invention the power supply for the LDO may be from a regulated power supply.

A first terminal of a second resistor R2 127 is connected to LDO 205 output 21 1 , A second terminal the second resistor R2 127 is connected to a first terminal of a third capacitor C3 129 and a first terminal of a third resistor R3 131. A second terminal of the third capacitor C3 129 is connected to ground. A second terminal of the third resistor R3 131 is connected to a first terminal of a fourth capacitor C4 133 and to the loop filter 105 output. A second terminal of the fourth capacitor C4 133 is connected to ground.

It would be appreciated that in order to further reduce the IC area used for the loop filter 203, further capacitors C1 121 , C3 129, C4 133 and resistors R2 127, R3 131 may be replaced or at least smaller components can be used, which may reduce the IC area used.

The resistor/capacitor/LDO network shown in figure 3 produces an improved and clearly defined low pass filter. As the number of capacitors required to implement the system is decreased then the amount of IC area used by the phased locked loop 201 is reduced. This would produce beneficial improvements in terms of cost and error rates of IC production as cost and error rates are roughly proportional to the IC area used in production of a device.

With respect to figure 4, the LDO 205 and VCO 107 are shown in further detail. In order to assist in the understanding of the embodiments of the invention the LDO 205 is shown connected directly to the input of the VCO 107. In other words the LDO 205 output 21 1 may for this example be considered to be the output of the loop filter which is connected to the input of the VCO 107.

The LDO comprises a reference input 207, a power supply input 209, an operational ampiifier (op-amp) 301, a field effect transistor (FET) 303, a first feedback resistor R1 ' 305, a second feedback resistor R2' 307, a LDO capacitor C_LDO 309 and a voltage output VCO_Vdd 21 1.

The reference input 207 is connected to a first input of the operational amplifier 301. The output of the op-amp 301 is connected to the gate of the FET 303. The power supply input 209 is connected to source of the FET 303. The drain of the FET 303 is connected to the voltage output VCO_Vdd 21 1 , the first terminal of the LDO capacitor C_LDO 309 and the first terminal of the second feedback resistor R2' 307. The second terminal of the second feedback resistor R2' 307 is connected to the second input terminal of the op- amp 301 and the first terminal of the first feedback resistor R1 ' 305. The second terminal of the first feedback resistor RV 305 is connected to ground.

With respect to the VCO 107, a differential oscillator is shown. The VCO 107 comprises a voltage input VC0_Vddjn 323, a current bias device 311, a VCO first FET 313, a VCO second FET 315, a resonance tank 317 and a frequency output F_out 321.

The VCO is configured such that the voltage input VCO_Vdd_in 323 is connected to one terminal of the current bias device 311. The second terminal of the current bias device is connected to the sources of the VCO first FET 313, and VCO second FET 315. The drains of the VCO first FET 313 and VCO second FET 315 are connected to the resonance tank 317. The gates of the VCO first FET 313 and VCO second FET 315 are cross coupled to the other FET drains, such that the VCO first FET 313 gate is connected to the VCO second FET 315 drain and the VCO second FET 315 gate is connected to the VCO first FET 313 drain.

The resonance tank 317 is further connected to ground.

As has been discussed about the LDO 205 power supply input 209 may be connected to an unregulated power supply, for example a battery or cell, or may be connected to a regulated power supply. The LDO voltage output

VCO_Vdd is defined by the resistive feedback network comprising the first feedback resistor R1 ' 305 and the second feedback resistor R2' 307. The dc output of the op-amp may be defined by the difference between the two inputs which is a proportion of the output voltage determined by the resistive network. In other words the dc component of the LDO voltage input follows the reference signal input.

The operation of the op-amp 301 , the resistive network and the FET and capacitor however produce a signal path from the reference input 207 to the LDO voltage output 211 which defines a low-pass filter. This low-pass filter may be used, as may be seen in figure 3, to replace the component resistors and capacitors of the ioop filter.

Furthermore the use of the LDO 205 op-amp 301 allows the embodiment loop filter to have a much higher input impedance than would be produced using the component resistors and capacitors shown in figure 2. This therefore reduces the signal loading effect on the output of the phase detector 103.

Furthermore the capacitor C_LDO rnay be an external component or integrated on iC. This capacitor C_LDO forms a part of the low pass function of the LDO and the low pass function of the LDO may therefore be used in this invention. In a VCO fine frequency tuning may be implemented by changing the control voltage of a varactor (or varactors). In embodiments of the invention the parasitic capacitances may be used for fine frequency tuning and varactor/varactors may be omitted. Utilizing parasitic capacitances in a DCO may therefore decrease any switchable capacitor matrix used for fine frequency tuning of a DCO.

With respect to figure 5, two of the parasitic capacitances within a Positive Metal Oxide Semiconductor (PMOS) FET are shown. The PMOS 401 is formed within a negatively doped region known as a n weil 409 within an intrinsic or slightly p doped substrate. The n well has well ties of more strongly doped regions n+ weil ties 413. Within the n well 411 are p doped regions forming the source 403 and drain 405 of the transistor. The area between the source 403 and drain 405 is known as the channel 409. Above the channel is the insulator 415 and above the insulator is the gate 407.

In normal operation of the transistor, the biasing of the transistor causes capacitances to be created between various terminals. For example one capacitor is formed between the n well and the source C_sb and a further capacitor is formed between the n well region and the drain Cdt_>- Typically these are known as parasitic capacitances. In this embodiment of the invention these parasitic capacitances may therefore be used for fine frequency tuning of the DCO.

Furthermore in other embodiments of the invention further parasitic capacitance effects, for example the parasitic capacitances of the VCO first FET 313, and VCO second FET 315 may be used assist in reducing the capacitor requirement within the VCO. The oscillation frequency of the VCO fou_t may be defined by the formula

fout = 1/ (2πV(LC_tot)) where L is the inductance of the VCO and C_tot is the total capacitance which may in embodiments of the invention include the resonance tank and any parasitic capacitances within the VCO, such as the parasitic capacitances within the VCO first FET 313, and VCO second FET 315.

Other parasitic capacitances which may be used in further embodiments of the invention include but are not ϋmited to any back-gate capacitances of the resonance tank loss cancelling transistors. In other words the back-gate capacitances of the FET transistors from the voltage controlled oscillator. Other parasitic capacitances also include, but are not limited to, the back-gate capacitances of the switching transistors used in the capacitance matrices/ladders used to select a central oscillation frequency, and any n-well capacitances from the n well protection shield located under the resonance inductor. N wells or n-isoiation layers may be used in !C designs to isolate critical blocks from the common substrate and hence to decrease substrate noise. This kind of protection shield under a resonance tank may generate parasitic capacitances and these capacitances may be used for fine frequency tuning of the synthesizer.

Although we have described the aforementioned PLL as being a VCO PLL it would be understood that similar improvements may be obtained in DCO PLL circuits implemented on integrated circuit technology. A typical Digital PLL may be implemented with two separate loops as may be shown in figure 6. Figure 6 shows the digital phase locked loop circuit 501 , which comprises a phase comparator 503, which receives the reference frequency and the output of the digitally controlled oscillator (DCO) 507 and outputs the phase difference between the two signals. The digital PLL 501 further comprises a first digital filter 505 which performs the operation of a first loop filter on the phase comparator output. The Digital PLL 501 further comprises a first loop branch where the filtered phase comparison information is passed to a second digital filter 506 and then to a first input of the digitally controlled oscillator 507 where the output of the second digital filter 506 is used to generate a control signal to the digitally controlled osciliator (DCO) 507 which when implemented in embodiments of the invention may be used for coarse frequency settings. The circuit 501 further comprises a second loop or branch where a tap from the digital filter is output to a LDO 511 similar to that described with respect to the analogue PLL circuit via a Digital to Analogue converter (DAC) 509 to the LDO 511 to generate a tuneable voltage output. The second loop or branch including the LDO may be used for fine frequency tuning.

By using the low-pass function of an LDO in a loop filter the embodiments of the invention wili decrease the siiicon area required by a loop filter and thus decrease the size of a possible PLL implementation on integrated circuits. Furthermore by using the parasitic capacitances within the voltage controlled oscillator to change the VCO oscillation frequency and in particular by using them for fine frequency tuning, it is possible to reduce the size of any varactors as used in voltage controlled osciilators or reduce the size or number of capacitors in a switchable capacitor matrix as used in a digitally controlled oscillators. In further embodiments of the invention the use of parasitic capacitances may be used to eliminate the varactor or capacitor matrix completely.

User equipment may comprise an apparatus such as those described in embodiments of the invention above.

it shali be appreciated that the term user equipment is intended to cover any suitable type of wireless user equipment, such as mobile telephones, portable data processing devices or portable web browsers.

Furthermore elements of a public land mobile network (PLMN) may also comprise apparatus as described above.

In general, the various embodiments of the invention may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the invention is not limited thereto. While various aspects of the invention may be illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

For example the embodiments of the invention may be implemented as a chipset, in other words a series of integrated circuits communicating among each other. The chipset may comprise microprocessors arranged to run code, application specific integrated circuits (ASICs), or programmable digital signal processors for performing the operations described above.

The embodiments of this invention may be implemented by computer software executable by a data processor of the mobile device, such as in the processor entity, or by hardware, or by a combination of software and hardware. Further in this regard it should be noted that any blocks of the logic flow as in the

Figures may represent program steps, or interconnected logic circuits, blocks and functions, or a combination of program steps and logic circuits, blocks and functions.

The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory. The data processors may be of any type suitable to the local technical environment, and may include one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and processors based on multi-core processor architecture, as non-limiting examples.

Embodiments of the inventions may be practiced in various components such as integrated circuit modules. The design of integrated circuits is by and large a highly automated process. Complex and powerful software tools are available for converting a logic level design into a semiconductor circuit design ready to be etched and formed on a semiconductor substrate.

Programs, such as those provided by Synopsys, Inc. of Mountain View, California and Cadence Design, of San Jose, California automatically route conductors and locate components on a semiconductor chip using well established rules of design as well as libraries of pre-stored design modules.

Once the design for a semiconductor circuit has been completed, the resultant design, in a standardized electronic format (e.g., Opus, GDSII, or the like) may be transmitted to a semiconductor fabrication facility or "fab" for fabrication.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skiiled in the relevant arts in view of the foregoing description, when read In conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.

Claims

1. A phase locked loop comprising; an oscillator configured to generate an adjustable frequency signal; a low drop out circuit comprising at least one capacitor configured to be connected to the oscillator.

2. The phase locked loop as claimed in claim 1 , wherein the low drop out circuit may be configured to affect at least one of: a loop filtering of the output of the phase error; and the adjustable frequency signal tuning.

3. The phase locked loop as claimed in claims 1 and 2, wherein the oscillator further comprises at least one parasitic capacitor which is used in association with the low drop out circuit.

4. The phase locked loop as claimed in claim 3, wherein the at least one parasitic capacitor comprises at least one of: a parasitic capacitor in at least one field effect transistor of the oscillator; a parasitic capacitor in a resonance tank loss cancelling transistor; a parasitic capacitor in a switching transistor; and a parasitic capacitor in a n well protection shield.

5. The phase locked loop as claimed in claims 1 to 4, wherein the oscillator comprises a voitage controlled oscillator, and the phase locked loop comprises a loop filter comprising the low drop out circuit.

6. The phase locked loop as claimed in claim 5, wherein the low drop out circuit is configured to receive a partially filtered phase error signal input and a power supply input and output a voltage controlled oscillator supply voltage output to the voltage controlled oscillator, wherein the voltage controlled oscillator supply voltage output is configured to contro! the output frequency of the voltage controlled oscillator.

7. The phase locked ioop as claimed in claims 1 to 4, wherein the oscillator comprises a digitally controlled oscillator, wherein the phase locked loop comprises: a digital loop filter configured to receive a digitally coded phase error signal, generate a first filtered output and a second filtered output, wherein the first filtered output is configured to be connected to a first input of the digitally controlled oscillator; and a digital to analogue converter configured to receive the second filtered output and generate an analogue version of the second filtered output, the low drop out circuit is configured to receive the analogue version of the second filtered output and a power supply input and output a digitally controlled oscillator supply voltage output to the digitally controlled oscillator, wherein the first filtered output is configured to coarsely control the output frequency of the digitally controlled oscillator and the digitally controlled oscillator supply voltage output is configured to finely control the output frequency of the digitally controlled oscillator.

8. The phase locked loop as claimed in claims 1 to 7, wherein the low drop out circuit comprises: an operational amplifier configured to output a switching signal; a pass transistor configured to receive the switching signal to control a received power supply signal to be output; and a filter comprising the low drop out capacitor configured to provide a feed back route for the operational amplifier.

9. The phase locked loop as claimed in claim 8, wherein the received power supply comprises at least one of: a unregulated power supply; a battery; a cell; and a regulated power supply.

10 The phase locked loop as claimed in claims 8 and 9, wherein the pass transistor is a field effect transistor. switching transistor = pass transistor

11. The method for operating a phase locked loop comprising; generating at an adjustable oscillator an adjustable frequency signal; connecting a low drop out circuit comprising at (east one capacitor to the oscillator.

12. The method for operating the phase locked loop as claimed in claim 11 , further comprising: performing a loop filtering of a phase error using the circuit.

13. The method for operating the phase locked loop as claimed in claims

11 and 12, further comprising; tuning the adjustable oscillator frequency signal using the low drop out circuit output voltage.

14. The method for operating the phase locked loop as claimed in claims 1 1 to 13, further comprising: providing at least one parasitic capacitor which is used in association with the iow drop out circuit output.

15. The method for operating the phase locked loop as claimed in claim 14, wherein providing the at least one parasitic capacitor comprises using the at least one parasitic capacitor from at least one of: a parasitic capacitor in at feast one field effect transistor of the oscillator; a parasitic capacitor in a resonance tank loss cancelling transistor; a parasitic capacitor in a switching transistor of coarse tuning matrix; and a parasitic capacitor in a n well protection shield.

16. The method for operating the phase locked loop as claimed in claims 1 1 to 15, wherein the oscillator comprises a voltage controlled oscillator, and the phase locked loop comprises a loop filter comprising the low drop out circuit.

17. The method for operating the phase locked loop as claimed in claim 16, further comprising receiving at the low drop out circuit a partially filtered phase error signal input and a power supply input; and outputting a voltage controlled oscillator supply voltage output to the voltage controlled oscillator, wherein the voltage controlled oscillator supply voltage output is configured to control the output frequency of the voltage controlled oscillator.

18. The method for operating the phase locked loop as claimed in claims 11 to 15, wherein the oscillator comprises a digitally controlled oscillator, wherein the phase locked loop comprises: a digital loop filter and a digital to analogue converter, the method further comprising receiving at the digital loop filter a digitally coded phase error signal; generating a first filtered output and a second filtered output, wherein the first filtered output is configured to be connected to a first input of the digitally controlled oscillator; receiving at the digital to analogue converter the second filtered output and generate an analogue version of the second filtered output, receiving at the low drop out circuit the analogue version of the second filtered output and a power supply input; and outputting from the low drop out circuit a digitally controlled oscillator supply voltage output to the digitally controlled oscillator, wherein the first filtered output is configured to coarsely control the output frequency of the digitally controiled oscillator and the digitally controlled oscillator supply voltage output is configured to finely control the output frequency of the digitally controlled oscillator.

19. An apparatus comprising a phase locked loop as claimed in claims 1 to 10.

20. A frequency synthesizer comprising a phase locked loop as claimed in claims 1 to 10.

21. A chipset comprising a phase locked loop as claimed in claims 1 to 10.

22. An electronic device comprising a phase locked loop as claimed in claims 1 to 10.

23. A computer program product configured to perform a method for operating a phase locked loop comprising; generating at an adjustable oscillator an adjustable frequency signal; connecting a low drop out circuit comprising at least one capacitor to the oscillator.

24. A phase locked loop comprising; oscillator means configured to generate an adjustable frequency signal; signal processing means for generating a low drop out circuit comprising at least one capacitor configured to be connected to the oscillator.