WO2009101015A1

WO2009101015A1 - An oscillator

Info

Publication number: WO2009101015A1
Application number: PCT/EP2009/051283
Authority: WO
Inventors: Janne Olavi Peltonen; Sami Tapani Vilhonen
Original assignee: Nokia Corporation
Priority date: 2008-02-13
Filing date: 2009-02-04
Publication date: 2009-08-20
Also published as: GB0802660D0

Abstract

A digitally controlled oscillator comprising: an oscillator core configured to output an adjustable frequency output; and an oscillator tuner comprising at least one switchable impedance stage configured to control the oscillator core frequency output.

Description

AN OSCILLATOR

Field of the Invention

The present invention is related to a digitally controlled oscillator, and more particularly but not exclusively a digitally controlled oscillator in a frequency synthesizer.

Background

One of the key building blocks found in most electronic equipment is the frequency synthesizer. The frequency synthesizer outputs an oscillator output which may be used for signal generation or signal mixing.

Signal mixing may be used for example in a receiver to down convert a received radio frequency signal to a baseband frequency signal in order that the modulating/information signal, in the received signal may be separated from the carrier signal. Similarly signal mixing may be used in a transmitter to up convert the information/modulating signal to the carrier frequency.

In a transmitter the modulating signal is formed in the base band frequency (i.e. around zero frequency). For example a phase of certain selected pulse form is modulated depending on the information that is to be transmitted. In a communication system using a radio channel to transmit the information, the base band signal is then up-converted to a radio frequency of the radio channel by mixing it with a local oscillator (LO) signal. In a direct conversion transmitter the mixing is carried out in one stage and the base band signal is therefore multiplied with a local oscillator signal which has a frequency determined by the radio channel used in that particular communication system. In a frequency domain representation this can be described as the base band signal being transferred from a zero frequency to the local oscillator frequency which in the case of the direct conversion transmitter is in the middle of the transmitted channel. In a receiver the local oscillator is used to convert the received signal down in frequency from the received signal radio frequency to the base band (zero frequency) or intermediate frequency, In case of a direct conversion receiver the received signal is mixed to the zero frequency in a single stage. In this way the carrier component (i.e. the frequency component in the LO frequency band) of the received signal is removed and the synchronization to the modulated base band signal is possible

Frequency synthesizers have traditionally been created using crystal oscillators, phase locked loops (PLL) using voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO).

These typicaily use a voltage controlled capacitor to generate a tuneable frequency output.

For example analogue frequency control of a voltage controlled oscillator is typicaily accomplished with a varactor diode. The varactor diode changes its capacitance dependent on the potential difference (voltage) across the diode.

This changing capacitance typically changes the resonance of the oscillator and thus affects the output frequency of the oscillator. Voltage contra! however may require several auxiliary circuits which are costly to implement and also may occupy a large amount of silicon area within an integrated circuit.

Furthermore digital oscillator frequency control is also problematic. A fully digitally controlled oscillator requires a large number of control bits in order to enable the control of the oscillator to produce a wide tuning range and yet to be able to cover the full range with sufficient resolution.

Typical methods use an oscillator core with a parallel connection of binary weighted switched capacitors. These switched capacitors are formed from capacitors and series switches that have two digital states (an 'on¹ and an 'off' state). The direct parallel connection however typically suffers from poor matching of weighting values. Device matching of the capacitors should achieve an accuracy better than 1/2 of a ieast significant bit (Isb) value. If the device matching can not provide this the oscillator may not be able to ensure that a monotonic function may be achieved (in other words that a switching of one capacitor may cause the device to change output frequency in a direction opposite to that intended).

Furthermore, the parallel connection may have a limited step size at the lower end of the selection range. Step size is typically limited by practical size considerations, and it is not usually possible to create small enough capacitor values required for the least significant bit step size with a parallel connection.

An example of such an approach Is the use of the digitally controlled capacitor matrix where a switch^' matrix can be selected by a row selection and column selection approach such as shown in US published patent application number US-2004066240.

Summary of the Invention

It is an object of the present invention to provide a controllable oscillator which overcomes the disadvantages of the prior art, or at least provides a useful alternative.

According to a first aspect of the present invention there is provided a digitally controlled oscillator comprising an oscillator core configured to output an adjustable frequency output; and an oscillator tuner comprising at least one switchable impedance stage configured to control the oscillator core frequency output.

Each switchable impedance stage may comprise a first impedance element and a second impedance element, wherein the second impedance element Is configured to be switchably connected to the oscillator core. The second impedance element is preferably configured to be switchably connected to an inverted value from the oscillator core.

The oscillator tuner may further comprise a switch configured to switchably connect the second impedance element to either the oscillator core or the inverted value from the oscillator core.

The second impedance element is preferably configured to be switchabiy connected to either the oscillator core or the inverted value from the oscillator core via at least one of an attenuator and a phase shifter.

The oscillator core may further comprise a resonance tank circuit configured to output a voltage supply value to the second impedance element and an inverted value of the voltage supply value to the second impedance element.

The resonance tank circuit may further be configured to receive an input voltage supply and generate the voltage_. supply value dependent on the input voltage supply.

The oscillator tuner may comprise at least two switchable impedance stages, wherein a first stage is connected directly to the oscillator core and each subsequent stage is connected to a previous stage in a ladder arrangement.

The first impedance stage may comprise; the first impedance element comprises a first node connected to the oscillator core and a second node connected to a first node of the second impedance element; and the second impedance element may comprise a second node switchably connected to the oscillator core.

The second impedance stage may comprise: a second impedance stage first impedance element comprises a first node connected to the second node of the first impedance stage first impedance element, and a second node connected to a first node of the second impedance element; and a second Impedance stage second impedance element may comprise a second node switchabiy connected to the oscillator core.

Each impedance element may comprise a capacitor,

The first impedance element capacitor may have a capacitance value which is twice a capacitance value of the second impedance element capacitor.

According to a second aspect of the present invention there is provided a method for operating a digitally controlled oscillator comprising outputting an adjustable frequency output; and controlling the adjustable frequency output by switchabiy operating at least one switchable impedance stage.

Each switchable impedance stage may comprise a first impedance element and a second impedance element, and switchabiy operating at least one switchable impedance stage may comprise switchabiy operating the second impedance element to be connected to the oscillator core.

Switchabiy operating at least one switchable impedance stage may further comprise switchabiy connecting the second impedance element to an inverted value from the oscillator core.

Switchabiy connecting the second impedance element to the oscillator core or an inverted value from the oscillator core may comprise switchabiy connecting with at least one of an attenuation and phase shifting.

The method for operating the oscillator may further comprise generating a voltage supply value and an inverted value of the oscillator core.

The method for operating the oscillator may further comprise receiving an input voltage supply and the generating of the oscillator core value being dependent on the input voltage supply. Controlling the adjustable frequency output may comprise switchabiy operating at least two switchable impedance stages, the method may further comprise connecting a first switchable impedance stage directly to the oscillator and connecting each subsequent stage to the preceeding stage in a Sadder arrangement.

A mixer may comprise an oscillator as featured above.

An apparatus may comprise an oscillator as featured above.

A frequency synthesizer may comprise an oscillator as featured above.

A chipset may comprise an oscillator as featured above.

An electronic device may comprise an oscillator as featured above.

According to a third aspect of the present invention there is provided a computer program product configured to perform a method for operating a digitally controlled oscillator comprising outputting an adjustable frequency output; and controlling the adjustable frequency output by switchabiy operating at least one switchable impedance stage-

According to a fourth aspect of the invention there is provided a digitally controlled oscillator comprising signal oscillation means for outputting an adjustable frequency output; and controlling means for controlling the signal oscillation means, wherein the controlling means comprises at least one switchable impedance stage.

Brief Description of the Drawings

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 shows a schematic diagram of a user equipment capable of implementing embodiments of the invention;

Figure 2 shows a schematic diagram illustrating an embodiment of the invention capable of being implemented within the user equipment of Figure 1; Figure 3 shows a schematic diagram illustrating an embodiment of the invention capable of being implemented within figure 1 and 2; and Figure 4 shows a schematic diagram illustrating a further embodiment of the invention.

Detailed Description of Preferred Embodiments

Figure 1 shows a schematic partially sectioned view of a possible electronic device capable of implementing embodiments of the invention. The electronic device may be a user equipment as shown in Figure 1 used for various tasks such as making and receiving phone calls, for receiving and sending data to and from a data network and for receiving and transmitting the data in the form of multimedia content. Although an electronic device is shown in the form of user equipment and specifically the implementation of the oscillator for communication purposes embodiments of the invention may be implemented in any electronic device requiring a stable but tuneable oscillator.

An appropriate electronic device may be any device capable of sending or receiving radio signals. Non-limiting examples include mobile stations (MS), user equipment (UE), portable computer equipment provided with a wireless interface card or other wireless interface facility, persona! data assistants (PDA) provided with wireless communication capabilities, or any combinations of these or the like.

The electronic device may communicate via an appropriate radio interface arrangement of the mobile device. The interface arrangement may be provided by means of a radio frequency and associated antenna arrangement 7. The antenna arrangement may be arranged intemaliy or externally to the electronic device. The radio part may comprise at least one mixer configured to down-convert or up-convert signals to and from the mobile station. The mixer device may comprise a tuneable frequency synthesiser according to the embodiments of the invention. The term frequency synthesiser may also be known as a frequency oscillator. The frequency synthesiser/frequency oscillator may be capable of supplying an oscillation signal of various predetermined or defined frequencies.

The electronic device is typically provided with at least one data processor 3 and at least one memory 4 for storing data and instructions used by the data processor 3. The data processor 3 and memory 4 may be provided on an appropriate circuit board and/or in chip sets 6.

The user may control the operation of the electronic device by means of a suitable user interface such as a keypad 2, voice command, touch-sensitive screen or pad, or a combination thereof or the like. A display 5, a speaker and a microphone are also typically provided. Furthermore, an electronic device may comprise appropriate connectors (either wired or wireless) to other electronic devices and/or for connecting external accessories, for example hands-free equipment, thereto.

The remainder of the parts of the electronic device are known generally and do not assist in the understanding of the invention and will not be described in further detail hereafter.

Figure 2 shows a schematic view of a frequency synthesiser as implemented within the radio part 7 of Figure 1.

The frequency synthesiser 101 may be considered to comprise a series of interconnected functional blocks.

The phase detector (PD) 107 receives the reference source input F_ref and the output of the digitally controlled oscillator 105 and outputs a detected phase signal to the discrete time loop filter 103. The phase detector 107 comprises a reference accumulator 121, a discrete time-domain integrator which receives the reference source input signal (FREF) and outputs values which increase by an amount defined by the synthesiser channel control for every reference source input signal cycle,

The output of the reference accumulator 121 is connected to a summing device 123. The summing device 123 also receives an output from the digitally controlled oscillator phase measurement decoder and sealer 125 and outputs the difference value between the output of the reference accumulator 121 and the output of the digitally controlled oscillator phase measurement decoder and scaler 125. This difference value is output to the discrete-time loop filter 103.

The phase detector 107 furthermore comprises a digitally controlled oscillator (DCO) accumulator and time-to-digital converter (TDC) 127. The DCO accumulator may be a discrete time integrator which receives an input from the output of the digitally controlled oscillator 105 and produces an output which is read for every reference source input signal cycle.

The time-to-digita! converter measures the timing difference between the digitally controlled oscillator (DCO) and the reference source input signal.. An example of a time-to-digital converter which may be implemented within an embodiment of the invention is shown in a co-pending application by the same applicant as shown in GB application XXXX (Nokia Reference 61289: PWF Reference 316141 GB). In other embodiments of the invention Vernier delay line (VDL) time-to-digital converters may be used to produce an output.

The DCO accumulator and TDC 127 output a result value to the DCO calibration logic 111. The DCO accumulator and TDC 127 furthermore output a TDC result value to the TDC calibration logic 109. The DCO accumulator and TDC 127 also output a DCO accumulator result value and the TDC result value to the DCO phase measurement decoder and sealer 125. The DCO phase measurement decoder and sealer 125 receives the DCO accumulator result value and the TDC result value and samples these values for each reference source input signal cycle.

The sealer produces a scaling of TDC result value according to the desired frequency (which in transceivers is dependent on the transceiver channel), In other words the TDC result value is normalized by the scaler to produce a TDC result value which is normalized to the full cycle of the desired digitally controlled oscillator (DCO) period. The scaled TDC result and DCO accumulator result values are passed to the summing device for comparison with the reference source input signal as described previously above,

The TDC calibration logic 109 receives the output from the DCO Accumuiator and TDC unit 127 and outputs to the DCO phase measurement decoder and scaling block 125. The TDC calibration logic block 109 maintains a control of the DCO phase measurement decoder and sealer 125 such that the TDC signal is kept within certain limits. For example, the TDC calibration logic block 109 tracks the changes in the measurement resolution due to environmental changes and compensates for effects in both environmental changes and 1C production variations to prevent these limits being exceeded.

The control state machine 135 controls the operation of the frequency synthesizer 101 so that there may be a separate phase-locked loop settling state and a locked-in state.

The discrete-time loop filter (which may be a configurable infinite impulse response filter) 103 receives the detected phase difference signal from the phase detector 107 and outputs a filtered phase difference to the digitally controlled oscillator 105. The discrete-time loop filter 103 may be configured to produce a zero-pole pair for the loop transfer function in order to stabilise the loop. The discrete-time loop filter 103 may be configured so that the location of the zero and the pole may be adjustable in order to optimise the in- band noise for a certain system or to tune the filter during the settling sequence in such a manner that the settling period is shorter. The digitally controlled oscillator (DCO) 105 receives the input from the discrete-time loop filter 103 (configurable infinite impulse response filter) and outputs the digitally controlled oscillator output to the phase detector 107.

The discrete controlled oscillator block 105 comprises a discrete controlled oscillator control mapping block 131 and a digitally controlled oscillator 131.

The discrete controlled oscillator control mapping block 131 receives outputs from the configurable infinite impulse response filter 103 and the discrete controlled oscillator (DCO) calibration logic 111, The DCO control mapping block 131 comprises a series of mappings by which input signals are mapped to produce a control output for the digitally controlled oscillator 133, The digitally controlled oscillator control mapping block 131 in practice has several parallel control matrices to produce the mapping function.

The DCO calibration logic block 111 receives the output of the DCO accumulator and determines if there has been any potential drift of the digitally controlled oscillator tuning characteristics due to IC processing variations and environmentally variations and provides a trimming or adjustment signal to the DCO control mapping to assist in the prevention in any change of the output frequency due to environmental conditions or construction changes.

Figure 3 is a schematic view of the digitally controlled oscillator and control mechanism as an embodiment of the invention.

The embodiment of the invention shows an arrangement of digitally switched capacitors connected to the oscillator core 203 is shown.

The oscillator 133 shown in Figure 3 comprises an osciilator core 203 arranged to output 299 an oscillation frequency which is tuneable dependent on the value of the capacitance between the oscillator core and ground. The oscillator core 203 is connected to an attenuator and phase shifter 205, The attenuator and phase shifter is furthermore connected to a capacitor ladder 209. The oscillator core 203 is connected to a ground 297 via the capacitor ladder 209.

The capacitor ladder 209 comprises at least one capacitor rung or stage. The embodiment shown in Figure 3 shows six capacitor rungs. The first capacitor rung 251 is connected to the oscillator core 203 and the second capacitor rung 253. The second capacitor rung 253 is connected to the first capacitor rung 251 and the third capacitor rung 255. The third capacitor 255 is connected to the second capacitor rung 253 and the fourth capacitor rung 257. The fourth capacitor rung is connected to the third capacitor rung 255 and the fifth capacitor rung 259. The fifth capacitor rung is connected to the fourth capacitor rung 257 and the sixth capacitor rung 261 , The sixth capacitor rung is connected to the fifth capacitor rung 259 and the anchor capacitor 263. The anchor capacitor 263 is connected to the ground 297.

In other embodiments of the invention there may be more capacitor rungs or fewer capacitor rungs,

Each capacitor rung 251, 253, 255, 257, 259, 261, comprises a first capacitor 221 with a value of C1 and a second capacitor 223 which has a capacitor value of C2,

The first capacitor 221 of each rung is connected so that a first terminal is connected to a preceding rung/stage and a second terminal is connected to a succeeding rung/stage. In other words each first capacitor 221 is connected between the rungs/stages.

Thus a first rung 251 first capacitor 221a has a first terminal connected to the oscillator core 203 and a second terminal connected to a second rung 253 first capacitor 221b first terminat. The second rung 253 first capacitor 221 b second terminal is connected to the third rung 255 first capacitor 221c first terminal.

The third rung 255 first capacitor 221 c second terminal is connected to the fourth rung 257 first capacitor 221d first terminal.

The fourth rung 257 first capacitor 221 d second terminal is connected to the fifth rung 259 first capacitor 221 e first terminal.

The fifth rung 259 first capacitor 221 e second terminal is connected to the sixth rung 261 first capacitor 221f first terminal.

The sixth rung 261 first capacitor 221 f second terminal is connected to a first terminal of the anchor capacitor 263. The second terminal of the anchor capacitor being connected to the ground terminal 297.

The second capacitor 223 may be arranged so that the n'th rung second capacitor 223 first terminal is connected to the n'th rung first capacitor 221 second terminal, and the n'th rung second capacitor 223 second terminal is connected to a n'th rung switch 225 first terminal.

For example the first rung 251 second capacitor 223a first terminal is connected to the first rung 251 first capacitor 221a second terminal (which also means that the first rung 251 second capacitor 223a first terminal is also connected to the second rung 253 first capacitor 221 b first terminal).

Furthermore the first rung 253 second capacitor 223a second terminal is connected to the first rung 251 switch 225a first terminai.

The switch 225 connects the first terminal to either a phase 160 degrees attenuation line (Phase_180_Atten) 208 or the phase 0 degree attenuation line (Phase_0_Atten) 207. Both attenuation lines are connected to the attenuator and phase shifter 205. Thus for example the first rung 251 switch 225a can connect the first rung 251 first switch 225a to a first rung phase 180 degrees attenuation terminal 227a connected to the phase 180 degree attenuation line 208, or to a first rung 251 0 degree attenuation terminal 229a connected to the phase 0 degree attenuation line 207.

The arrangement of the switching is that each ladder rung or step halves the oscillator signal voltage swing. This therefore produces an effect where each stage effectively operates as a binary division switch.

For example, in the example shown in Figure 3 of six stages/rungs, a resolution of 2^β steps are available. In other words 64 different capacitor values are selectable.

As would be understood by the person skilled in the art the length of the ladder defines the minimum size of step - and this it is possible to construct a oscillator with as large or as small a step are required.

Furthermore the requirement for component matching is relaxed compared against the prior art methods as a monotonic variation is guaranteed by the design itself.

In embodiments of the invention, the capacitor value of C1 is chosen to be twice the value of C2.

Thus the capacitance seen by the oscillator core 203 can be easily modified in embodiments of the present invention by switching the switches DO 225f (in the sixth rung 261) to D5 225a (the switch in the first rung 251 ).

Furthermore the attenuator and phase differentia! form of the oscillator reverse phase signal is also available.

Frequency change may be achieved by adding or subtracting small amounts of current from the oscillator main resonator. In such embodiments of the invention current is added or subtracted using either the 0 degree or 180 phase switches. Furthermore the magnitude of the added current defines in embodiments of the invention the step size, in other words the resolution of the tuning of the DCO. The attenuator may be used to add the current values to produce the ful! correct current value.

The attenuator may be resistive in embodiments of the invention. However in further embodiments of the invention the attenuator may be capacitive or inductive.

In embodiments of the invention, the attenuator can be formed from capacitor voltage divider networks or resistive voltage divider networks.

In some embodiments of the invention the attenuator may be a 4 resistor resistive divider.

The resistive attenuator in such embodiments of the invention may be connected to. the resonator main resonance tank (which has a large voltage swing).

In other embodiments of the invention, the attenuation phase shifting may be achieved using an active network for example a buffer,

in some embodiments of the invention, the attenuation block may be formed using a further switchable ladder.

The attenuation seen by the oscillator core has an impact on the tuning sensitivity.

The tuning of the output frequency is achieved by connecting the switch capacitor to an in-phase or opposite-phase signal. The switching between these two wili therefore change the total capacitance of the network. The capacitance ladder has been shown to be connected to be in parallel with the osciilator core resonator.

In embodiments of the invention, the oscillator core 203 comprises a resonator formed from an inductor with some coarsely tuneable capacitors (or fixed capacitors) in parallel.

The induction values from the inductors and the total capacitance resonance define the oscillation frequency of the oscillator. The oscillator core 203 topology can be selected from any known oscillator core technology. For example the oscillator core 203 may be formed from active units.

With respect to figure 4, the interconnection between an implantation of the oscillator core 203, an implementation of the attenuator and phase shifter 205 and the fine frequency control implemented by switched capacitors 209 is shown in more detail.

in the embodiment of the invention shown in figure 4, the oscillator core 203 comprises a current source 401 connected between a voltage rail V_ss and a first terminal of a pair of cross linked p-mos transistors 403 and 405. The p- mos transistors have each gate (or second) terminal connected the the other p-mos transistor third terminal. Each of the p-mos transistors 403, 405 third terminals are further connected to an opposite terminal of a preset capacitor 407. Each of the p-mos transistors 403, 405 third terminals are further connected via a inductor 409, 411 to the ground or sink voltage V_dd.

The oscillator core operates by generating an oscillation across the oscillation terminals 451a and 451 b which is the connection between the capacitor, inductor and transistors on each side of the circuit. The core oscillator preset capacitor 407 and inductors 409 and 411 operate to generate a coarsely adjustable oscillation determined by the capacitor and inductor values as the transistors 403 and 405 alternately switch on and off. The attenuator and phase shifter 205 in this embodiment of the invention comprises two sets of potential dividers. Each potential divider provides an attenuated voltage either in phase or in anti-phase to the capacitor ladder 209.

The first potential divider has a first terminal 481 connected to the first oscillator terminal 451a, a second terminal 483 connected to an anti-phase voltage line 473, and a third terminal 485 connected to the ground or negative voltage supply V_dd. The first potential divider first terminal 481 is connected to the second terminal 483 via a first resistor Ri 413, and the second terminal 483 is connected to the third terminal 485 via a second resistor R₂ 415. Typically the value of the first resistor Ri 413 is larger than the value of the second resistor R₂ 415 and thus the voltage at the second terminal 483 is nearer the ground or negative voltage supply V_dd than the voltage at the first oscillator terminal 451 a.

The second potential divider has a first terminal 491 connected to the second oscillator terminal 451b, a second terminal 493 connected to an in-phase voltage line 471, and a third terminal connected to the ground or negative voltage supply Vdd. The second potential divider first terminal 491 is connected to the second terminal 493 via a first resistor R-i 417, and the second terminal 483 is connected to the third terminai 485 via a second resistor R₂ 419. As described previously typically the value of the first resistor R₁ 417 is larger than the value of the second resistor R₂ 419 and thus the voltage at the second terminal 493 is nearer the ground or negative voltage supply Vd_d than the voltage at the second oscillator terminal 451 b.

As the oscillator is a differential or two sided oscillator the capacitor ladder 209 comprises a first capacitor ladder part 209a, which in figure 4 shows a first stage 251a and a second stage 253a, and a second capacitor ladder part 209b which shows an associated second capacitor ladder part first stage 251 b and second stage 253b. Each part comprises a separate capacitor ladder arrangement as shown in figure 3 and described in detail above. The first and second capacitor parts first stages 251a and 251 b of each part are connected to an associated core oscillator 203 oscillator terminal, so that the first part first stage 251a is connected to the core oscillator first terminal 451a and the second part first stage 251b is connected to the core oscillator second terminal 451b respectively. Similarly each part second stage is connected to its associated part first stage, thus the first part second stage 253a is connected to its associated first part first stage 251a and the second part second stage 253b is connected to its associated second part first stage 251b.

Each stage is as described above switchably connected to either to the in- phase voltage line 471 or the anti-phase voltage line 473 dependent on the value of the switch word B where the most significant bit of the switch word controls the first stage switches Ds_a and Dsb and the next significant bit of the switch word controls the second stage switched D_4a and D^, and the least significant bit of the switch word controls the final stage switches (not shown in figure 4).

Thus it can be seen that a fine digital frequency control may be configured by providing the switch word value to the stage switched and thus switching each stage to either the iπ-phase or anti-phase voltage lines.

The attenuator and phase shifter 205 shown in the differential oscillator arrangement above is purely resistive, and produces attenuated versions of the in-phase and anti-phase oscillator outputs. However in further embodiments of the invention the attenuator may comprise or further comprise capadtive or inductive elements which produce voitage lines which are in anti-phase with respect to each other and phase delayed with respect to the two oscillator terminal outputs.

In some embodiments of the invention, the attenuator and phase shifter 205 may be formed using a pair of switchable ladders comprising rungs or stages comprising resistive, capacitive, and inductive elements or any combination of resistive, capacitive and inductive elements in order that the voltage line outputs are finely controllable.

The inductor values from the inductors 409, 411 and the total capacitance from the coarse tuning capacitor 407 and the capacitor ladder 209 define the oscillation frequency of the oscillator.

User equipment may comprise an apparatus such as those described in embodiments of the invention above.

It shall be appreciated that the term user equipment is intended to cover any suitable type of wireless user equipment such as mobile telephones, portable data processing devices or portable web browsers.

Furthermore elements of a public land mobile network (PLMN) may also comprise apparatus as described above.

In general, the various embodiments of the invention and/or control of various embodiments of the invention may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the invention is not limited thereto. While various aspects of the invention may be illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non- limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

For example embodiments of the invention may be implemented as a chipset, in other words a series of integrated circuits communicating among each other. The chipset may comprise microprocessors arranged to run code, application specific integrated circuits (ASiCs), or programmable digital signal processors for performing the operations described above.

The embodiments of this invention may be implemented or controlled by computer software executable by a data processor of the mobile device, such as in the processor entity, or by hardware, or by a combination of software and hardware. Further in this regard it should be noted that any blocks of the logic flow as in the Figures may represent program steps, or interconnected logic circuits, blocks and functions, or a combination of program steps and logic circuits, blocks and functions,

The data processors may be of any type suitable to the local technical environment, and may include one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and processors based on multi-core processor architecture, as non-limiting examples.

Embodiments of the inventions may be practiced in various components such as integrated circuit modules. The design of integrated circuits is by and large a highly automated process. Complex and powerful software tools are available for converting a logic level design into a semiconductor circuit design ready to be etched and formed on a semiconductor substrate.

Programs, such as those provided by Synopsys, Inc. of Mountain View, California and Cadence Design, of San Jose, California automatically route conductors and locate components on a semiconductor chip using well established rules of design as well as libraries of pre-stored design modules. Once the design for a semiconductor circuit has been completed, the resultant design, in a standardized electronic format (e.g., Opus, GDSl!, or the like) may be transmitted to a semiconductor fabrication facility or "fab" for fabrication.

The foregoing description has provided by way of exemplary and non-ϋmiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, ail such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.

Claims

1. A digitally controlled oscillator comprising; an oscillator core configured to output an adjustable frequency output; and an oscillator tuner comprising at least one switchable impedance stage configured to control the oscillator core frequency output,

2. The oscillator as claimed in claim 1, wherein each switchable impedance stage comprises a first impedance element ahd a second impedance element, wherein the second impedance element is configured to be switchably connected to the oscillator core.

3. The oscillator as claimed in claim 2, wherein the second impedance element is configured to be switchably connected to an inverted value from the oscillator core .

4. The oscillator as claimed in claim 3, wherein the oscillator tuner further comprises a switch configured to switchably connect the second impedance element to either the oscillator core or the inverted value from the oscillator core.

5. The oscillator as claimed in claim 4, wherein the second impedance element is configured to be switchably connected to either the oscillator core or the inverted value from the oscillator core via at least one of an attenuator and a phase shifter.

6, The oscillator as claimed in claim 3 to 5, wherein the oscillator core further comprises a resonance tank circuit configured to output a voltage supply value to the second impedance element and an inverted value of the voltage supply value to the second impedance element.

7. The oscillator as claimed in claim 6, wherein the resonance tank circuit further is configured to receive an input voltage supply and generate the voltage supply value dependent on the input voltage supply.

8. The oscillator as claimed in claims 1 to 7, wherein the oscillator tuner comprises at least two switchable impedance stages, wherein a first stage is connected directly to the oscillator core and each subsequent stage is connected to a previous stage in a ladder arrangement.

9, The oscillator as claimed in claim 8 when dependent on claim 2, wherein the first impedance stage comprises: the first impedance element comprises a first node connected to the oscillator core and a second node connected to a first node of the second impedance element; and the second impedance element comprises a second node switchably connected to the oscillator core.

10. The oscillator as claimed In claim 9, wherein the second impedance stage comprises: a second impedance stage first impedance element comprises a first node connected to the second node of the first impedance stage first impedance element, and a second node connected to a first node of the second impedance element; and a second impedance stage second impedance element comprises a second node switchably connected to the oscillator core.

1 1 , The oscillator as claimed in claims 2 to 10, wherein each impedance element comprises a capacitor.

12. The oscillator as claimed in claim 11 , wherein the first impedance element capacitor has a capacitance value which is twice a capacitance value of the second impedance element capacitor.

13. A method for operating a digitally controlled oscillator comprising: outputting an adjustable frequency output; and controlling the adjustable frequency output by switchably operating at least one switchable impedance stage.

14. The method for operating the oscillator as claimed in claim 13, wherein each switchable impedance stage comprises a first impedance element and a second impedance element, and switchably operating at least one switchable impedance stage comprises switchably operating the second impedance element to be connected to the oscillator core.

15. The method for operating the oscillator as claimed in claim 14, wherein switchably operating at Seast one switchable impedance stage further comprises switchably connecting the second impedance element to an inverted value from the oscillator core.

16. The method for operating the oscillator as claimed in claim 15, wherein switchably connecting the second impedance element to the oscillator core or an inverted value from the oscillator core, comprises switchably connecting with at least one of an attenuation and phase shifting.

17. The method for operating the oscillator as claimed in claims 14 to 16, further comprising generating a voltage supply value and an inverted value of the oscillator core,

18. The method for operating the oscillator as claimed in claim 17, further comprising receiving an input voltage supply and the generating of the oscillator core value being dependent on the input voltage supply.

19. The method for operating the oscillator as claimed in claims 12 to 18, wherein controlling the adjustable frequency output comprises switchably operating at least two switchable impedance stages, the method further comprising connecting a first switchabje impedance stage directly to the oscillator and connecting each subsequent stage to the preceeding stage in a ladder arrangement.

20. A mixer comprising an oscillator as claimed in claims 1 to 12.

21. An apparatus comprising an oscillator as claimed in claims 1 to 12.

22. . A frequency synthesizer comprising an oscillator as claimed in claims 1 to 12.

23. A chipset comprising an oscillator as claimed in claims 1 to 12.

24. An electronic device comprising an oscillator claimed in claims 1 to 12.

25. A computer program product configured to perform a method for operating a digitally controlled oscillator comprising: outputting an adjustable frequency output; and controlling the adjustable frequency output by switchably operating at least one switchable impedance stage.

26. A digitally controlled oscillator comprising: signal oscillation means for outputting an adjustable frequency output; and controlling means for controlling the signal oscillation means, wherein the controlling means comprises at least one switchable impedance stage.