WO2009082852A1 - Dispositif de tri de données pour traiter des données de communication - Google Patents

Dispositif de tri de données pour traiter des données de communication Download PDF

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Publication number
WO2009082852A1
WO2009082852A1 PCT/CN2007/003883 CN2007003883W WO2009082852A1 WO 2009082852 A1 WO2009082852 A1 WO 2009082852A1 CN 2007003883 W CN2007003883 W CN 2007003883W WO 2009082852 A1 WO2009082852 A1 WO 2009082852A1
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WIPO (PCT)
Prior art keywords
data
input
register
output
communication data
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Application number
PCT/CN2007/003883
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English (en)
Chinese (zh)
Inventor
Tianliang Sun
Original Assignee
Zte Corporation
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Priority to PCT/CN2007/003883 priority Critical patent/WO2009082852A1/fr
Publication of WO2009082852A1 publication Critical patent/WO2009082852A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
    • G06F7/24—Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers sorting methods in general

Definitions

  • the present invention relates to the field of communications, and in particular to a data sorting apparatus for processing communication data.
  • BACKGROUND OF THE INVENTION Sorting operations are common operations in various algorithms. The sorting operation is usually programmed in software and then implemented on a general purpose computing device. However, in the process of implementing the present invention, the inventors have found that at least the following problems exist in the prior art: The software implementation is serial processing, and even if the CPU operates at a higher frequency, the sorting operation still takes a lot of time.
  • the method is (1) taking the first input data as the current maximum value; (2) taking the next input data. Compared with the current maximum value, if the next input data is greater than the current maximum value, the next input data becomes the current maximum value; (3) repeat step 2 until all input data is processed; (4) the current maximum value is The input data is removed; (5) Steps 1 to 4 are repeated until m maximum values are found.
  • the m maximum values have been sorted in descending order of order, and the maximum value found for the first time is m values. The biggest one.
  • the above sorting operation is to sort all input data.
  • the number of clock cycles occupied by the software implementation of the sort operation is proportional to the factorial of n.
  • the time taken by the sorting operation is particularly significant. Real-time signal processing requires high real-time performance.
  • the sorting operation using the above techniques cannot meet the real-time requirements of real-time signal processing for data processing.
  • the current maximum or smaller is used as the new current minimum value, and the output is compared to the comparator for comparison;
  • the second register is used to save the smaller or larger one, and is output to the next-level data comparison unit; the output processing state machine And sequentially outputting the current maximum value or the current minimum value in the m cascaded data comparison units to obtain m
  • the communication data is from a queue
  • the input processing state machine includes: a first reader for sequentially reading communication data from the queue; and a counter for counting each time a communication data is retrieved from the queue, When n is counted, a full signal is issued; a first monitor for monitoring the full signal, the first read unit is disabled; and a first outputter for sequentially outputting the communication data to the first level data comparison unit.
  • the queue is a first in first out queue.
  • the selector comprises: two two-select multiplexers, comprising: a first two-select multiplexer, comprising: two inputs, wherein the first input is used for inputting communication data, and the second The input terminal is used to input the current maximum value or the current minimum value provided by the first register; 1 enable end for inputting the comparison result; and 1 output terminal for the communication end receiving the communication data whose comparison result is input
  • the second two-select multiplexer includes: 2 input terminals, wherein the second input end For inputting communication data, the first input is used to input the current maximum value or the current minimum value provided by the first register; 1 enable end for inputting the comparison result; and 1 output terminal for the enable end receiving
  • the comparison result is that the input communication data is greater than the current maximum value or less than the current minimum value, enabling the output of the current maximum value or the current minimum value input by the first
  • the output processing state machine comprises: a second reader for sequentially reading m cascaded data comparison units; and a counter for counting each data from the m cascaded data comparison units One time, when the count reaches m, a full signal is issued; the second monitor is used to monitor the full letter
  • the second read unit is disabled, and the second output is used to sequentially output data to a queue.
  • the queue is a first in first out queue.
  • the communication data is k bits, and all components in the data sorting device are components capable of processing k bits.
  • the first register and the second register are D flip-flops.
  • FIG. 1 is a circuit diagram of a hardware sequencer implementation apparatus according to an embodiment of the present invention
  • FIG. 2 is a circuit diagram of the data comparison unit of FIG. 1.
  • FIG. 3 shows an implementation of the present invention.
  • FIG. 4 is a state transition diagram of an output processing state machine in accordance with an embodiment of the present invention.
  • the present invention will be described in detail with reference to the accompanying drawings in conjunction with the embodiments.
  • the following is an example of sorting by the maximum value, but it is obvious that the present invention can also be applied to the minimum order as long as the maximum value is replaced with the minimum value and the smaller one is sorted.
  • the input data be n, and find the m maximum values sorted by size from the input data.
  • 1 shows a hardware sequencer implementation apparatus according to an embodiment of the present invention, which is composed of the following parts: an input processing state machine 10; an output processing state machine 30; m data comparison units 20.
  • the input processing state machine is configured to process the input n communication data;
  • the m cascaded data comparison units, m ⁇ n, each of which includes: a comparator, configured to input communication data and current
  • 3 P 17456 Comparing the maximum value or the current minimum value to obtain a comparison result; a selector for outputting the input communication data and the current maximum value according to the comparison result or the smaller one of the input communication data and the current minimum value to The first register outputs the smaller or larger to the second register; the first register is configured to save the larger one as the new current maximum value or the smaller one as the new current minimum value, and output the output to the comparator Comparing; a second register for storing the smaller or larger, outputting to the next level of data comparison unit; an output processing state machine for comparing the current maximum or current of the m cascaded data comparison units The minimum values are sequentially outputted to obtain m sorted communication data among the n communication data.
  • the communication data is from a queue
  • the input processing state machine includes: a first reader for sequentially reading communication data from the queue; and a counter for counting each time a communication data is retrieved from the queue, When n is counted, a full signal is issued; a first monitor for monitoring the full signal, the first read unit is disabled; and a first outputter for sequentially outputting the communication data to the first level data comparison unit.
  • the queue is a first in first out queue.
  • the selector comprises: two two-select multiplexers, comprising: a first two-select multiplexer, comprising: two inputs, wherein the first input is used for inputting communication data, and the second The input terminal is used to input the current maximum value or the current minimum value provided by the first register; 1 enable end for inputting the comparison result; and 1 output terminal for the communication end receiving the communication data whose comparison result is input
  • the second two-select multiplexer includes: 2 input terminals, wherein the second input end For inputting communication data, the first input is used to input the current maximum value or the current minimum value provided by the first register; 1 enable end for inputting the comparison result; and 1 output terminal for the enable end receiving
  • the comparison result is that the input communication data is greater than the current maximum value or less than the current minimum value, enabling the output of the current maximum value or the current minimum value input by the first
  • the output processing state machine comprises: a second reader for sequentially reading m cascaded data comparison units; and a counter for counting each data from the m cascaded data comparison units a number of times, when counting to m, a full signal is issued; a second monitor for monitoring the full signal, disabling the second reading unit; and a second output for sequentially outputting data to a queue
  • the queue is a first in first out queue.
  • the communication data is k bits, and all components in the data sorting device are components capable of processing k bits.
  • the first register and the second register are D flip-flops.
  • Figure 2 shows a circuit diagram of the data comparison unit of Figure 1, the data comparison unit consists of one greater than comparator 22, one selector (including two two-select multiplexers 24, 26) and two bit widths. It is a combination of k-bit registers (28, 29). The input data (V_in) greater than the bit width of the comparator is compared with the current maximum value (value).
  • the two-choice multiplexer selects one of the two inputs as the output according to the value of the selection signal, and outputs the input from the branch 1 (the first input terminal) if the value of the selection signal is 1, if the value of the selection signal is 0. Then the input from branch 0 (the second input) is output.
  • the register is used to store the result of each data comparison; the initial value of the register after power-on reset is 0; when the register enable signal (enable) is valid, the data on the register data input is saved to the register; when the register clears the signal The register is cleared when (clear) is active.
  • the two registers respectively store the current maximum value (value) and output to the value (v_out) of the next-stage data comparison unit. If the input data v_in is greater than the current maximum value, the value of the value register will be updated to the current input data when the enable signal is valid, and the value of the v_out register will be updated to the original maximum value. If the input data v_in is not greater than the current maximum value, the value of the value register will be unchanged when the enable signal is valid, and the value of the v_out register will be updated to the current input data.
  • the packet format of the input data packet according to an embodiment of the present invention is shown in the following table:
  • the packet parameter n is the number of input data; the packet format parameter I is the bit width of the parameter n.
  • the packet parameter m is the number of output results;
  • the packet format parameter J is the bit width of the parameter m.
  • the CPU is in the order of the number of the input packet from small to large.
  • the input processing state machine monitors the input FIFO, and generates a FIFO read signal when there is a data packet in the input FIFO; parses the packet parameters n and m from the first word of the data packet according to the determined packet format parameters I and J;
  • the parameter n value obtained from the input data packet determines the number of times the data is read, sequentially reads n data from the input FIFO and synchronously generates a register enable signal of the data comparison unit; reads n data and m clocks
  • the cycle sorting pipeline delays the current round of data processing and generates a sorting completion signal; waits for the output completion signal generated by the output processing state machine to complete the output of the data, and generates a register clearing signal of the data comparison unit after detecting the output completion signal and returns Idle state.
  • 3 shows a state transition diagram of an input processing state machine in accordance with an embodiment of the present invention, as follows:
  • S—IDLE Idle state.
  • the input processing state machine is in this state after power-on reset. In this state, the data presence signal ( s_exists ) of the input FIFO is monitored, and when the signal is active (high level), a FIFO read signal (s-read, active high) is generated and goes to the S_DECODE state.
  • S— DECODE Decode status.
  • the first word of the packet on the input FIFO data signal (s_data) is parsed to obtain the packet parameters n and m. If the parameter n or m is 0, no sorting is required, and the input processing state machine returns to the S_IDLE state. If the parameters n and m are both greater than 0, the data of the input FIFO is monitored (s_present). When the signal is valid (high level), a FIFO read signal (s-read, active high) is generated and transferred.
  • S_COMP Comparison status. In this state the input data into the count ⁇ 1, if the input data counter data- cnt is smaller than n, the monitoring of the presence signal FIFO input data (s_exists), as a FIFO read signal (s When this signal is active (high level) —read, active high). If the input data counter data_cnt is equal to ⁇ , it is transferred to the S_WAIT state.
  • S—WAIT Waiting state. In this state, first wait m clock cycles, ensure that the last input data reaches the m-th data comparison unit and complete the data comparison; then generate a sort completion signal (order_ finish), notify the output processing state machine to start outputting the result; The output completion signal (output_finish) generated by the processing state machine is monitored. When the signal is valid (high level), the register clear signal of the data comparison unit is generated and the S_IDLE state is returned. The output processing state machine monitors the sort completion signal, generates a FIFO write signal when the signal is valid and there is an idle position in the output FIFO, and stores the m maximum values stored in the current maximum value register of the m data comparison units from large to small. The order is sequentially written to the output FIFO, the first level of data ratio
  • M— WRITE Output status, in which the m maximum values stored in the current maximum value register of m data comparison units are sequentially written to the output FIFO in descending order. If the FIFO full signal of the output FIFO (m_ftill, active high) is invalid, that is, there is an idle position in the output FIFO, the current maximum value stored in each stage of the data comparison unit is output to the data input signal (m_data) of the output FIFO one by one.
  • the FIFO write signal (m_write, active high) of the output FIFO is synchronously generated, and the maximum value stored in the first-stage data comparison unit is output first.
  • an output completion signal ( output_fmish ) is generated and the M_IDLE state is returned.
  • the entire hardware sequencer implementation is shown in Figure 1.
  • the input data packets stored in the input FIFO are sequentially read under the control of the input processing state machine, and the packet parameters n and m are parsed from the first word of the data packet according to the determined packet format parameters I and J; Then, each data is sequentially read and input to the first-stage data comparison unit; each time one data is read from the input FIFO, the enable signal of each data comparison unit is valid once; the output of the first-stage data comparison unit is input to the second level.
  • the data comparison unit inputs the output of the second-stage data comparison unit to the third-stage data comparison unit, and so on, and the output of the m-1th-level data comparison unit is input to the m-th level data comparison unit; After the unit has also completed the comparison of all the data, the m maximum values stored in the data comparison units of each stage are written to the output FIFO under the control of the output processing state machine.
  • the input processing state machine returns to the idle state, and the output processing state machine returns to the idle state. Take the common peak search operation in wireless communication processing as an example.
  • the number of input data is at most
  • the data bit width is 16 bits; it is required to find up to 8 maximum peaks from the input data.
  • the hardware sequencing coprocessor implemented by the embodiment of the present invention implements input through
  • the FIFO and output FIFO are connected to the CPU.
  • the CPU writes the input data packet to the input FIFO according to the data packet format of Figure 2.
  • the implementation device completed according to the above design requirements can handle all cases where the number of input data is less than or equal to 256 and the number of output results is less than or equal to 8.
  • the actual number of input data is 199, and it is required to output 7 maximum peaks.
  • the working process of the entire hardware sequencing coprocessor implementation device can be derived.
  • the input processing state machine is idle after a power-on reset and monitors the input FIFO.
  • the output of the first-stage data comparison unit is input to the second-stage data comparison unit, the output of the second-stage data comparison unit is input to the third-stage data comparison unit, and so on, and the output of the sixth-stage data comparison unit is input to Level 7 data comparison unit; after the 7th stage data comparison unit also completes the comparison of all 199 data, the 7 maximum values stored in the 1st to 7th stage data comparison units are under the control of the output processing state machine Is written to the output FIFO. The input processing state machine returns to the idle state, and the output processing state returns to the idle state.
  • the above embodiments of the present invention are characterized by: 1.
  • the sorting operation is implemented by hardware.
  • each data comparison unit compares the input data of the unit, and the data comparison units of the pipelines operate simultaneously; all the input data can be sorted once by the pipeline once. operating. 3.
  • the implementation device according to the determined n and m values can process all cases where the number of input data is less than or equal to n and the number of output results is less than or equal to m.
  • the sorting operation is improved from software implementation to hardware implementation as compared with the prior art. Assuming that there are a total of n input data and m-level data comparison units, after n + m clock cycles, the m-level data comparison units from 1 to m store m maximum values arranged in descending order.
  • the device of the present invention can overcome the shortcoming that the number of clock cycles occupied by the software implementation of the sorting operation in the prior art is proportional to the factorial of n, and solves the problem that the sorting operation implemented by software in the prior art cannot meet the real-time signal processing pair.

Abstract

L'invention porte sur un dispositif de tri de données, comprenant : un automate de traitement d'entrée, pour traiter les n données mises en entrée; m unités de comparaison de données en cascade, dont chacune comprend un comparateur pour comparer les données mises en entrée avec les données les plus grandes actuelles ou les données les plus petites actuelles pour obtenir un résultat, un sélecteur pour délivrer les données les plus grandes d'entre les données de communication mises en entrée et les données les plus grandes actuelles, ou les données les plus petites d'entre les données de communication mises en entrée et les données les plus petites actuelles, à un premier registre et les données plus petites ou les données plus grandes à un second registre selon le résultat de comparaison, le premier registre servant à stocker les données plus grandes en tant que nouvelles données les plus grandes actuelles ou les données plus petites en tant que nouvelles données plus petites actuelles, et les délivrer au comparateur, et le second registre servant à stocker les données plus petites ou les données plus grandes devant être délivrées à l'unité de comparaison de données suivante; un automate de traitement de sortie, pour délivrer les données les plus grandes actuelles ou les données les plus petites actuelles dans les m unités de comparaison de données en cascade dans l'ordre. La vitesse de tri est améliorée.
PCT/CN2007/003883 2007-12-28 2007-12-28 Dispositif de tri de données pour traiter des données de communication WO2009082852A1 (fr)

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PCT/CN2007/003883 WO2009082852A1 (fr) 2007-12-28 2007-12-28 Dispositif de tri de données pour traiter des données de communication

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1105134A (zh) * 1993-07-13 1995-07-12 三菱电机株式会社 分类系统和方法
US5740459A (en) * 1992-10-07 1998-04-14 Motorola, Inc. Method and circuit for sorting data in a fuzzy inference data processing system
US20030123418A1 (en) * 2001-12-27 2003-07-03 Interdigital Technology Corporation Insertion sorter
CN1783760A (zh) * 2004-11-30 2006-06-07 中兴通讯股份有限公司 能量信号的峰值搜索和排序装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5740459A (en) * 1992-10-07 1998-04-14 Motorola, Inc. Method and circuit for sorting data in a fuzzy inference data processing system
CN1105134A (zh) * 1993-07-13 1995-07-12 三菱电机株式会社 分类系统和方法
US20030123418A1 (en) * 2001-12-27 2003-07-03 Interdigital Technology Corporation Insertion sorter
CN1783760A (zh) * 2004-11-30 2006-06-07 中兴通讯股份有限公司 能量信号的峰值搜索和排序装置

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