WO2009077311A4 - Kasumi algorithm implementation - Google Patents
Kasumi algorithm implementation Download PDFInfo
- Publication number
- WO2009077311A4 WO2009077311A4 PCT/EP2008/066475 EP2008066475W WO2009077311A4 WO 2009077311 A4 WO2009077311 A4 WO 2009077311A4 EP 2008066475 W EP2008066475 W EP 2008066475W WO 2009077311 A4 WO2009077311 A4 WO 2009077311A4
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- function
- bit
- output
- input
- bits
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
Abstract
There is disclosed an apparatus, and corresponding method, operable to perform an FI function of a Kasumi algorithm, including a reconfigurable processing stage, wherein in a first configuration the processing stage implements a first stage of the FI function and in a second configuration the processing stage implements a second stage of the FI function.
Claims
1. An apparatus, operable to perform an FI function of a Kasumi algorithm, including a reconfigurable processing stage, wherein in a first configuration • the processing stage implements a first stage of the PI function under a first processor instruction and in a second configuration the processing Btage implements a second stage of the PI function under a second processor instruction.
2. An apparatus according to claim 1 in which the first configuration is implemented in a first cycle of the FI function and the second configuration is implemented in a second cycle of the FI function,
3. An apparatus according to any one of claims 1 to 2 wherein the second configuration is chosen from one of two possible configurations .
4 , An apparatus according to any one of claims 1 to 3 in which the reconfigurable processing stage includes an S9 function and an S7 function.
5. An apparatus according to claim 4 in which the reconfigurable processing stage further includes first, second, third and fourth exclusive-OR functions.
6. An apparatus acαording to claim 5 in which in the first configuration ! a, the £37 function receives 7 bits of a 16 bit input to the FI function and generates a 7 bit S7 output; b. the S9 function receives 9 bits of the 16 bit input to the FI function and generates a 9 bit S9 output; c. the first exclusive-OR function receives as a first input the 9 bit S9 output and as a second input the 7 bit input to the S7 function, zero extended to 9 bits, and generates a 9 bit output; d, the second exclusive-OR function receives as a first input the 7 bit S7 output and as a second input 7 bits of a 16 bit key, and generates a 7 bit output; e. the third exclusive-OR function receives as a first input the 9 bit output of the first exclueive-OR
. function and as a second input 9 bits of the 16 bit key, and generates a 9 bit output of the first stage of the PI function; and f , the fourth exclusive-OR function receives as a first input the 7 bit output of the third excuaive-OR function and as a second input the 9 bit output of the first exclusive-OR function, truncated, and generates the 7 bit output of the first stage of the FI function.
7. An apparatus according to claim 6 in which in the second configuration: a. the S7 function receives the 7 bit output of the first stage and generates a further 7 bit S7 output; 29
b. the £59 function receives the 9 bit output of the first stage and generates a further 9 bit S9 output; σ, the first exclusive-OR function receives as a first input the further 9 bit S9 output and as a second input the 7 bit input to the Si function, zero extended to 9 bits, and generate.. 9 bits of a 16-bit output of the FI function; and d, the fourth exclusive-OR function receives as a first input the further 7 bit output of the S7 function and as a second input the 9 bit output of the first exclu3ive-0R function, truncated, and generates 7 bits of the 16-bit output of the FI function.
8.An apparatus according to claim 7, wherein the 7 bit output and the 9 bit output of the Fl function are swapped,
9,An apparatus according to claim 8 in which the functional stage is implemented in an integrated circuit, a conductive element associated with the 7 bit output being arranged to crossover a conductive element associated with the 9 bit output, to provide inputs to a subsequent stage.
10. An apparatus according to claim 6 in which in the second configuration i a. the S7 function receives the 7 bit output of the first stage and generates a further 7 bit S7 output; b. the £39 function receives the 9 bit output of the first stage and generates a further 9 bit Θ9 output; 30
c. the first exclusive-OR function receives as a first input the further 9 bit S9 output and as a second input the 7 bit input to the S7 function, zero extended to 9 bits, and generates 9 bits of a 16 bit output of the FI function,- and d, the third exdlusive-OR function receives as a first input the 9 bit output of the first excusive-OR function, truncated to 7 bits, and as a second input the further 7 bit S7 output, and generates 7 bits of the 16 bit output of the FI function.
11. An apparatus according to claim 9 in which the 7 bit and 9 bit outputg are not swapped.
12. An apparatus according to claim 11 in which the functional stage is implemented in an integrated circuit, a conductive element associated with the 7 bit output being arranged to not crossover a conductive element associated with the 9 bit output.
13. A method of controlling an FI function of a Kasumi algorithm, in a reconfigurable processing stage, comprising configuring the processing stage in a first configuration to implement a first stage of the PI function; and configuring the processing stage in a second configuration to implement a second stage of the FI function, 4, A method according to claim 13, further comprising 'the steps of generating a first process instruction to implement 31
the first configuration and generating a second processor instruction to implement the second configuration.
15. A method according to claim 13 or claim 14, further comprising the steps of, in a first processor cycle of the
Fi function, implementing the first configuration; and in a second processor cycle of the PI function, implementing the second configuration,
16. A method according to any one of claims 13 to 15 further comprising the step of selecting the second configuration from one of two possible configurations.
17. A method according to any one of claims 13 to 16 in which in the first configuration the processing stage is configured to: a. receive at an S7 function 7 bits of a 16 bit input to the FI function and generate a 7 bit S7 output; b. receive at an S9 function 9 bits of the 16 bit input to the FI function and generate a 9 bit S9 output; σ. receive as a first input at a first exclusive-OR function the 9 bit S9 output and as a second input the 7 bit input to the S7 function, zero extended to 9 bits, and generate a 9 bit output; d, receive as a first input at a second exclusive-OR function the 7 bit S7 output and as a second input 7 bits of a 16 bit key, and generate a 7 bit output; 32
e, receive as a first input to a third exclusive-OR function the 9 bit output of the first exclusive-OR function and as a second input 9 bits of the 16 bit key, and generate a 9 bit output of the first stage of the FI function; and f . receive as a first input at a fourth exclusive-OR gate the 7 bit output of the third excusive-OR function and as a second input the 9 bit output of the first exclusive-OR function, truncated, and generate the 7 bit output of the first stage of the FI function.
18. A method according to claim 17 in which in the second configuration the processing stage is configured to: a. receive at the S7 function the 7 bit output of the first stage and generate a further 7 bit S7 output; b. receive at the S9 function the 9 bit output of the first stage and generate a further 9 bit S9 output; c. receive as a first input at the first exclusive-OR function the further 9 bit S9 output and aa a second input the 7 bit input to the S7 function, zero extended to 9 bits, and generate 9 bits of a 16 -bit output of the FI function; and d. receive as a first input at the fourth exclusive-OR function the further 7 bit output of the S7 function and as a second input the 9 bit output of the first exclusive-OR function, truncated, and generate 7 bits of the 16-bit output of the FI function, 33
19. A method according to claim 17 in which in the second configuration the processing stage is configured to; a. receive at the S7 function the 7 bit output of the first stage and generates a further 7 bit S7 output; b. receive at the S9 function the 9 bit output of the first stage and generates a further 9 bit ≤9 output; c. receiving as a first input at the first exclusive-OR function the further 9 bit S9 output and. as a second input the 7 bit input to the S7 function/ zero extended to 9 bits, and generates 9 bits of a 16 bit output of the FI function; and d. receiving as a first input at the third exclusive-OR function the 9 bit output of the firat excusive-OR function, truncated to 7 bits, and as a second input the further 7 bit S7 output, and generates 7 bits of the 16 bit output of the FI function,
20. A computer program for implementing the method of any one of claims 13 to 19.
21. A computer program product for storing computer program code which, when run on a computer, implements the method of any one of claims 13 to 19.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1011024.5A GB2468457B (en) | 2007-12-14 | 2008-11-28 | Kasumi algorithm implementation |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0724438.7 | 2007-12-14 | ||
| GBGB0724438.7A GB0724438D0 (en) | 2007-12-14 | 2007-12-14 | Kasumi algorithm implementation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2009077311A1 WO2009077311A1 (en) | 2009-06-25 |
| WO2009077311A4 true WO2009077311A4 (en) | 2009-09-03 |
Family
ID=39048126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP2008/066475 WO2009077311A1 (en) | 2007-12-14 | 2008-11-28 | Kasumi algorithm implementation |
Country Status (3)
| Country | Link |
|---|---|
| GB (2) | GB0724438D0 (en) |
| TW (1) | TW200943885A (en) |
| WO (1) | WO2009077311A1 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7212631B2 (en) * | 2001-05-31 | 2007-05-01 | Qualcomm Incorporated | Apparatus and method for performing KASUMI ciphering |
| US7760874B2 (en) * | 2004-07-14 | 2010-07-20 | Broadcom Corporation | Method and system for implementing FI function in KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets |
-
2007
- 2007-12-14 GB GBGB0724438.7A patent/GB0724438D0/en not_active Ceased
-
2008
- 2008-11-26 TW TW097145690A patent/TW200943885A/en unknown
- 2008-11-28 GB GB1011024.5A patent/GB2468457B/en active Active
- 2008-11-28 WO PCT/EP2008/066475 patent/WO2009077311A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| GB201011024D0 (en) | 2010-08-18 |
| WO2009077311A1 (en) | 2009-06-25 |
| TW200943885A (en) | 2009-10-16 |
| GB2468457B (en) | 2012-05-30 |
| GB2468457A (en) | 2010-09-08 |
| GB0724438D0 (en) | 2008-01-30 |
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