WO2009069087A1 - Appareil et procédé pour décoder des codes de correction d'erreurs concaténés - Google Patents

Appareil et procédé pour décoder des codes de correction d'erreurs concaténés Download PDF

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Publication number
WO2009069087A1
WO2009069087A1 PCT/IB2008/054971 IB2008054971W WO2009069087A1 WO 2009069087 A1 WO2009069087 A1 WO 2009069087A1 IB 2008054971 W IB2008054971 W IB 2008054971W WO 2009069087 A1 WO2009069087 A1 WO 2009069087A1
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code
error correction
codeword
correction code
error
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PCT/IB2008/054971
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English (en)
Inventor
Jia Zhu
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Nxp B.V.
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Publication of WO2009069087A1 publication Critical patent/WO2009069087A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Definitions

  • the present invention relates generally to error correction of digital signals and in particular relates to correcting error by using error correction codes.
  • ECC Error correction codes
  • Block codes segment the information bits into multiple blocks of constant bit-length and independently encode the multiple blocks into codewords.
  • convolutional codes perform convolution operation over the information bits so that the coded bits are relevant to the fore-and-aft bits in a sequence.
  • each m-bit information symbol i.e., each m-bit string
  • n-bit symbol i.e., each m-bit string
  • m/n the code rate (n > m)
  • the transformation is a function of the last k information symbols, where k is the constraint length of the code.
  • Hamming codes Bose Ray-Chaudhuri Hocquenghem (BCH) codes, Reed-Solomon (RS) codes and Low-Density Parity-Check (LDPC) codes are representatives of the block codes family.
  • PCCC Parallel Concatenated Convolutional Codes
  • turbo codes use convolutional codes as their component codes.
  • Decoding algorithms for ECC have experienced an evolution from hard-decision decoding to soft-decision decoding. It has been shown that applications of soft-decision decoding algorithms to turbo codes and LDPC codes can perform error corrections approaching the Shannon limit very closely.
  • FIG. 1 illustrates a typical concatenated ECC receiver (100) for decoding a concatenated ECC encoded signal.
  • Encoded data (102) is input to an inner ECC decoder (104) which decodes the encoded signal to generate codewords.
  • the codewords are input to an optional de-interleaver (106) if the codewords are interleaved. Otherwise, the codewords are directly input to an outer ECC decoder (108) to generate decoded data (110).
  • an outer ECC decoder (108) One exemplary application of the concatenated ECC encoding method is the Digital
  • Video Broadcasting - Terrestrial (DVB-T) system which adopts convolutional codes as inner ECC codes to correct randomly distributed errors and RS codes as outer ECC codes to correct burst errors.
  • a large number of error cases can be handled by either of these two ECCs to maintain the BER at a very low level.
  • SNR signal to noise ratio
  • the outer ECC (108) actually is not necessary. Only in cases where the inner ECC decoder (104) cannot correct all the errors of the encoded signal (102) that the outer ECC decoder (108) is needed to further decode the codewords decoded by the inner ECC decoder (104).
  • the outer ECC decoder (108) In systems like DVB-T where convolutional codes are adopted as the inner ECC, one cannot judge whether the decoded inner codewords are correct or not since convolutional codes cannot be parity -checked block by block. Therefore, the outer ECC decoder (108) always perform decoding, even though it makes no difference most of the time (i.e., the decoded codewords by the inner ECC decoder (104) are error free most of the time).
  • ECCs like BCH and RS codes are normally favored as outer ECC in concatenated ECC systems due to their excellent burst error correction ability.
  • the decoded codeword can contain an error bit number exceeding the maximum error bit number the outer ECC decoder (108) can correct.
  • the decoding of the codeword by the outer ECC decoder (108) is unproductive and useless. Therefore, if one could determine from the decoding result of the inner ECC decoder (104) that the error bit number of the codeword is more than that the outer ECC decoder (108) can handle, it can be determined that it is not necessary to perform the outer ECC decoding.
  • the method comprises receiving a digital signal encoded with an inner error correction code and an outer error correction code, decoding the digital signal to generate a first codeword, generating a syndrome vector from the first codeword, and outputting a decoded result, wherein the decode result is determined from the syndrome vector and the first codeword.
  • the method can further comprise de-interleaving the first codeword prior to generating the syndrome vector from the first codeword.
  • the outputting a decoded result comprises outputting the first codeword as the decoded result when the syndrome vector is an all-zero vector and determining an error bit number from the syndrome vector when the syndrome vector is not an all-zero vector.
  • the inner error correction code can be block code which can be uniquely defined by its parity check matrix.
  • the inner error correction code can be one of Hamming code, BCH code, RS code, or LDPC code.
  • the outer error correction code can be one of block code, convolutional code, turbo code, algebraic code, or geometrical code.
  • the outer error correction code can be one of Hamming code, BCH code, RS code, or LDPC code.
  • the first error correction code can be configured to correct randomly distributed errors contained in the digital signal
  • the second error correction code can be configured to correct burst errors contained in the digital signal.
  • an apparatus for decoding a digital signal to correct error contained therein comprises an inner ECC decoder for decoding a digital signal encoded with an inner error correction code and an outer error correction code and generating a first codeword, and a control unit coupled to the inner ECC decoder and configured to generate a syndrome vector from the first codeword.
  • the control unit is configured to output a decoded result determined by the syndrome vector and the first codeword.
  • the apparatus can further comprise an outer ECC decoder coupled to the control unit and the inner ECC decoder, wherein the control unit is configured to output the first codeword as the decoded result when the syndrome vector is an all-zero vector and determine an error bit number from the syndrome vector when the syndrome vector is not an all-zero vector, wherein when the error bit number is larger than a threshold value, the control unit is configured to output the first codeword as the decoded result, and when the error bit number is equal to or less than the threshold value, the control unit is configured to input the first codeword to the outer ECC decoder which is configured to decode the first codeword to generate the decoded result.
  • the inner error correction code can be block code which can be uniquely defined by its parity matrix.
  • the inner error correction code can be one of Hamming code, BCH code, RS code, or LDPC code.
  • the outer error correction code can be one of block code, convolutional code, turbo code, algebraic code, or geometrical code.
  • the outer error correction code can be one of Hamming code, BCH code, RS code, or LDPC code.
  • the first error correction code can be configured to correct randomly distributed errors contained in the digital signal, and the second error correction code can be configured to correct burst errors contained in the digital signal.
  • the apparatus can further comprise a de-interleaver coupled between the first ECC decoder and the control unit for de-interleaving the first codeword.
  • FIG. 1 is a block diagram showing a typical ECC decoding scheme.
  • FIG. 2 is a block diagram showing a simplified concatenated ECC system.
  • FIG. 3 is a flowchart showing an exemplary embodiment of a method of decoding concatenated ECC signal.
  • FIG. 4 is a simplified block diagram showing an exemplary embodiment of a concatenated ECC receiver according to the present invention.
  • FIG. 4 is a simplified block diagram showing an exemplary embodiment of a concatenated ECC receiver according to the present invention.
  • a concatenated ECC decoder including an inner ECC decoder and an outer ECC decoder is provided.
  • the outer ECC decoder is bypassed.
  • the other ECC decoder is bypassed.
  • a parity -check matrix H of a linear block code C is a generator matrix of the dual of the code.
  • a codeword c is in C if and only if the matrix-vector product
  • Equation (1) shows an exemplary parity-check matrix of a block code.
  • the exemplary parity -check matrix H can be used in soft-decision decoding to detect error. Furthermore, the parity -check matrix H as shown by Equation (1) can be utilized in other ways in additional to soft-decision decoding application. According to classical coding theory, if a codeword could be correctly parity-checked by using the parity-check matrix H, it must be a valid codeword encoded from a generation matrix corresponding to the parity -check matrix H. In other words, when parity-check performed to a decoded codeword generates an all-zero syndrome vector, it indicates that the decoded codeword is a valid codeword, but not necessarily a correct decoded result.
  • FIG. 2 illustrates a concatenated ECC system (200).
  • the transmitted data (102) shown in FIG. 1 is encoded with an inner ECC concatenated with an outer ECC.
  • the transmitter (202) is configured to a suitable transmission power level to keep the SNR at a receiver (206) low enough to enable the inner ECC decoder (104) shown in FIG. 1 to successfully correct randomly distributed errors most of the time.
  • the outer ECC decoder (108) actually is not necessary to correct errors contained in the signal (102). Only when there are some burst errors that the inner ECC decoder (104) cannot correct, the outer ECC decoder (108) should be operated to correct errors not corrected by the inner ECC decoder (104).
  • a method of decoding concatenated ECC encoded data is presented to reduce or prevent unnecessary power consumption of the outer ECC decoder (108) and the decoding delay corresponding to unnecessary operations of the outer ECC decoder (108).
  • the method utilizes block codes as the inner ECC.
  • the outer ECC decoder (108) can be selectively bypassed if operations of the outer ECC decoder (108) is determined to be not necessary.
  • the inner ECC is selected to be block codes in a concatenated ECC system because the inner ECC must be block codes for syndrome computations performed on the inner ECC codeword to provide useful additional information to determine whether the operations of the outer ECC decoder (108) is necessary.
  • the decoded inner ECC codeword From the results of the syndrome computation of the inner ECC, it can be determined whether the decoded inner ECC codeword has at least a certain number of error bits. If the error bit number remaining in the decoded inner ECC codeword is more than the error bit number that the outer ECC decoder (108) can correct, further decoding by operating the outer ECC decoder (108) is unnecessary and can be omitted. The upper limit of the error bit number in a decoded inner ECC codeword can be estimated from the syndrome computation result.
  • the minimum error bit number in the decoded inner ECC codeword is [Ns/dv], where [x] indicates ceiling operation over x.
  • FIG. 3 is a flowchart illustrating a method of decoding concatenated ECC encoded data according to an embodiment of the present invention.
  • a signal encoded with an inner ECC and an outer ECC is first decoded in step (SlO) to generate a first codeword.
  • step (S20) a syndrome vector is determined from the first codeword and the corresponding parity-check matrix.
  • the syndrome vector is an all-zero vector
  • the first codeword is used as the decoded result in step (S30).
  • the syndrome vector is a non-zero vector
  • a bit error number is determined from the syndrome vector in step (S40). If the bit error number is determined to be larger than a threshold value in (S40), the first codeword is used as the decoded result in step (S30). If the bit error number is determined to be less than or equal to the threshold value in (S40), a second codeword is decoded from the first code word in step (S50) and used as the decoded result in step (S30).
  • FIG. 4 illustrates an exemplary embodiment according to the present invention.
  • a concatenated ECC receiver (300) is provided.
  • the concatenated ECC receiver (300) includes an inner ECC decoder (302), an optional de-interleaver (303) if the codewords are interleaved, and an outer ECC decoder (304).
  • the inner ECC decoder (302) is configured to decode an inner ECC code (e.g., LDPC codes)
  • the outer ECC decoder (304) is configured to decode an outer ECC code (e.g., RS codes).
  • a received signal (306) encoded with concatenated ECC is received and decoded by the inner ECC decoder (302).
  • the inner ECC decoder (302) decodes LDPC codes.
  • Syndrome decoding is performed over the decoded codeword to obtain a syndrome vector S, which has the same number of elements as the row number of the corresponding parity -check matrix.
  • Syndrome decoding can be implemented by methods generally known in the art. Case I
  • the syndrome vector S When the syndrome vector S is an all-zero vector, it indicates that the decoded codeword is a valid codeword of the corresponding LDPC codes.
  • the probability that decoding one codeword into a valid but incorrect codeword is negligible because the decoded BER of the LDPC codes is to the magnitude of 10 "4 which is the minimum normal working BER for LDPC codes for most systems.
  • the outer ECC decoder (304) can be bypassed by a control unit (308), and the information bits in the decoded codeword are taken out of sequence to the drain (310).
  • control unit (308) is only a representation of a control scheme to determine when the outer ECC decoder (304) should be bypassed and not operated.
  • control unit (308) can include multiple elements and coupled with the inner ECC decoder (302) and the outer ECC decoder (304) in other possible configurations.
  • the block codes implemented by the outer ECC decoder (304) are 255, 239 RS codes, which can correct any 8 byte errors in 255 bytes of data.
  • the outer ECC decoder (304) can also be bypassed and not operated by operations of the control unit (308), and the information bits in the decoded LDPC codeword are taken out of sequence to the drain (310).
  • ECC codes can be selected for the outer ECC such as, but not limited to, convolutional code, turbo code, algebraic code, or geometrical code.
  • the maximum error correction ability, code length of both inner and outer ECC, and dy of the inner ECC to calculate the upper limit of Ns for outer ECC decoding should all be considered according to the need of a particular application. Performance evaluation
  • the exemplary embodiment can reduce the power consumption and decoding delay of the concatenated ECC receiver (300) shown in FIG. 4.
  • the receiver (300) for concatenated ECC encoded signal normally works at a SNR that produces decoded BER of inner ECC to be less than 10 "4 and block error rate (BLER) to be less than 10 "2 . Therefore, over 99% of the time, the decoded inner ECC codewords are correct after inner ECC decoding, and the outer ECC decoder (304) can accordingly be bypassed to save a large amount of power.
  • the outer ECC decoder (304) can also be bypassed to save power until the SNR rises back into the normal range.
  • the decoding algorithm of the outer ECC is not simple and does require multiple signal processing operations.
  • outer ECC decoding adds delay to the total signal decoding time of the receiver (300) and increases the power consumption of the receiver (300).
  • the inner ECC decoder (302) and the outer ECC decoder (304) can be cascaded through a de-interleaver (not shown) which requires a lot of read/write operations on memory (not shown).
  • embodiments of the present invention are suitable to be applied in systems that have a strict requirement on transmission delay.
  • the reduction of decoding delay from bypassing the outer ECC decoder (304) helps to reduce the overall transmission delay, especially when the de-interleaving depth of the de-interleaver between the inner and outer ECCs is so large that causes a large amount of delay.

Abstract

L'invention porte sur un procédé de décodage d'un signal numérique pour corriger une erreur contenue dans celui-ci. Le procédé comprend la réception d'un signal numérique codé avec un premier code de correction d'erreur et un second code de correction d'erreur ; le décodage du signal numérique (S10) pour générer un premier mot de code ; la génération d'un vecteur de syndrome (S20) à partir du premier mot de code ; et l'émission d'un résultat décodé (S30), le résultat décodé étant déterminé à partir du vecteur de syndrome et du premier mot de code.
PCT/IB2008/054971 2007-11-29 2008-11-26 Appareil et procédé pour décoder des codes de correction d'erreurs concaténés WO2009069087A1 (fr)

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CN113364471A (zh) * 2020-03-05 2021-09-07 华为技术有限公司 一种译码系统、译码控制器及译码控制的方法
EP4261746A1 (fr) * 2022-04-15 2023-10-18 Nokia Solutions and Networks Oy Codage hiérarchique de canaux profonds

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CN113364471A (zh) * 2020-03-05 2021-09-07 华为技术有限公司 一种译码系统、译码控制器及译码控制的方法
EP4106207A4 (fr) * 2020-03-05 2023-03-29 Huawei Technologies Co., Ltd. Système de décodage, dispositif de commande de décodage et procédé de commande de décodage
US11764810B2 (en) 2020-03-05 2023-09-19 Huawei Technologies Co., Ltd. Decoding system, decoding controller, and decoding control method
CN113364471B (zh) * 2020-03-05 2024-04-12 华为技术有限公司 一种译码系统、译码控制器及译码控制的方法
EP4261746A1 (fr) * 2022-04-15 2023-10-18 Nokia Solutions and Networks Oy Codage hiérarchique de canaux profonds

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