WO2009063596A1 - 再構成可能回路、リセット方法、及び構成情報生成装置 - Google Patents

再構成可能回路、リセット方法、及び構成情報生成装置 Download PDF

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Publication number
WO2009063596A1
WO2009063596A1 PCT/JP2008/003121 JP2008003121W WO2009063596A1 WO 2009063596 A1 WO2009063596 A1 WO 2009063596A1 JP 2008003121 W JP2008003121 W JP 2008003121W WO 2009063596 A1 WO2009063596 A1 WO 2009063596A1
Authority
WO
WIPO (PCT)
Prior art keywords
reset
calculation
configuration information
generation device
information generation
Prior art date
Application number
PCT/JP2008/003121
Other languages
English (en)
French (fr)
Inventor
Takashi Morimoto
Shinichiro Nishioka
Koji Asai
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to US12/520,909 priority Critical patent/US20100023736A1/en
Priority to JP2009541027A priority patent/JPWO2009063596A1/ja
Publication of WO2009063596A1 publication Critical patent/WO2009063596A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17772—Structural details of configuration resources for powering on or off
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17756—Structural details of configuration resources for partial configuration or partial reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories

Abstract

　本発明は、複数の再構成セルを含み、各再構成セルに含まれる演算処理部の構成を変更する再構成可能回路であって、前記各再構成セルは、前記演算処理部による演算結果を保持する演算記憶部と、前記演算記憶部のリセットの要否を示すリセットフラグを保持しているフラグ保持部と、前記演算処理部の構成変更時に、前記フラグ保持部に保持されているフラグを用いて、前記演算記憶部のリセットを制御するリセット制御部とを備えることを特徴とする。
PCT/JP2008/003121 2007-11-12 2008-10-30 再構成可能回路、リセット方法、及び構成情報生成装置 WO2009063596A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/520,909 US20100023736A1 (en) 2007-11-12 2008-10-30 Reconfigurable circuit, reset method, and configuration information generation device
JP2009541027A JPWO2009063596A1 (ja) 2007-11-12 2008-10-30 再構成可能回路、リセット方法、及び構成情報生成装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-292829 2007-11-12
JP2007292829 2007-11-12

Publications (1)

Publication Number Publication Date
WO2009063596A1 true WO2009063596A1 (ja) 2009-05-22

Family

ID=40638451

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/003121 WO2009063596A1 (ja) 2007-11-12 2008-10-30 再構成可能回路、リセット方法、及び構成情報生成装置

Country Status (4)

Country Link
US (1) US20100023736A1 (ja)
JP (1) JPWO2009063596A1 (ja)
CN (1) CN101578768A (ja)
WO (1) WO2009063596A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9075669B2 (en) 2012-03-16 2015-07-07 Nec Corporation Time series data processing device, time series data processing method and time series data processing program storage medium

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9116751B2 (en) * 2011-02-08 2015-08-25 Canon Kabushiki Kaisha Reconfigurable device, processing assignment method, processing arrangement method, information processing apparatus, and control method therefor
US8572538B2 (en) * 2011-07-01 2013-10-29 Altera Corporation Reconfigurable logic block
JP6751057B2 (ja) 2017-07-04 2020-09-02 日立オートモティブシステムズ株式会社 電子制御システム
JP6726648B2 (ja) * 2017-08-28 2020-07-22 日立オートモティブシステムズ株式会社 電子制御装置、回路の再構成方法
CN110826705B (zh) * 2018-08-09 2022-08-19 上海寒武纪信息科技有限公司 运算方法、装置及相关产品

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH104345A (ja) * 1996-06-18 1998-01-06 Hitachi Ltd フィールドプログラマブルゲートアレイ
JP2005510901A (ja) * 2001-10-29 2005-04-21 シーメンス　アクチエンゲゼルシヤフト 再構成可能なディジタル論理ユニット
JP2005165961A (ja) * 2003-12-05 2005-06-23 Matsushita Electric Ind Co Ltd 動的再構成論理回路装置、割込制御方法、及び、半導体集積回路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001202236A (ja) * 2000-01-20 2001-07-27 Fuji Xerox Co Ltd プログラマブル論理回路装置によるデータ処理方法、プログラマブル論理回路装置、情報処理システム、プログラマブル論理回路装置への回路再構成方法
JP5096923B2 (ja) * 2005-11-25 2012-12-12 パナソニック株式会社 動的再構成論理回路を有するマルチスレッドプロセッサ
JP4490392B2 (ja) * 2006-05-30 2010-06-23 富士通マイクロエレクトロニクス株式会社 初期化回路を自動構築するリコンフィグ可能な集積回路装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH104345A (ja) * 1996-06-18 1998-01-06 Hitachi Ltd フィールドプログラマブルゲートアレイ
JP2005510901A (ja) * 2001-10-29 2005-04-21 シーメンス　アクチエンゲゼルシヤフト 再構成可能なディジタル論理ユニット
JP2005165961A (ja) * 2003-12-05 2005-06-23 Matsushita Electric Ind Co Ltd 動的再構成論理回路装置、割込制御方法、及び、半導体集積回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9075669B2 (en) 2012-03-16 2015-07-07 Nec Corporation Time series data processing device, time series data processing method and time series data processing program storage medium

Also Published As

Publication number Publication date
JPWO2009063596A1 (ja) 2011-03-31
US20100023736A1 (en) 2010-01-28
CN101578768A (zh) 2009-11-11

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