WO2009063535A1 - バイアス回路、及びバイアス回路に対する制御方法 - Google Patents

バイアス回路、及びバイアス回路に対する制御方法 Download PDF

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Publication number
WO2009063535A1
WO2009063535A1 PCT/JP2007/001247 JP2007001247W WO2009063535A1 WO 2009063535 A1 WO2009063535 A1 WO 2009063535A1 JP 2007001247 W JP2007001247 W JP 2007001247W WO 2009063535 A1 WO2009063535 A1 WO 2009063535A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
bias circuit
gate
transistors
gate width
Prior art date
Application number
PCT/JP2007/001247
Other languages
English (en)
French (fr)
Inventor
Tomoyuki Arai
Masahiro Kudo
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to EP07828024.5A priority Critical patent/EP2216902B1/en
Priority to PCT/JP2007/001247 priority patent/WO2009063535A1/ja
Priority to JP2009540978A priority patent/JP5146460B2/ja
Publication of WO2009063535A1 publication Critical patent/WO2009063535A1/ja
Priority to US12/770,841 priority patent/US7920028B2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/108—A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/18—Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/456—A scaled replica of a transistor being present in an amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

　非線形増幅回路に対してバイアス電圧を与えるバイアス回路において、定電流源と、第１，第２，第３，及び第４のトランジスタを備え、前記第１のトランジスタと前記第２のトランジスタとによりカレントミラー回路を構成し、前記第３のトランジスタのドレイン及びゲートと前記第４のトランジスタのゲートとが接続され、前記第１のトランジスタと前記第３のトランジスタとが縦列に接続され、前記第２のトランジスタと前記第４のトランジスタとが縦列に接続され、前記第２のトランジスタのドレインから前記バイアス電圧が出力されるように構成し、　さらに、前記第１及び第２のトランジスタのゲート長及びゲート幅は同じであり、前記第１から第４のトランジスタのゲート長は同じであり、前記第１のトランジスタのゲート幅に対する前記第３のトランジスタのゲート幅の比をｋ３、前記第１のトランジスタのゲート幅に対する前記第４のトランジスタのゲート幅の比をｋ４とした場合、ｋ４ －０．５―ｋ３ －０．５が略１になるように、前記第１，第２，第３，第４の各トランジスタのゲート長及びゲート幅が構成される。
PCT/JP2007/001247 2007-11-16 2007-11-16 バイアス回路、及びバイアス回路に対する制御方法 WO2009063535A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP07828024.5A EP2216902B1 (en) 2007-11-16 2007-11-16 Bias circuit and method for controlling bias circuit
PCT/JP2007/001247 WO2009063535A1 (ja) 2007-11-16 2007-11-16 バイアス回路、及びバイアス回路に対する制御方法
JP2009540978A JP5146460B2 (ja) 2007-11-16 2007-11-16 バイアス回路、及びバイアス回路に対する制御方法
US12/770,841 US7920028B2 (en) 2007-11-16 2010-04-30 Bias circuit and control method for bias circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/001247 WO2009063535A1 (ja) 2007-11-16 2007-11-16 バイアス回路、及びバイアス回路に対する制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/770,841 Continuation US7920028B2 (en) 2007-11-16 2010-04-30 Bias circuit and control method for bias circuit

Publications (1)

Publication Number Publication Date
WO2009063535A1 true WO2009063535A1 (ja) 2009-05-22

Family

ID=40638391

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/001247 WO2009063535A1 (ja) 2007-11-16 2007-11-16 バイアス回路、及びバイアス回路に対する制御方法

Country Status (4)

Country Link
US (1) US7920028B2 (ja)
EP (1) EP2216902B1 (ja)
JP (1) JP5146460B2 (ja)
WO (1) WO2009063535A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT201700054686A1 (it) * 2017-05-19 2018-11-19 St Microelectronics Srl Circuito ad elevato swing di ingresso, dispositivo e procedimento corrispondenti
TWI716980B (zh) * 2018-08-28 2021-01-21 美商高效電源轉換公司 使用具回授之主動前置驅動器的GaN驅動器

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0348506A (ja) * 1989-04-19 1991-03-01 Nec Corp 電流可変回路
JPH0613820A (ja) * 1992-03-18 1994-01-21 Natl Semiconductor Corp <Ns> エンハンスメント／デプリーション・モード・カスコード電流ミラー
JPH06104762A (ja) * 1992-09-16 1994-04-15 Fujitsu Ltd カレントミラー回路
JPH09148853A (ja) 1995-11-17 1997-06-06 Fujitsu Ltd 電流出力回路
JPH11234060A (ja) 1998-02-18 1999-08-27 Fujitsu Ltd カレントミラー回路および該カレントミラー回路を有する半導体集積回路
JP2000151310A (ja) * 1998-08-31 2000-05-30 Hitachi Ltd 半導体増幅回路および無線通信装置
WO2001008299A1 (fr) 1999-07-23 2001-02-01 Fujitsu Limited Circuit miroir de courant basse tension
JP2005229268A (ja) * 2004-02-12 2005-08-25 Renesas Technology Corp 高周波電力増幅回路および無線通信システム

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3278598B2 (ja) * 1997-12-18 2002-04-30 富士通テン株式会社 Ｂ級ｍｏｓオペアンプ
US6172567B1 (en) * 1998-08-31 2001-01-09 Hitachi, Ltd. Radio communication apparatus and radio frequency power amplifier
US6791418B2 (en) * 2002-10-02 2004-09-14 Koninklijke Philips Electronics N.V. Capacitor coupled dynamic bias boosting circuit for a power amplifier
AU2003276645A1 (en) * 2002-12-09 2004-06-30 Koninklijke Philips Electronics N.V. Amplifier circuit having an extended wilson current-mirror self-bias boosting circuit
JP4026603B2 (ja) * 2004-02-16 2007-12-26 ソニー株式会社 バイアス電圧供給回路および高周波増幅回路
US7639081B2 (en) * 2007-02-06 2009-12-29 Texas Instuments Incorporated Biasing scheme for low-voltage MOS cascode current mirrors

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0348506A (ja) * 1989-04-19 1991-03-01 Nec Corp 電流可変回路
JPH0613820A (ja) * 1992-03-18 1994-01-21 Natl Semiconductor Corp <Ns> エンハンスメント／デプリーション・モード・カスコード電流ミラー
JPH06104762A (ja) * 1992-09-16 1994-04-15 Fujitsu Ltd カレントミラー回路
JPH09148853A (ja) 1995-11-17 1997-06-06 Fujitsu Ltd 電流出力回路
JPH11234060A (ja) 1998-02-18 1999-08-27 Fujitsu Ltd カレントミラー回路および該カレントミラー回路を有する半導体集積回路
JP2000151310A (ja) * 1998-08-31 2000-05-30 Hitachi Ltd 半導体増幅回路および無線通信装置
WO2001008299A1 (fr) 1999-07-23 2001-02-01 Fujitsu Limited Circuit miroir de courant basse tension
JP2005229268A (ja) * 2004-02-12 2005-08-25 Renesas Technology Corp 高周波電力増幅回路および無線通信システム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2216902A4

Also Published As

Publication number Publication date
EP2216902A4 (en) 2014-03-26
EP2216902A1 (en) 2010-08-11
JP5146460B2 (ja) 2013-02-20
JPWO2009063535A1 (ja) 2011-03-24
EP2216902B1 (en) 2017-08-30
US7920028B2 (en) 2011-04-05
US20100207692A1 (en) 2010-08-19

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