WO2009060260A1

WO2009060260A1 - Data processing arrangement, pipeline stage and method

Info

Publication number: WO2009060260A1
Application number: PCT/IB2007/054496
Authority: WO
Inventors: Adrianus Marinus Gerardus Peeters; Mark De Wit
Original assignee: Koninklijke Philips Electronics, N.V.; U.S. Philips Corporation
Priority date: 2007-11-06
Filing date: 2007-11-06
Publication date: 2009-05-14
Also published as: TW200923773A

Abstract

The asynchronous pipeline stage (20) comprises a data input (22) arranged for being coupled to a data providing environment (41) and a data output (24), arranged for being coupled to a data receiving environment (43). A controllable data retaining element (26) is coupled to the data input and the data output. The asynchronous pipeline stage further has a first handshake port (31) for exchanging handshake signals (ackN+1, reqiN) with the data providing environment and a second handshake port (32) for exchanging handshake signals (ackiv, reqN+1) with the data receiving environment. The pipeline stage (20) has a reset input (33) for receiving a reset signal (reset). The pipeline stage (20) assumes an initial state after receiving an asserted reset signal, and activates a handshake signal (reqN+1) at its second handshake port (32) after the reset signal has been de-asserted.

Description

Data processing arrangement, pipeline stage and method

FIELD OF THE INVENTION

The invention relates to a pipeline stage. The invention further relates to a data processing arrangement. The invention still further relates to a method for operating a pipeline stage.

BACKGROUND OF THE INVENTION

For some time the performance of synchronous designs has shown a dramatical improvement thanks to the use of global clocks to synchronize the switching activity of these designs. Unfortunately, the global synchronous approach has major difficulties. One of these difficulties is that circuitry has to operate constantly at a frequency determined by the longest path in the combinational logic even it is not necessary to do so. Furthermore, registers are triggered by the clock at each cycle, and subsequently dissipate energy whether the state has changed or not. It becomes increasingly difficult to synchronize the numerous clocked blocks in a large design due to the growing dominance of interconnect delays. Another problem is that the constant switching of the clock can cause surges in power-supply noise and electromagnetic emissions. Designers are exploring the paradigm of clockless design to overcome these problems. When compared to their synchronous counterparts, clockless designs have inherent advantages such as lower emissions of electromagnetic noise. The absence of clock distribution problems and of clock skew. Furthermore asynchronous circuitry is more robust to environmental variations and fabrication faults, and provides for a better modularity and better security.

An example of such asynchronous circuitry is described by Montek Singh and Steven M. Nowick in "MOUSETRAP: Ultra-high-speed transition-signaling asynchronous pipelines", Proc. International Conf. Computer Design (ICCD), pages 9-17, November 2001. A FIFO stage presents the basic idea of the Mousetrap circuit. The read and write interface of such a stage consist of a two-phase single rail handshake channel. Internally, the stage has standard level-sensitive latches in the datapath. The control circuit is implemented using an additional latch and an exclusive-nor gate. The control circuit for the latches in the data-path combines a transition (two-phase handshake) interface with level- sensitive (four-phase) internal operation for the latches.

A Mousetrap stage has a passive handshake interface, consisting of request signal ReqN and acknowledge signal AckN-i, via which data is written into the latches, and an active output handshake interface, consisting of request Req_N+i and acknowledge signal AckN, via which data is read from the latches.

According to the publication referred to above 'Initially, when the pipeline is empty, all its latches are transparent, and all the Req and Ack signals are low'. It is not addressed how this initial state is achieved. It is a disadvantage of the known circuit that it is not suitable for application in pipelined microprocessors.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an asynchronous digital pipeline stage that is suitable for such applications.

This object is achieved by the pipeline stage of claim 1 and the method of claim 5. It was recognized by the inventor that the known pipeline stage has the restriction that it needs to start empty. I.e. the known pipeline stage first needs to receive an input before it produces an output. This makes these circuits suited only for pipeline circuits where data flows in only one (forward) direction.

The asynchronous digital pipeline stage according to the invention is allowed to start with an output handshake, rather than with an input handshake. This enlarges the application domain of these circuits from simple data-processing blocks to pipelined microprocessors. The asynchronous digital pipeline circuit according to the invention is for example suitable for application in an asynchronous data processing arrangement as described in claim 5.

Several options are possible for the implementation of the pipeline stages. The data retaining element may be an edge-triggerable device, such as a flip-flop. The embodiment of claim 2 is however preferred, as the latch, which is a level triggerable device, allows for a faster operation, and requires less components.

Likewise various alternatives are possible for the handshake signaling between subsequent pipeline stages and/or between a pipeline stage and the environment. Options are for example a transition (two-phase handshake) or a level (four-phase handshake). The two- phase hand-shake as in the pipeline stage claimed in claim 3 is preferred, as this allows for the most efficient communication between subsequent devices.

Various wiring schemes may be used. E.g. a single wire scheme, where the handshake signals are exchanged by a pull-up/pull-down mechanism. Alternatively separate wires may be used to communicate a request and an acknowledge signal. A further alternative is to communicate each of the handshake signals via a dual rail, i.e. an additional rail for the inverted value of the handshake signal.

It may be indicated in various way that a signal is asserted or de-asserted. E.g. an asserted signal may be indicated by a logical high value or a logical low value and correspond to a low or a high physical signal value e.g. a current or voltage. The status asserted or de-asserted may alternatively be indicated by a combination of signals, e.g. via a dual rail. Instead of a value, a transition of the signal may indicate assertion of a signal.

BRIEF DESCRIPTION OF THE DRAWINGS These and other aspects are described in more detail with reference to the drawing. Therein, Fig. 1 shows a pipeline stage according to the prior art. Fig. 2 shows a pipeline stage according to the invention, Fig. 2A shows a part of an alternative embodiment of the pipeline stage according to the invention, Fig. 3 shows a data processing arrangement comprising a pipeline stage according to the invention,

Fig. 4 shows a first part of the data processing arrangement of Fig. 3 in more detail,

Fig. 5 shows a second part of the data processing arrangement of Fig. 3 in more detail,

Fig. 6 shows a third part of the data processing arrangement of Fig. 3 in more detail.

DETAILED DESCRIPTION OF AN EMBODIMENT Fig. 1 shows a mousetrap pipeline stage 10 as described in the above- mentioned article of Singh et all. The stage comprises a latch 11 that is controlled by an XNOR-gate 12. The latch contra llab Iy provides output data Dout, dependent on the input data Din and a latch enable signal en. According to the cited article it is assumed that initially all handshake signals req_N, req_N+i,ack_N_i,ack_N are low. Accordingly, the enable signal en is high, so that the latch is in a transparent state where the output data signal Dout follows the input data signal Din, and the output request signal req_N+i follows the input request signal req_N.

A write cycle, the first cycle of operation, is initiated by toggling signal req_N, thus indicating the validity of new data on Din. This leads, via the transparent control latch, to toggling of output signal ackN-i, which completes the write handshake. In parallel, Din will also pass through the transparent latch 11 to Dout, so that the output data is also updated. As a third parallel activity during a write cycle, the enable signal (en) of the latch 11 is toggled via the XNOR gate, thus making the latch 11 opaque, and keeping the new output data signal D_out stable.

A read cycle is initiated directly by the write cycle. The toggling of output req_N+i is caused by the toggling of the input req_N while the control latch 11 is transparent. This toggling of output req_N+i indicates to the output side that the output data D_out is valid (and can be interpreted/latched by the receiver. The receiver will then at some point toggle the ack_N signal, thereby indicating that the data has been received. The completion of a read cycle leads to the enable (en) signal going high again, which makes the control latch transparent, thus allowing a write action to complete (once the req_N signal toggles again).

The latch cycle is part of both the read and the write cycle. Initially, the enable signal en is high, which makes the control latch transparent. When a write signal starts (by toggling of the req_N signal), the enable signal en goes low, thereby making the latch opaque. As soon as the read cycle completes, the enable signal en switches back to high, and makes the control latch transparent again.

Fig. 2 shows an embodiment of an asynchronous digital pipeline stage according to the invention. The pipeline stage 20 comprises a data input 22 arranged for being coupled to a first environment 41. The first environment 41 may be a further pipeline stage, for example of the same type, but may alternatively be another stage. The pipeline stage 20 further comprises a data output 24 arranged for being coupled to a second environment 43. Analogously, the second environment 43 may be a further pipeline stage, for example of the same type, but may alternatively be another stage. A controllable data retaining element 26 is coupled to the data input 22 and the data output 24. The pipeline stage has a first handshake port 31 for exchanging handshake signals ack_N-i, req_N with the first environment 41, and a second handshake port 32 for exchanging handshake signals ack_N, req_N+i with the second environment 43. The pipeline stage 20 has a reset input for receiving a reset signals reset and a further reset input for receiving a further reset signal reset'. The reset' signal must be de- asserted after the de-assertion of the reset signal has propagated through the first logic element (36) and the second logic element (37). This behavior can be implemented by using an additional delay element DL shown in Fig. 2A, which provides the signal reset' as a delayed version of the reset signal.

In the embodiment shown, the pipeline stage 20 has a latch 26 as a controllable data retaining element, that is controlled by a latch controller 36 of a control module 30. The latch 26 has an enable input 28. The control module 30 is coupled to the first handshake port 31, to the second handshake port 32 and to the reset input 33. The control module 30 has an enable output 34 for providing an enable signal en to the enable input 28 of the latch 26. The latch 26 has an enabled state if the enable signal is asserted, and a disabled state if said signal is de-asserted. In the enabled state the latch passes data from the data input 22 to the data output 24, and in the disabled state the latch retains the data at its data output 24.

In the embodiment shown the control module 30 has a further latch 35, a first logic element 36 and a second logic element 37. The handshake ports 31, 32 each comprise a request terminal 31b, 32b and an acknowledge terminal 31a, 32a. The first logic element 36 is coupled to the acknowledge terminal 32a and the request terminal 32b of the second handshake port 32. The first logic element 36 provides an enable signal en at an output port 36a. It toggles the value of the enable signal en if a signal transition occurs at one of the terminals 32a, 32b of the second handshake port.

The further latch 35 is coupled to the request terminal 31b of the first handshake port 31, and to the reset input 33. The further latch has a done output 35a for providing a done signal. The further latch 35 has an enabled state if the enable signal is asserted, and a disabled state if said signal is de-asserted. In the enabled state the further latch passes a value at the request terminal 3 Ib of the first handshake port 31 as the value of the done signal to the done output 35 a, and in the disabled state the further latch 35 retains the value at its done output. The further latch 35 de-asserts the done signal upon receipt of an asserted reset signal.

The second logic element 37 has a first input coupled to the reset input 33 and a second input coupled to the done output 35 a, and provides a request signal reqN+1 to the request terminal 32b of the second handshake port 32. The second logic element 37 is arranged for asserting the request signal at the second handshake port 32 upon de-assertion of the reset signal and for further transmitting the done signal as the request signal

at said request terminal 32b after the reset signal is de-asserted.

The asynchronous digital pipeline stage shown in Fig. 2 operates as follows. When the reset signal reset is asserted (logical 1 in this embodiment), it resets the further latch 35 to an initial state. In said initial state the output value of the further latch is "0". On its turn this forces the handshake signal reqN₊i provided by the second logical circuit to the output 32b to signal value "0". Provided that the handshake signal ackiv is reset to "0" by the data receiving environment the first logical element 36 asserts the enable signal. When subsequently the reset signal reset is made low, thus activating the circuit, the second logical circuit 37 will toggle the signal req_N+i, leading to a request event to the data receiving environment 43. This toggling of the signal req_N+i causes the enable signal toggling to opaque mode, thus starting an output cycle following the original Mousetrap protocol. It is noted that other implementations are also possible, for example by choosing an other polarity of the reset signal, or by applying the reset signal at different locations in the circuit, e.g. at the req_N+i and the enable signal.

Fig. 2A shows an alternative embodiment of a part of second logical element 37. In said embodiment the second logical element 37 comprises a direction control input 373 for receiving a direction control signal dir. A multiplexer 372 either transfers the signal NOR (reset, done) provided by logical element 371 or the signal done as the output signal reqN₊i, depending on the value of the direction control signal dir. This enables the pipeline stage in the initial state either to be triggered by a handshake signal (ack_N, reqiv) received at its second handshake port (32) or at its first handshake port (31) depending on a value of the direction control signal (dir) during assertion of the reset signal (reset).

Fig. 3 shows an example of an asynchronous data processing arrangement comprising a pipeline stage 20 according to the invention. The data processing arrangement shown therein comprises a join stage 50, a data processing stage 60, and a fork stage 70. The join stage 50 comprises a first data input 51 arranged for receiving data Data in from a first environment 42 under control of a first handshake sequence reqi_n, acki_n, and a second data input 52 for receiving data from the data output 24 of the pipeline stage 20, under control of a second handshake sequence ack_N,

exchanged via the second handshake port 32 of the pipeline stage 20. The join stage synchronizes two handshake channels (the input from the environment and the output of the backward stage) and sends their values as separate parts of the data path to the 'Add' stage. The join stage 50 combines and synchronizes the data streams at its input to provide a combined data stream to the data processing stage 60. The data processing stage 60, comprises a data input 61 for receiving the data from the join stage 50 under control of a third handshake sequence and a data output 62 for providing data to the fork stage 70 under control of a fourth handshake sequence. The data processing stage 60 may for example perform an arithmetical operation at the data provided by the joins stage, such as an addition or a multiplication. In the embodiment shown the data processing arrangement is an accumulator. The fork stage 70 provides output data Data out to a second environment 44 under control of a fourth handshake sequence and to the input of the pipeline stage 22 under control of a fifth handshake sequence req_N, ack^-i via the first handshake port 31 of the pipeline stage 20. Each time a new value is communicated to the data processing arrangement by the environment 42, the accumulator is incremented with this value and the result is sent to the environment 44. This behavior could not have been implemented using a standard pipeline with only forward stages.

An example of the join stage 50 is shown in Fig. 4. Parts therein corresponding to those shown in Fig. 2 have a reference number that is 500 higher. In the join stage shown in Fig. 5 the request terminal of the input handshake port is replaced by a first and a second request terminal for receiving an input request signal reqi_n(l), reqi_n(2). The request terminals are coupled to a Muller C-element, which provides a combined request event reqc each time an input request event has occurred at each of the request terminals. Acknowledge signals acki_n(l) and acki_n(2) in response to said combined request are signaled both to the source of the request reqi_n(l) at the first terminal and the source of the request reqin(2) at the second request terminal. The data received at the input data channels 522a,b , for example 32 bits each, is provided to separate parts of a wide output data channel 524, having a width of for example 64 bits. An example of the data processing stage 60 is shown in Fig. 5. Parts therein corresponding to those shown in Fig. 2 have a reference number that is 600 higher. In the data processing stage 60 shown therein the output of the latch 626 is coupled to a data processing element, here an adder, which calculates the sum of the input values provided via the separate parts of the data channel coupled to output 624. The control module 30 comprises an additional delay element 639 which provides a delayed version of the done signal as the request signal req_out- The done signal is delayed by a delay time at least equal to the processing time required by the data processing element 628.

An example of the fork stage 70 is shown in Fig. 6. Parts therein corresponding to those shown in Fig. 2 have a reference number that is 700 higher. In the fork stage shown in Fig. 6, the output data Data out is forked to a first and a second destination. The acknowledge terminal of the input handshake port is replaced by a first and a second request terminal for receiving a first and a second output acknowledge signal ackout(l), ack_Out(2) from said destinations. The request terminals are coupled to a Muller C- element, which provides a combined acknowledge event ackc each time an input request event has occurred at each of the acknowledge terminals. Request signals req_out(l) and req_out(2) are signaled both to the source of the output acknowledge signal ack_out(l) and to the source of the output acknowledge signal ack_out(2).

It is remarked that the scope of protection of the invention is not restricted to the embodiments described herein. Parts of the system may implemented in hardware, software or a combination thereof. Neither is the scope of protection of the invention restricted by the reference numerals in the claims. The word 'comprising' does not exclude other parts than those mentioned in a claim. The word 'a(n)' preceding an element does not exclude a plurality of those elements. Means forming part of the invention may both be implemented in the form of dedicated hardware or in the form of a programmed general purpose processor. The invention resides in each new feature or combination of features.

Claims

CLAIMS:

1. Asynchronous pipeline stage (20) comprising: a data input (22) arranged for being coupled to a data providing environment

(41), a data output (24), arranged for being coupled to a data receiving environment (43), a controllable data retaining element (26) coupled to the data input and the data output, a first handshake port (31) for exchanging handshake signals (ack_N-χ, reqiv) with the data providing environment, - a second handshake port (32) for exchanging handshake signals (ackiv, req_N+i) with the data receiving environment, the pipeline stage (20) having a reset input (33) for receiving a reset signal (reset), which pipeline stage (20) assumes an initial state after receiving an asserted reset signal, and activates a handshake signal (req_N+i) at its second handshake port (32) after the reset signal has been de-asserted.

2. Asynchronous digital pipeline according to claim 1, wherein the pipeline stage has a one or more latches (26) as controllable data retaining elements, the latches being controllable by a latch controller (36) of a control module 30, the latches (26) having an enable input (28), the control module (36) being coupled to the first (31) and the second handshake port (32) and the reset input (33), wherein the latch controller (36) has an enable output (34) for providing an enable signal (en) to the enable input of the latches, the latches (26) having an enabled state if the enable signal is asserted, and a disabled state if said signal is de-asserted, in which enabled state the latches pass data from the data input (22) to the data output (24), and in which disabled state the latches retains the data at their data output (24).

3. Asynchronous digital pipeline stage according to claim 2, wherein the control module (30) has a further latch (35), a first logic element (36) and a second logic element (37), and wherein said handshake ports (31, 32) each comprise a request terminal (31b, 32b) and an acknowledge terminal (31a, 32a), the first logic element (36) being coupled to the acknowledge terminal (32a) and the request terminal (32b) of the second handshake port (32), and having an output (36a) for providing the enable signal (en), the first logic element toggling the value of the enable signal if a signal transition occurs at one of the terminals of the second handshake port, wherein the further latch (35) is coupled to the request terminal (3 Ib) of the first handshake port (31), and coupled to the reset input (33), and has a done output (35a) for providing a done signal, the further latch (35) having an enabled state if the enable signal is asserted, and a disabled state if said signal is de-asserted, in which enabled state the further latch passes a value at the request terminal (3 Ib) of the first handshake port (31) as the value of the done signal to the done output (35a), and in which disabled state the further latch (35) retains the value at its done output, the further latch (35) de-asserting the done signal upon receipt of an asserted reset signal, wherein the second logic element (37) has a first input coupled to the reset input (33) and a second input coupled to the done output (35a), and provides a request signal (reqN+1) to the request terminal (32b) of the second handshake port (32), the second logic element (37) being arranged for asserting the request signal at the second handshake port (32) upon de-assertion of the reset signal and for further transmitting the done signal as the request signal (reqN+1) at said request terminal (32b) after the reset signal is de-asserted.

4. Asynchronous digital pipeline stage according to claim 1, further having a direction control input (373) for receiving a direction control signal (dir), wherein the pipeline stage in said initial state either is capable of being triggered by a handshake signal (ackiv, reqiy) received at its second handshake port (32) or at its first handshake port (31) depending on a value of the direction control signal (dir) during assertion of the reset signal (reset).

5. Asynchronous data processing arrangement, comprising a pipeline stage (20) according to claim 1, a join stage (50), an data processing stage (60), and a fork stage (70), wherein the join stage (50) comprises a first data input (51) arranged for receiving data (Data in) from a first environment (42) under control of a first handshake sequence (reqm, acki_n), and a second data input (52) for receiving data from the data output (24) of the pipeline stage (20), under control of a second handshake sequence (ack_N, req_N+i) exchanged via the second handshake port (32) of the pipeline stage (20), wherein the data processing stage (60) comprises a data input (61) for receiving data from the join stage (50) under control of a third handshake sequence and a data output (62) for providing data to the fork stage (70) under control of a fourth handshake sequence, wherein the fork stage (70) provides output data (Data out) to a second environment (44) under control of a fourth handshake sequence and to the input of the pipeline stage (22) under control of a fifth handshake sequence (req_N, ack^-i) via the first handshake port (31) of the pipeline stage.

6. Method for operating an asynchronous digital pipeline stage comprising: providing a reset signal to the pipeline stage, providing an acknowledge signal to the pipeline stage, after the pipeline stage has assumed an initial state upon receipt of the reset signal, upon detection of an acknowledge signal provided by the pipeline stage, providing data to the pipeline stage.