WO2009050974A1 - Process for manufacturing ceramic multilayer substrate with cavity - Google Patents
Process for manufacturing ceramic multilayer substrate with cavity Download PDFInfo
- Publication number
- WO2009050974A1 WO2009050974A1 PCT/JP2008/066692 JP2008066692W WO2009050974A1 WO 2009050974 A1 WO2009050974 A1 WO 2009050974A1 JP 2008066692 W JP2008066692 W JP 2008066692W WO 2009050974 A1 WO2009050974 A1 WO 2009050974A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cavity
- base material
- multilayer substrate
- layer
- material layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/4807—Ceramic parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15157—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09127—PCB or component having an integral separable or breakable part
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0264—Peeling insulating layer, e.g. foil, or separating mask
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
- H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Abstract
A process for manufacturing a ceramic multilayer substrate with cavity, in which the production cost for cavity formation can be reduced. (1) In the forming of a composite laminate (11) by superimposing an unfired ceramic base material layer (12) and shrinkage suppressing layers (20,22) one upon another, the ceramic base material layer (12) at its portion destined for a cavity side face is provided with a void forming layer (16) and at its portion destined for a cavity bottom is provided with a peel layer (18). (2) The composite laminate (11) is fired while suppressing any facial-direction shrinkage by the shrinkage suppressing layers (20,22). When the ceramic base material layer (12) is sintered, multiple voids are formed by the void forming layer (16), and any spaces linking the voids with each other are formed by the ceramic base material layer (12). (3) When a ceramic multilayer substrate is taken out from the composite laminate (11) after the firing, any portions remaining in cavity are removed with the spaces and the peel layer (18) as borders.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009538012A JP4888564B2 (en) | 2007-10-17 | 2008-09-17 | Manufacturing method of ceramic multilayer substrate with cavity |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007270612 | 2007-10-17 | ||
JP2007-270612 | 2007-10-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009050974A1 true WO2009050974A1 (en) | 2009-04-23 |
Family
ID=40567250
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/066692 WO2009050974A1 (en) | 2007-10-17 | 2008-09-17 | Process for manufacturing ceramic multilayer substrate with cavity |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP4888564B2 (en) |
WO (1) | WO2009050974A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11387182B2 (en) * | 2018-01-29 | 2022-07-12 | Anhui Anuki Technologies Co., Ltd. | Module structure and method for manufacturing the module structure |
EP4132237A3 (en) * | 2021-08-04 | 2023-05-31 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Manufacturing component carrier with cavity by trimming poorly adhesive structure before removing stack material |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08245268A (en) * | 1995-03-07 | 1996-09-24 | Sumitomo Metal Ind Ltd | Method for sintering glass ceramic laminate |
JP2007059863A (en) * | 2005-07-26 | 2007-03-08 | Tdk Corp | Multilayer ceramic substrate and its manufacture |
WO2008018227A1 (en) * | 2006-08-07 | 2008-02-14 | Murata Manufacturing Co., Ltd. | Method of producing multilayer ceramic substrate |
-
2008
- 2008-09-17 JP JP2009538012A patent/JP4888564B2/en active Active
- 2008-09-17 WO PCT/JP2008/066692 patent/WO2009050974A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08245268A (en) * | 1995-03-07 | 1996-09-24 | Sumitomo Metal Ind Ltd | Method for sintering glass ceramic laminate |
JP2007059863A (en) * | 2005-07-26 | 2007-03-08 | Tdk Corp | Multilayer ceramic substrate and its manufacture |
WO2008018227A1 (en) * | 2006-08-07 | 2008-02-14 | Murata Manufacturing Co., Ltd. | Method of producing multilayer ceramic substrate |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11387182B2 (en) * | 2018-01-29 | 2022-07-12 | Anhui Anuki Technologies Co., Ltd. | Module structure and method for manufacturing the module structure |
EP4132237A3 (en) * | 2021-08-04 | 2023-05-31 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Manufacturing component carrier with cavity by trimming poorly adhesive structure before removing stack material |
Also Published As
Publication number | Publication date |
---|---|
JP4888564B2 (en) | 2012-02-29 |
JPWO2009050974A1 (en) | 2011-03-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2051570A4 (en) | Method of producing multilayer ceramic substrate | |
TW200644757A (en) | Multilayer ceramic substrate and production method thereof | |
WO2007115839A3 (en) | Layered thermal barrier coating with a high porosity, and a component | |
TW200629491A (en) | Wiring substrate and the manufacturing method of the same | |
WO2009069398A1 (en) | Ceramic composite multilayer substrate, method for manufacturing ceramic composite multilayer substrate and electronic component | |
EP2023701A4 (en) | Method for manufacturing ceramic multilayer substrate | |
TW200503601A (en) | Monolithic ceramic electronic component and method for manufacturing monolithic ceramic electronic component | |
WO2008146487A1 (en) | Circuit board and method for manufacturing the same | |
EP1272020A4 (en) | Method of manufacturing ceramic multi-layer substrate, and unbaked composite laminated body | |
EP1061569A3 (en) | Method for manufacturing ceramic substrate and non-fired ceramic substrate | |
EP1881751A4 (en) | Ceramic multilayer board | |
EP2026642A4 (en) | Multilayer ceramic substrate, method for producing the same and electronic component | |
EP2404754A3 (en) | Multilayer ceramic substrate | |
WO2009014017A1 (en) | Multilayer ceramic board and process for manufacturing the same | |
CN103460818A (en) | Multilayer ceramic substrate | |
GB2392312B (en) | Method for manufacturing ceramic multilayer substrate and green composite laminate | |
WO2008126661A1 (en) | Multilayer ceramic substrate and process for producing the same | |
TW200713361A (en) | Method of manufacturing multilayer capacitor and multilayer capacitor | |
JP2007043050A5 (en) | ||
WO2009050974A1 (en) | Process for manufacturing ceramic multilayer substrate with cavity | |
JP2006261390A5 (en) | ||
WO2007100621A3 (en) | Process of manufacturing a multi-layer device and device manufactured thereby | |
WO2013021354A3 (en) | Ceramic tile for combustion chambers lining, in particular of gas turbines, and manufacturing method thereof | |
ATE535946T1 (en) | PIEZOCERAMIC MULTI-LAYER ACTUATOR AND METHOD FOR PRODUCING A PIEZOCERAMIC MULTI-LAYER ACTUATOR | |
CN101668620B (en) | Multilayer ceramic substrate, method for manufacturing multilayer ceramic substrate and method for suppressing warpage of multilayer ceramic substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08839701 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009538012 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 08839701 Country of ref document: EP Kind code of ref document: A1 |