WO2009034800A1 - 剰余乗算処理装置 - Google Patents

剰余乗算処理装置 Download PDF

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Publication number
WO2009034800A1
WO2009034800A1 PCT/JP2008/064352 JP2008064352W WO2009034800A1 WO 2009034800 A1 WO2009034800 A1 WO 2009034800A1 JP 2008064352 W JP2008064352 W JP 2008064352W WO 2009034800 A1 WO2009034800 A1 WO 2009034800A1
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WO
WIPO (PCT)
Prior art keywords
remainder
multiplier
processing device
data
multiplication
Prior art date
Application number
PCT/JP2008/064352
Other languages
English (en)
French (fr)
Inventor
Masayuki Yoshino
Katsuyuki Okeya
Vuillaume Camille
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO2009034800A1 publication Critical patent/WO2009034800A1/ja

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/722—Modular multiplication

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Error Detection And Correction (AREA)

Abstract

　剰余乗算器を用い、剰余乗算器が処理可能なビット長を越えるデータの剰余乗算を処理する剰余乗算処理装置である。剰余乗算処理装置において、剰余乗算器１１３が処理できるビット長にあわせ、剰余乗算の対象データを分解する。剰余乗算器１１３の出力結果を用いて作成した、剰余乗算の計算に必要なデータを記憶装置１２３へ格納する。記憶領域の利用量が最小となるよう、一時データを逐次的に特定の記憶領域へ蓄積する。記憶領域へ蓄積された一時データを合わせ、剰余乗算器１１３が処理できるビット長を越えた剰余乗算の解を作成する。
PCT/JP2008/064352 2007-09-14 2008-08-08 剰余乗算処理装置 WO2009034800A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-238715 2007-09-14
JP2007238715A JP2011007820A (ja) 2007-09-14 2007-09-14 剰余乗算処理装置

Publications (1)

Publication Number Publication Date
WO2009034800A1 true WO2009034800A1 (ja) 2009-03-19

Family

ID=40451810

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/064352 WO2009034800A1 (ja) 2007-09-14 2008-08-08 剰余乗算処理装置

Country Status (2)

Country Link
JP (1) JP2011007820A (ja)
WO (1) WO2009034800A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011232404A (ja) * 2010-04-23 2011-11-17 Nec Soft Ltd 剰余乗算演算装置、剰余乗算演算方法、剰余乗算演算プログラム
JP2020140120A (ja) * 2019-02-28 2020-09-03 ルネサスエレクトロニクス株式会社 演算処理方法、演算処理装置、及び半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1515226A2 (de) * 2003-09-10 2005-03-16 Giesecke & Devrient GmbH Modulare Multiplikation
US20050149595A1 (en) * 2002-04-29 2005-07-07 Infineon Technologies Ag Apparatus and method for calculating a result of a modular multiplication
JP2007503036A (ja) * 2003-08-21 2007-02-15 ジェムプリュス モジュラ乗算を行うための方法、および２ｎビットの数を使用してユークリッド乗算を行うための方法
US20070100926A1 (en) * 2005-10-28 2007-05-03 Infineon Technologies Ag Device and method for calculating a multiplication addition operation and for calculating a result of a modular multiplication
JP2007212701A (ja) * 2006-02-09 2007-08-23 Renesas Technology Corp 剰余演算処理装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050149595A1 (en) * 2002-04-29 2005-07-07 Infineon Technologies Ag Apparatus and method for calculating a result of a modular multiplication
JP2007503036A (ja) * 2003-08-21 2007-02-15 ジェムプリュス モジュラ乗算を行うための方法、および２ｎビットの数を使用してユークリッド乗算を行うための方法
EP1515226A2 (de) * 2003-09-10 2005-03-16 Giesecke & Devrient GmbH Modulare Multiplikation
US20070100926A1 (en) * 2005-10-28 2007-05-03 Infineon Technologies Ag Device and method for calculating a multiplication addition operation and for calculating a result of a modular multiplication
JP2007212701A (ja) * 2006-02-09 2007-08-23 Renesas Technology Corp 剰余演算処理装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MASAYUKI YOSHINO ET AL.: "Coprocessor no Nibai no Bitlength o Motsu Montgomery Josan", TECHNICAL REPORT OF IEICE ISEC 2006-21, vol. 106, no. 175, 13 July 2006 (2006-07-13), pages 87 - 94 *
WIELAND FISCHER,JEAN-PIERRE SEIFERT: "Increasing the Bitlength of a Crypto-Coprocessor,Cryptographic Hardware and Embedded Systems -CHES 2002", LNCS 2523, 2003, pages 71 - 81 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011232404A (ja) * 2010-04-23 2011-11-17 Nec Soft Ltd 剰余乗算演算装置、剰余乗算演算方法、剰余乗算演算プログラム
JP2020140120A (ja) * 2019-02-28 2020-09-03 ルネサスエレクトロニクス株式会社 演算処理方法、演算処理装置、及び半導体装置
JP7286239B2 (ja) 2019-02-28 2023-06-05 ルネサスエレクトロニクス株式会社 演算処理方法、演算処理装置、及び半導体装置

Also Published As

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JP2011007820A (ja) 2011-01-13

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